tjh.dev
Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
1* Qualcomm PCI express root complex
2
3- compatible:
4 Usage: required
5 Value type: <stringlist>
6 Definition: Value should contain
7 - "qcom,pcie-ipq8064" for ipq8064
8 - "qcom,pcie-apq8064" for apq8064
9 - "qcom,pcie-apq8084" for apq8084
10 - "qcom,pcie-msm8996" for msm8996 or apq8096
11 - "qcom,pcie-ipq4019" for ipq4019
12 - "qcom,pcie-ipq8074" for ipq8074
13
14- reg:
15 Usage: required
16 Value type: <prop-encoded-array>
17 Definition: Register ranges as listed in the reg-names property
18
19- reg-names:
20 Usage: required
21 Value type: <stringlist>
22 Definition: Must include the following entries
23 - "parf" Qualcomm specific registers
24 - "dbi" DesignWare PCIe registers
25 - "elbi" External local bus interface registers
26 - "config" PCIe configuration space
27
28- device_type:
29 Usage: required
30 Value type: <string>
31 Definition: Should be "pci". As specified in designware-pcie.txt
32
33- #address-cells:
34 Usage: required
35 Value type: <u32>
36 Definition: Should be 3. As specified in designware-pcie.txt
37
38- #size-cells:
39 Usage: required
40 Value type: <u32>
41 Definition: Should be 2. As specified in designware-pcie.txt
42
43- ranges:
44 Usage: required
45 Value type: <prop-encoded-array>
46 Definition: As specified in designware-pcie.txt
47
48- interrupts:
49 Usage: required
50 Value type: <prop-encoded-array>
51 Definition: MSI interrupt
52
53- interrupt-names:
54 Usage: required
55 Value type: <stringlist>
56 Definition: Should contain "msi"
57
58- #interrupt-cells:
59 Usage: required
60 Value type: <u32>
61 Definition: Should be 1. As specified in designware-pcie.txt
62
63- interrupt-map-mask:
64 Usage: required
65 Value type: <prop-encoded-array>
66 Definition: As specified in designware-pcie.txt
67
68- interrupt-map:
69 Usage: required
70 Value type: <prop-encoded-array>
71 Definition: As specified in designware-pcie.txt
72
73- clocks:
74 Usage: required
75 Value type: <prop-encoded-array>
76 Definition: List of phandle and clock specifier pairs as listed
77 in clock-names property
78
79- clock-names:
80 Usage: required
81 Value type: <stringlist>
82 Definition: Should contain the following entries
83 - "iface" Configuration AHB clock
84
85- clock-names:
86 Usage: required for ipq/apq8064
87 Value type: <stringlist>
88 Definition: Should contain the following entries
89 - "core" Clocks the pcie hw block
90 - "phy" Clocks the pcie PHY block
91- clock-names:
92 Usage: required for apq8084/ipq4019
93 Value type: <stringlist>
94 Definition: Should contain the following entries
95 - "aux" Auxiliary (AUX) clock
96 - "bus_master" Master AXI clock
97 - "bus_slave" Slave AXI clock
98
99- clock-names:
100 Usage: required for msm8996/apq8096
101 Value type: <stringlist>
102 Definition: Should contain the following entries
103 - "pipe" Pipe Clock driving internal logic
104 - "aux" Auxiliary (AUX) clock
105 - "cfg" Configuration clock
106 - "bus_master" Master AXI clock
107 - "bus_slave" Slave AXI clock
108
109- clock-names:
110 Usage: required for ipq8074
111 Value type: <stringlist>
112 Definition: Should contain the following entries
113 - "iface" PCIe to SysNOC BIU clock
114 - "axi_m" AXI Master clock
115 - "axi_s" AXI Slave clock
116 - "ahb" AHB clock
117 - "aux" Auxiliary clock
118
119- resets:
120 Usage: required
121 Value type: <prop-encoded-array>
122 Definition: List of phandle and reset specifier pairs as listed
123 in reset-names property
124
125- reset-names:
126 Usage: required for ipq/apq8064
127 Value type: <stringlist>
128 Definition: Should contain the following entries
129 - "axi" AXI reset
130 - "ahb" AHB reset
131 - "por" POR reset
132 - "pci" PCI reset
133 - "phy" PHY reset
134
135- reset-names:
136 Usage: required for apq8084
137 Value type: <stringlist>
138 Definition: Should contain the following entries
139 - "core" Core reset
140
141- reset-names:
142 Usage: required for ipq/apq8064
143 Value type: <stringlist>
144 Definition: Should contain the following entries
145 - "axi_m" AXI master reset
146 - "axi_s" AXI slave reset
147 - "pipe" PIPE reset
148 - "axi_m_vmid" VMID reset
149 - "axi_s_xpu" XPU reset
150 - "parf" PARF reset
151 - "phy" PHY reset
152 - "axi_m_sticky" AXI sticky reset
153 - "pipe_sticky" PIPE sticky reset
154 - "pwr" PWR reset
155 - "ahb" AHB reset
156 - "phy_ahb" PHY AHB reset
157
158- reset-names:
159 Usage: required for ipq8074
160 Value type: <stringlist>
161 Definition: Should contain the following entries
162 - "pipe" PIPE reset
163 - "sleep" Sleep reset
164 - "sticky" Core Sticky reset
165 - "axi_m" AXI Master reset
166 - "axi_s" AXI Slave reset
167 - "ahb" AHB Reset
168 - "axi_m_sticky" AXI Master Sticky reset
169
170- power-domains:
171 Usage: required for apq8084 and msm8996/apq8096
172 Value type: <prop-encoded-array>
173 Definition: A phandle and power domain specifier pair to the
174 power domain which is responsible for collapsing
175 and restoring power to the peripheral
176
177- vdda-supply:
178 Usage: required
179 Value type: <phandle>
180 Definition: A phandle to the core analog power supply
181
182- vdda_phy-supply:
183 Usage: required for ipq/apq8064
184 Value type: <phandle>
185 Definition: A phandle to the analog power supply for PHY
186
187- vdda_refclk-supply:
188 Usage: required for ipq/apq8064
189 Value type: <phandle>
190 Definition: A phandle to the analog power supply for IC which generates
191 reference clock
192- vddpe-3v3-supply:
193 Usage: optional
194 Value type: <phandle>
195 Definition: A phandle to the PCIe endpoint power supply
196
197- phys:
198 Usage: required for apq8084
199 Value type: <phandle>
200 Definition: List of phandle(s) as listed in phy-names property
201
202- phy-names:
203 Usage: required for apq8084
204 Value type: <stringlist>
205 Definition: Should contain "pciephy"
206
207- <name>-gpios:
208 Usage: optional
209 Value type: <prop-encoded-array>
210 Definition: List of phandle and GPIO specifier pairs. Should contain
211 - "perst-gpios" PCIe endpoint reset signal line
212 - "wake-gpios" PCIe endpoint wake signal line
213
214* Example for ipq/apq8064
215 pcie@1b500000 {
216 compatible = "qcom,pcie-apq8064", "qcom,pcie-ipq8064", "snps,dw-pcie";
217 reg = <0x1b500000 0x1000
218 0x1b502000 0x80
219 0x1b600000 0x100
220 0x0ff00000 0x100000>;
221 reg-names = "dbi", "elbi", "parf", "config";
222 device_type = "pci";
223 linux,pci-domain = <0>;
224 bus-range = <0x00 0xff>;
225 num-lanes = <1>;
226 #address-cells = <3>;
227 #size-cells = <2>;
228 ranges = <0x81000000 0 0 0x0fe00000 0 0x00100000 /* I/O */
229 0x82000000 0 0 0x08000000 0 0x07e00000>; /* memory */
230 interrupts = <GIC_SPI 238 IRQ_TYPE_NONE>;
231 interrupt-names = "msi";
232 #interrupt-cells = <1>;
233 interrupt-map-mask = <0 0 0 0x7>;
234 interrupt-map = <0 0 0 1 &intc 0 36 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
235 <0 0 0 2 &intc 0 37 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
236 <0 0 0 3 &intc 0 38 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
237 <0 0 0 4 &intc 0 39 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
238 clocks = <&gcc PCIE_A_CLK>,
239 <&gcc PCIE_H_CLK>,
240 <&gcc PCIE_PHY_CLK>;
241 clock-names = "core", "iface", "phy";
242 resets = <&gcc PCIE_ACLK_RESET>,
243 <&gcc PCIE_HCLK_RESET>,
244 <&gcc PCIE_POR_RESET>,
245 <&gcc PCIE_PCI_RESET>,
246 <&gcc PCIE_PHY_RESET>;
247 reset-names = "axi", "ahb", "por", "pci", "phy";
248 pinctrl-0 = <&pcie_pins_default>;
249 pinctrl-names = "default";
250 };
251
252* Example for apq8084
253 pcie0@fc520000 {
254 compatible = "qcom,pcie-apq8084", "snps,dw-pcie";
255 reg = <0xfc520000 0x2000>,
256 <0xff000000 0x1000>,
257 <0xff001000 0x1000>,
258 <0xff002000 0x2000>;
259 reg-names = "parf", "dbi", "elbi", "config";
260 device_type = "pci";
261 linux,pci-domain = <0>;
262 bus-range = <0x00 0xff>;
263 num-lanes = <1>;
264 #address-cells = <3>;
265 #size-cells = <2>;
266 ranges = <0x81000000 0 0 0xff200000 0 0x00100000 /* I/O */
267 0x82000000 0 0x00300000 0xff300000 0 0x00d00000>; /* memory */
268 interrupts = <GIC_SPI 243 IRQ_TYPE_NONE>;
269 interrupt-names = "msi";
270 #interrupt-cells = <1>;
271 interrupt-map-mask = <0 0 0 0x7>;
272 interrupt-map = <0 0 0 1 &intc 0 244 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
273 <0 0 0 2 &intc 0 245 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
274 <0 0 0 3 &intc 0 247 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
275 <0 0 0 4 &intc 0 248 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
276 clocks = <&gcc GCC_PCIE_0_CFG_AHB_CLK>,
277 <&gcc GCC_PCIE_0_MSTR_AXI_CLK>,
278 <&gcc GCC_PCIE_0_SLV_AXI_CLK>,
279 <&gcc GCC_PCIE_0_AUX_CLK>;
280 clock-names = "iface", "master_bus", "slave_bus", "aux";
281 resets = <&gcc GCC_PCIE_0_BCR>;
282 reset-names = "core";
283 power-domains = <&gcc PCIE0_GDSC>;
284 vdda-supply = <&pma8084_l3>;
285 phys = <&pciephy0>;
286 phy-names = "pciephy";
287 perst-gpio = <&tlmm 70 GPIO_ACTIVE_LOW>;
288 pinctrl-0 = <&pcie0_pins_default>;
289 pinctrl-names = "default";
290 };