tjh.dev
Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
1// SPDX-License-Identifier: GPL-2.0
2/*
3 * RNG driver for Exynos TRNGs
4 *
5 * Author: Łukasz Stelmach <l.stelmach@samsung.com>
6 *
7 * Copyright 2017 (c) Samsung Electronics Software, Inc.
8 *
9 * Based on the Exynos PRNG driver drivers/crypto/exynos-rng by
10 * Krzysztof Kozłowski <krzk@kernel.org>
11 */
12
13#include <linux/clk.h>
14#include <linux/crypto.h>
15#include <linux/delay.h>
16#include <linux/err.h>
17#include <linux/hw_random.h>
18#include <linux/io.h>
19#include <linux/iopoll.h>
20#include <linux/kernel.h>
21#include <linux/module.h>
22#include <linux/platform_device.h>
23#include <linux/pm_runtime.h>
24
25#define EXYNOS_TRNG_CLKDIV (0x0)
26
27#define EXYNOS_TRNG_CTRL (0x20)
28#define EXYNOS_TRNG_CTRL_RNGEN BIT(31)
29
30#define EXYNOS_TRNG_POST_CTRL (0x30)
31#define EXYNOS_TRNG_ONLINE_CTRL (0x40)
32#define EXYNOS_TRNG_ONLINE_STAT (0x44)
33#define EXYNOS_TRNG_ONLINE_MAXCHI2 (0x48)
34#define EXYNOS_TRNG_FIFO_CTRL (0x50)
35#define EXYNOS_TRNG_FIFO_0 (0x80)
36#define EXYNOS_TRNG_FIFO_1 (0x84)
37#define EXYNOS_TRNG_FIFO_2 (0x88)
38#define EXYNOS_TRNG_FIFO_3 (0x8c)
39#define EXYNOS_TRNG_FIFO_4 (0x90)
40#define EXYNOS_TRNG_FIFO_5 (0x94)
41#define EXYNOS_TRNG_FIFO_6 (0x98)
42#define EXYNOS_TRNG_FIFO_7 (0x9c)
43#define EXYNOS_TRNG_FIFO_LEN (8)
44#define EXYNOS_TRNG_CLOCK_RATE (500000)
45
46
47struct exynos_trng_dev {
48 struct device *dev;
49 void __iomem *mem;
50 struct clk *clk;
51 struct hwrng rng;
52};
53
54static int exynos_trng_do_read(struct hwrng *rng, void *data, size_t max,
55 bool wait)
56{
57 struct exynos_trng_dev *trng;
58 int val;
59
60 max = min_t(size_t, max, (EXYNOS_TRNG_FIFO_LEN * 4));
61
62 trng = (struct exynos_trng_dev *)rng->priv;
63
64 writel_relaxed(max * 8, trng->mem + EXYNOS_TRNG_FIFO_CTRL);
65 val = readl_poll_timeout(trng->mem + EXYNOS_TRNG_FIFO_CTRL, val,
66 val == 0, 200, 1000000);
67 if (val < 0)
68 return val;
69
70 memcpy_fromio(data, trng->mem + EXYNOS_TRNG_FIFO_0, max);
71
72 return max;
73}
74
75static int exynos_trng_init(struct hwrng *rng)
76{
77 struct exynos_trng_dev *trng = (struct exynos_trng_dev *)rng->priv;
78 unsigned long sss_rate;
79 u32 val;
80
81 sss_rate = clk_get_rate(trng->clk);
82
83 /*
84 * For most TRNG circuits the clock frequency of under 500 kHz
85 * is safe.
86 */
87 val = sss_rate / (EXYNOS_TRNG_CLOCK_RATE * 2);
88 if (val > 0x7fff) {
89 dev_err(trng->dev, "clock divider too large: %d", val);
90 return -ERANGE;
91 }
92 val = val << 1;
93 writel_relaxed(val, trng->mem + EXYNOS_TRNG_CLKDIV);
94
95 /* Enable the generator. */
96 val = EXYNOS_TRNG_CTRL_RNGEN;
97 writel_relaxed(val, trng->mem + EXYNOS_TRNG_CTRL);
98
99 /*
100 * Disable post-processing. /dev/hwrng is supposed to deliver
101 * unprocessed data.
102 */
103 writel_relaxed(0, trng->mem + EXYNOS_TRNG_POST_CTRL);
104
105 return 0;
106}
107
108static int exynos_trng_probe(struct platform_device *pdev)
109{
110 struct exynos_trng_dev *trng;
111 struct resource *res;
112 int ret = -ENOMEM;
113
114 trng = devm_kzalloc(&pdev->dev, sizeof(*trng), GFP_KERNEL);
115 if (!trng)
116 return ret;
117
118 trng->rng.name = devm_kstrdup(&pdev->dev, dev_name(&pdev->dev),
119 GFP_KERNEL);
120 if (!trng->rng.name)
121 return ret;
122
123 trng->rng.init = exynos_trng_init;
124 trng->rng.read = exynos_trng_do_read;
125 trng->rng.priv = (unsigned long) trng;
126
127 platform_set_drvdata(pdev, trng);
128 trng->dev = &pdev->dev;
129
130 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
131 trng->mem = devm_ioremap_resource(&pdev->dev, res);
132 if (IS_ERR(trng->mem))
133 return PTR_ERR(trng->mem);
134
135 pm_runtime_enable(&pdev->dev);
136 ret = pm_runtime_get_sync(&pdev->dev);
137 if (ret < 0) {
138 dev_err(&pdev->dev, "Could not get runtime PM.\n");
139 goto err_pm_get;
140 }
141
142 trng->clk = devm_clk_get(&pdev->dev, "secss");
143 if (IS_ERR(trng->clk)) {
144 ret = PTR_ERR(trng->clk);
145 dev_err(&pdev->dev, "Could not get clock.\n");
146 goto err_clock;
147 }
148
149 ret = clk_prepare_enable(trng->clk);
150 if (ret) {
151 dev_err(&pdev->dev, "Could not enable the clk.\n");
152 goto err_clock;
153 }
154
155 ret = hwrng_register(&trng->rng);
156 if (ret) {
157 dev_err(&pdev->dev, "Could not register hwrng device.\n");
158 goto err_register;
159 }
160
161 dev_info(&pdev->dev, "Exynos True Random Number Generator.\n");
162
163 return 0;
164
165err_register:
166 clk_disable_unprepare(trng->clk);
167
168err_clock:
169 pm_runtime_put_sync(&pdev->dev);
170
171err_pm_get:
172 pm_runtime_disable(&pdev->dev);
173
174 return ret;
175}
176
177static int exynos_trng_remove(struct platform_device *pdev)
178{
179 struct exynos_trng_dev *trng = platform_get_drvdata(pdev);
180
181 hwrng_unregister(&trng->rng);
182 clk_disable_unprepare(trng->clk);
183
184 pm_runtime_put_sync(&pdev->dev);
185 pm_runtime_disable(&pdev->dev);
186
187 return 0;
188}
189
190static int __maybe_unused exynos_trng_suspend(struct device *dev)
191{
192 pm_runtime_put_sync(dev);
193
194 return 0;
195}
196
197static int __maybe_unused exynos_trng_resume(struct device *dev)
198{
199 int ret;
200
201 ret = pm_runtime_get_sync(dev);
202 if (ret < 0) {
203 dev_err(dev, "Could not get runtime PM.\n");
204 pm_runtime_put_noidle(dev);
205 return ret;
206 }
207
208 return 0;
209}
210
211static SIMPLE_DEV_PM_OPS(exynos_trng_pm_ops, exynos_trng_suspend,
212 exynos_trng_resume);
213
214static const struct of_device_id exynos_trng_dt_match[] = {
215 {
216 .compatible = "samsung,exynos5250-trng",
217 },
218 { },
219};
220MODULE_DEVICE_TABLE(of, exynos_trng_dt_match);
221
222static struct platform_driver exynos_trng_driver = {
223 .driver = {
224 .name = "exynos-trng",
225 .pm = &exynos_trng_pm_ops,
226 .of_match_table = exynos_trng_dt_match,
227 },
228 .probe = exynos_trng_probe,
229 .remove = exynos_trng_remove,
230};
231
232module_platform_driver(exynos_trng_driver);
233MODULE_AUTHOR("Łukasz Stelmach");
234MODULE_DESCRIPTION("H/W TRNG driver for Exynos chips");
235MODULE_LICENSE("GPL v2");