tjh.dev
Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
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linux
1/*
2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * Authors: Dave Airlie
25 * Alex Deucher
26 * Jerome Glisse
27 */
28#ifndef __AMDGPU_OBJECT_H__
29#define __AMDGPU_OBJECT_H__
30
31#include <drm/amdgpu_drm.h>
32#include "amdgpu.h"
33
34#define AMDGPU_BO_INVALID_OFFSET LONG_MAX
35
36struct amdgpu_bo_param {
37 unsigned long size;
38 int byte_align;
39 u32 domain;
40 u32 preferred_domain;
41 u64 flags;
42 enum ttm_bo_type type;
43 struct reservation_object *resv;
44};
45
46/* bo virtual addresses in a vm */
47struct amdgpu_bo_va_mapping {
48 struct amdgpu_bo_va *bo_va;
49 struct list_head list;
50 struct rb_node rb;
51 uint64_t start;
52 uint64_t last;
53 uint64_t __subtree_last;
54 uint64_t offset;
55 uint64_t flags;
56};
57
58/* User space allocated BO in a VM */
59struct amdgpu_bo_va {
60 struct amdgpu_vm_bo_base base;
61
62 /* protected by bo being reserved */
63 unsigned ref_count;
64
65 /* all other members protected by the VM PD being reserved */
66 struct dma_fence *last_pt_update;
67
68 /* mappings for this bo_va */
69 struct list_head invalids;
70 struct list_head valids;
71
72 /* If the mappings are cleared or filled */
73 bool cleared;
74};
75
76struct amdgpu_bo {
77 /* Protected by tbo.reserved */
78 u32 preferred_domains;
79 u32 allowed_domains;
80 struct ttm_place placements[AMDGPU_GEM_DOMAIN_MAX + 1];
81 struct ttm_placement placement;
82 struct ttm_buffer_object tbo;
83 struct ttm_bo_kmap_obj kmap;
84 u64 flags;
85 unsigned pin_count;
86 u64 tiling_flags;
87 u64 metadata_flags;
88 void *metadata;
89 u32 metadata_size;
90 unsigned prime_shared_count;
91 /* list of all virtual address to which this bo is associated to */
92 struct list_head va;
93 /* Constant after initialization */
94 struct drm_gem_object gem_base;
95 struct amdgpu_bo *parent;
96 struct amdgpu_bo *shadow;
97
98 struct ttm_bo_kmap_obj dma_buf_vmap;
99 struct amdgpu_mn *mn;
100
101 union {
102 struct list_head mn_list;
103 struct list_head shadow_list;
104 };
105
106 struct kgd_mem *kfd_bo;
107};
108
109static inline struct amdgpu_bo *ttm_to_amdgpu_bo(struct ttm_buffer_object *tbo)
110{
111 return container_of(tbo, struct amdgpu_bo, tbo);
112}
113
114/**
115 * amdgpu_mem_type_to_domain - return domain corresponding to mem_type
116 * @mem_type: ttm memory type
117 *
118 * Returns corresponding domain of the ttm mem_type
119 */
120static inline unsigned amdgpu_mem_type_to_domain(u32 mem_type)
121{
122 switch (mem_type) {
123 case TTM_PL_VRAM:
124 return AMDGPU_GEM_DOMAIN_VRAM;
125 case TTM_PL_TT:
126 return AMDGPU_GEM_DOMAIN_GTT;
127 case TTM_PL_SYSTEM:
128 return AMDGPU_GEM_DOMAIN_CPU;
129 case AMDGPU_PL_GDS:
130 return AMDGPU_GEM_DOMAIN_GDS;
131 case AMDGPU_PL_GWS:
132 return AMDGPU_GEM_DOMAIN_GWS;
133 case AMDGPU_PL_OA:
134 return AMDGPU_GEM_DOMAIN_OA;
135 default:
136 break;
137 }
138 return 0;
139}
140
141/**
142 * amdgpu_bo_reserve - reserve bo
143 * @bo: bo structure
144 * @no_intr: don't return -ERESTARTSYS on pending signal
145 *
146 * Returns:
147 * -ERESTARTSYS: A wait for the buffer to become unreserved was interrupted by
148 * a signal. Release all buffer reservations and return to user-space.
149 */
150static inline int amdgpu_bo_reserve(struct amdgpu_bo *bo, bool no_intr)
151{
152 struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev);
153 int r;
154
155 r = ttm_bo_reserve(&bo->tbo, !no_intr, false, NULL);
156 if (unlikely(r != 0)) {
157 if (r != -ERESTARTSYS)
158 dev_err(adev->dev, "%p reserve failed\n", bo);
159 return r;
160 }
161 return 0;
162}
163
164static inline void amdgpu_bo_unreserve(struct amdgpu_bo *bo)
165{
166 ttm_bo_unreserve(&bo->tbo);
167}
168
169static inline unsigned long amdgpu_bo_size(struct amdgpu_bo *bo)
170{
171 return bo->tbo.num_pages << PAGE_SHIFT;
172}
173
174static inline unsigned amdgpu_bo_ngpu_pages(struct amdgpu_bo *bo)
175{
176 return (bo->tbo.num_pages << PAGE_SHIFT) / AMDGPU_GPU_PAGE_SIZE;
177}
178
179static inline unsigned amdgpu_bo_gpu_page_alignment(struct amdgpu_bo *bo)
180{
181 return (bo->tbo.mem.page_alignment << PAGE_SHIFT) / AMDGPU_GPU_PAGE_SIZE;
182}
183
184/**
185 * amdgpu_bo_mmap_offset - return mmap offset of bo
186 * @bo: amdgpu object for which we query the offset
187 *
188 * Returns mmap offset of the object.
189 */
190static inline u64 amdgpu_bo_mmap_offset(struct amdgpu_bo *bo)
191{
192 return drm_vma_node_offset_addr(&bo->tbo.vma_node);
193}
194
195/**
196 * amdgpu_bo_gpu_accessible - return whether the bo is currently in memory that
197 * is accessible to the GPU.
198 */
199static inline bool amdgpu_bo_gpu_accessible(struct amdgpu_bo *bo)
200{
201 switch (bo->tbo.mem.mem_type) {
202 case TTM_PL_TT: return amdgpu_gtt_mgr_has_gart_addr(&bo->tbo.mem);
203 case TTM_PL_VRAM: return true;
204 default: return false;
205 }
206}
207
208/**
209 * amdgpu_bo_in_cpu_visible_vram - check if BO is (partly) in visible VRAM
210 */
211static inline bool amdgpu_bo_in_cpu_visible_vram(struct amdgpu_bo *bo)
212{
213 struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev);
214 unsigned fpfn = adev->gmc.visible_vram_size >> PAGE_SHIFT;
215 struct drm_mm_node *node = bo->tbo.mem.mm_node;
216 unsigned long pages_left;
217
218 if (bo->tbo.mem.mem_type != TTM_PL_VRAM)
219 return false;
220
221 for (pages_left = bo->tbo.mem.num_pages; pages_left;
222 pages_left -= node->size, node++)
223 if (node->start < fpfn)
224 return true;
225
226 return false;
227}
228
229/**
230 * amdgpu_bo_explicit_sync - return whether the bo is explicitly synced
231 */
232static inline bool amdgpu_bo_explicit_sync(struct amdgpu_bo *bo)
233{
234 return bo->flags & AMDGPU_GEM_CREATE_EXPLICIT_SYNC;
235}
236
237int amdgpu_bo_create(struct amdgpu_device *adev,
238 struct amdgpu_bo_param *bp,
239 struct amdgpu_bo **bo_ptr);
240int amdgpu_bo_create_reserved(struct amdgpu_device *adev,
241 unsigned long size, int align,
242 u32 domain, struct amdgpu_bo **bo_ptr,
243 u64 *gpu_addr, void **cpu_addr);
244int amdgpu_bo_create_kernel(struct amdgpu_device *adev,
245 unsigned long size, int align,
246 u32 domain, struct amdgpu_bo **bo_ptr,
247 u64 *gpu_addr, void **cpu_addr);
248void amdgpu_bo_free_kernel(struct amdgpu_bo **bo, u64 *gpu_addr,
249 void **cpu_addr);
250int amdgpu_bo_kmap(struct amdgpu_bo *bo, void **ptr);
251void *amdgpu_bo_kptr(struct amdgpu_bo *bo);
252void amdgpu_bo_kunmap(struct amdgpu_bo *bo);
253struct amdgpu_bo *amdgpu_bo_ref(struct amdgpu_bo *bo);
254void amdgpu_bo_unref(struct amdgpu_bo **bo);
255int amdgpu_bo_pin(struct amdgpu_bo *bo, u32 domain, u64 *gpu_addr);
256int amdgpu_bo_pin_restricted(struct amdgpu_bo *bo, u32 domain,
257 u64 min_offset, u64 max_offset,
258 u64 *gpu_addr);
259int amdgpu_bo_unpin(struct amdgpu_bo *bo);
260int amdgpu_bo_evict_vram(struct amdgpu_device *adev);
261int amdgpu_bo_init(struct amdgpu_device *adev);
262int amdgpu_bo_late_init(struct amdgpu_device *adev);
263void amdgpu_bo_fini(struct amdgpu_device *adev);
264int amdgpu_bo_fbdev_mmap(struct amdgpu_bo *bo,
265 struct vm_area_struct *vma);
266int amdgpu_bo_set_tiling_flags(struct amdgpu_bo *bo, u64 tiling_flags);
267void amdgpu_bo_get_tiling_flags(struct amdgpu_bo *bo, u64 *tiling_flags);
268int amdgpu_bo_set_metadata (struct amdgpu_bo *bo, void *metadata,
269 uint32_t metadata_size, uint64_t flags);
270int amdgpu_bo_get_metadata(struct amdgpu_bo *bo, void *buffer,
271 size_t buffer_size, uint32_t *metadata_size,
272 uint64_t *flags);
273void amdgpu_bo_move_notify(struct ttm_buffer_object *bo,
274 bool evict,
275 struct ttm_mem_reg *new_mem);
276int amdgpu_bo_fault_reserve_notify(struct ttm_buffer_object *bo);
277void amdgpu_bo_fence(struct amdgpu_bo *bo, struct dma_fence *fence,
278 bool shared);
279u64 amdgpu_bo_gpu_offset(struct amdgpu_bo *bo);
280int amdgpu_bo_backup_to_shadow(struct amdgpu_device *adev,
281 struct amdgpu_ring *ring,
282 struct amdgpu_bo *bo,
283 struct reservation_object *resv,
284 struct dma_fence **fence, bool direct);
285int amdgpu_bo_validate(struct amdgpu_bo *bo);
286int amdgpu_bo_restore_from_shadow(struct amdgpu_device *adev,
287 struct amdgpu_ring *ring,
288 struct amdgpu_bo *bo,
289 struct reservation_object *resv,
290 struct dma_fence **fence,
291 bool direct);
292uint32_t amdgpu_bo_get_preferred_pin_domain(struct amdgpu_device *adev,
293 uint32_t domain);
294
295/*
296 * sub allocation
297 */
298
299static inline uint64_t amdgpu_sa_bo_gpu_addr(struct amdgpu_sa_bo *sa_bo)
300{
301 return sa_bo->manager->gpu_addr + sa_bo->soffset;
302}
303
304static inline void * amdgpu_sa_bo_cpu_addr(struct amdgpu_sa_bo *sa_bo)
305{
306 return sa_bo->manager->cpu_ptr + sa_bo->soffset;
307}
308
309int amdgpu_sa_bo_manager_init(struct amdgpu_device *adev,
310 struct amdgpu_sa_manager *sa_manager,
311 unsigned size, u32 align, u32 domain);
312void amdgpu_sa_bo_manager_fini(struct amdgpu_device *adev,
313 struct amdgpu_sa_manager *sa_manager);
314int amdgpu_sa_bo_manager_start(struct amdgpu_device *adev,
315 struct amdgpu_sa_manager *sa_manager);
316int amdgpu_sa_bo_new(struct amdgpu_sa_manager *sa_manager,
317 struct amdgpu_sa_bo **sa_bo,
318 unsigned size, unsigned align);
319void amdgpu_sa_bo_free(struct amdgpu_device *adev,
320 struct amdgpu_sa_bo **sa_bo,
321 struct dma_fence *fence);
322#if defined(CONFIG_DEBUG_FS)
323void amdgpu_sa_bo_dump_debug_info(struct amdgpu_sa_manager *sa_manager,
324 struct seq_file *m);
325#endif
326
327
328#endif