tjh.dev / kernel
Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
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kernel / drivers / phy / qualcomm / phy-qcom-qmp.c
at v4.18-rc1 1657 lines 54 kB view raw
1// SPDX-License-Identifier: GPL-2.0 2/* 3 * Copyright (c) 2017, The Linux Foundation. All rights reserved. 4 */ 5 6#include <linux/clk.h> 7#include <linux/clk-provider.h> 8#include <linux/delay.h> 9#include <linux/err.h> 10#include <linux/io.h> 11#include <linux/iopoll.h> 12#include <linux/kernel.h> 13#include <linux/module.h> 14#include <linux/of.h> 15#include <linux/of_device.h> 16#include <linux/of_address.h> 17#include <linux/phy/phy.h> 18#include <linux/platform_device.h> 19#include <linux/regulator/consumer.h> 20#include <linux/reset.h> 21#include <linux/slab.h> 22 23#include <dt-bindings/phy/phy.h> 24 25#include "phy-qcom-qmp.h" 26 27/* QPHY_SW_RESET bit */ 28#define SW_RESET BIT(0) 29/* QPHY_POWER_DOWN_CONTROL */ 30#define SW_PWRDN BIT(0) 31#define REFCLK_DRV_DSBL BIT(1) 32/* QPHY_START_CONTROL bits */ 33#define SERDES_START BIT(0) 34#define PCS_START BIT(1) 35#define PLL_READY_GATE_EN BIT(3) 36/* QPHY_PCS_STATUS bit */ 37#define PHYSTATUS BIT(6) 38/* QPHY_COM_PCS_READY_STATUS bit */ 39#define PCS_READY BIT(0) 40 41/* QPHY_V3_DP_COM_RESET_OVRD_CTRL register bits */ 42/* DP PHY soft reset */ 43#define SW_DPPHY_RESET BIT(0) 44/* mux to select DP PHY reset control, 0:HW control, 1: software reset */ 45#define SW_DPPHY_RESET_MUX BIT(1) 46/* USB3 PHY soft reset */ 47#define SW_USB3PHY_RESET BIT(2) 48/* mux to select USB3 PHY reset control, 0:HW control, 1: software reset */ 49#define SW_USB3PHY_RESET_MUX BIT(3) 50 51/* QPHY_V3_DP_COM_PHY_MODE_CTRL register bits */ 52#define USB3_MODE BIT(0) /* enables USB3 mode */ 53#define DP_MODE BIT(1) /* enables DP mode */ 54 55/* QPHY_PCS_AUTONOMOUS_MODE_CTRL register bits */ 56#define ARCVR_DTCT_EN BIT(0) 57#define ALFPS_DTCT_EN BIT(1) 58#define ARCVR_DTCT_EVENT_SEL BIT(4) 59 60/* QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR register bits */ 61#define IRQ_CLEAR BIT(0) 62 63/* QPHY_PCS_LFPS_RXTERM_IRQ_STATUS register bits */ 64#define RCVR_DETECT BIT(0) 65 66/* QPHY_V3_PCS_MISC_CLAMP_ENABLE register bits */ 67#define CLAMP_EN BIT(0) /* enables i/o clamp_n */ 68 69#define PHY_INIT_COMPLETE_TIMEOUT 1000 70#define POWER_DOWN_DELAY_US_MIN 10 71#define POWER_DOWN_DELAY_US_MAX 11 72 73#define MAX_PROP_NAME 32 74 75struct qmp_phy_init_tbl { 76 unsigned int offset; 77 unsigned int val; 78 /* 79 * register part of layout ? 80 * if yes, then offset gives index in the reg-layout 81 */ 82 int in_layout; 83}; 84 85#define QMP_PHY_INIT_CFG(o, v) \ 86 { \ 87 .offset = o, \ 88 .val = v, \ 89 } 90 91#define QMP_PHY_INIT_CFG_L(o, v) \ 92 { \ 93 .offset = o, \ 94 .val = v, \ 95 .in_layout = 1, \ 96 } 97 98/* set of registers with offsets different per-PHY */ 99enum qphy_reg_layout { 100 /* Common block control registers */ 101 QPHY_COM_SW_RESET, 102 QPHY_COM_POWER_DOWN_CONTROL, 103 QPHY_COM_START_CONTROL, 104 QPHY_COM_PCS_READY_STATUS, 105 /* PCS registers */ 106 QPHY_PLL_LOCK_CHK_DLY_TIME, 107 QPHY_FLL_CNTRL1, 108 QPHY_FLL_CNTRL2, 109 QPHY_FLL_CNT_VAL_L, 110 QPHY_FLL_CNT_VAL_H_TOL, 111 QPHY_FLL_MAN_CODE, 112 QPHY_SW_RESET, 113 QPHY_START_CTRL, 114 QPHY_PCS_READY_STATUS, 115 QPHY_PCS_AUTONOMOUS_MODE_CTRL, 116 QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR, 117 QPHY_PCS_LFPS_RXTERM_IRQ_STATUS, 118}; 119 120static const unsigned int pciephy_regs_layout[] = { 121 [QPHY_COM_SW_RESET] = 0x400, 122 [QPHY_COM_POWER_DOWN_CONTROL] = 0x404, 123 [QPHY_COM_START_CONTROL] = 0x408, 124 [QPHY_COM_PCS_READY_STATUS] = 0x448, 125 [QPHY_PLL_LOCK_CHK_DLY_TIME] = 0xa8, 126 [QPHY_FLL_CNTRL1] = 0xc4, 127 [QPHY_FLL_CNTRL2] = 0xc8, 128 [QPHY_FLL_CNT_VAL_L] = 0xcc, 129 [QPHY_FLL_CNT_VAL_H_TOL] = 0xd0, 130 [QPHY_FLL_MAN_CODE] = 0xd4, 131 [QPHY_SW_RESET] = 0x00, 132 [QPHY_START_CTRL] = 0x08, 133 [QPHY_PCS_READY_STATUS] = 0x174, 134}; 135 136static const unsigned int usb3phy_regs_layout[] = { 137 [QPHY_FLL_CNTRL1] = 0xc0, 138 [QPHY_FLL_CNTRL2] = 0xc4, 139 [QPHY_FLL_CNT_VAL_L] = 0xc8, 140 [QPHY_FLL_CNT_VAL_H_TOL] = 0xcc, 141 [QPHY_FLL_MAN_CODE] = 0xd0, 142 [QPHY_SW_RESET] = 0x00, 143 [QPHY_START_CTRL] = 0x08, 144 [QPHY_PCS_READY_STATUS] = 0x17c, 145 [QPHY_PCS_AUTONOMOUS_MODE_CTRL] = 0x0d4, 146 [QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR] = 0x0d8, 147 [QPHY_PCS_LFPS_RXTERM_IRQ_STATUS] = 0x178, 148}; 149 150static const unsigned int qmp_v3_usb3phy_regs_layout[] = { 151 [QPHY_SW_RESET] = 0x00, 152 [QPHY_START_CTRL] = 0x08, 153 [QPHY_PCS_READY_STATUS] = 0x174, 154 [QPHY_PCS_AUTONOMOUS_MODE_CTRL] = 0x0d8, 155 [QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR] = 0x0dc, 156 [QPHY_PCS_LFPS_RXTERM_IRQ_STATUS] = 0x170, 157}; 158 159static const struct qmp_phy_init_tbl msm8996_pcie_serdes_tbl[] = { 160 QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CLKBUFLR_EN, 0x1c), 161 QMP_PHY_INIT_CFG(QSERDES_COM_CLK_ENABLE1, 0x10), 162 QMP_PHY_INIT_CFG(QSERDES_COM_CLK_SELECT, 0x33), 163 QMP_PHY_INIT_CFG(QSERDES_COM_CMN_CONFIG, 0x06), 164 QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_EN, 0x42), 165 QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_MAP, 0x00), 166 QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_TIMER1, 0xff), 167 QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_TIMER2, 0x1f), 168 QMP_PHY_INIT_CFG(QSERDES_COM_HSCLK_SEL, 0x01), 169 QMP_PHY_INIT_CFG(QSERDES_COM_SVS_MODE_CLK_SEL, 0x01), 170 QMP_PHY_INIT_CFG(QSERDES_COM_CORE_CLK_EN, 0x00), 171 QMP_PHY_INIT_CFG(QSERDES_COM_CORECLK_DIV, 0x0a), 172 QMP_PHY_INIT_CFG(QSERDES_COM_BG_TIMER, 0x09), 173 QMP_PHY_INIT_CFG(QSERDES_COM_DEC_START_MODE0, 0x82), 174 QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START3_MODE0, 0x03), 175 QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START2_MODE0, 0x55), 176 QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START1_MODE0, 0x55), 177 QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE0, 0x00), 178 QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP2_MODE0, 0x1a), 179 QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP1_MODE0, 0x0a), 180 QMP_PHY_INIT_CFG(QSERDES_COM_CLK_SELECT, 0x33), 181 QMP_PHY_INIT_CFG(QSERDES_COM_SYS_CLK_CTRL, 0x02), 182 QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_BUF_ENABLE, 0x1f), 183 QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_EN_SEL, 0x04), 184 QMP_PHY_INIT_CFG(QSERDES_COM_CP_CTRL_MODE0, 0x0b), 185 QMP_PHY_INIT_CFG(QSERDES_COM_PLL_RCTRL_MODE0, 0x16), 186 QMP_PHY_INIT_CFG(QSERDES_COM_PLL_CCTRL_MODE0, 0x28), 187 QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN1_MODE0, 0x00), 188 QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN0_MODE0, 0x80), 189 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_EN_CENTER, 0x01), 190 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER1, 0x31), 191 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER2, 0x01), 192 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER1, 0x02), 193 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER2, 0x00), 194 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE1, 0x2f), 195 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE2, 0x19), 196 QMP_PHY_INIT_CFG(QSERDES_COM_RESCODE_DIV_NUM, 0x15), 197 QMP_PHY_INIT_CFG(QSERDES_COM_BG_TRIM, 0x0f), 198 QMP_PHY_INIT_CFG(QSERDES_COM_PLL_IVCO, 0x0f), 199 QMP_PHY_INIT_CFG(QSERDES_COM_CLK_EP_DIV, 0x19), 200 QMP_PHY_INIT_CFG(QSERDES_COM_CLK_ENABLE1, 0x10), 201 QMP_PHY_INIT_CFG(QSERDES_COM_HSCLK_SEL, 0x00), 202 QMP_PHY_INIT_CFG(QSERDES_COM_RESCODE_DIV_NUM, 0x40), 203}; 204 205static const struct qmp_phy_init_tbl msm8996_pcie_tx_tbl[] = { 206 QMP_PHY_INIT_CFG(QSERDES_TX_HIGHZ_TRANSCEIVEREN_BIAS_DRVR_EN, 0x45), 207 QMP_PHY_INIT_CFG(QSERDES_TX_LANE_MODE, 0x06), 208}; 209 210static const struct qmp_phy_init_tbl msm8996_pcie_rx_tbl[] = { 211 QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_ENABLES, 0x1c), 212 QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL2, 0x01), 213 QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL3, 0x00), 214 QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL4, 0xdb), 215 QMP_PHY_INIT_CFG(QSERDES_RX_RX_BAND, 0x18), 216 QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SO_GAIN, 0x04), 217 QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SO_GAIN_HALF, 0x04), 218 QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x4b), 219 QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_DEGLITCH_CNTRL, 0x14), 220 QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_LVL, 0x19), 221}; 222 223static const struct qmp_phy_init_tbl msm8996_pcie_pcs_tbl[] = { 224 QMP_PHY_INIT_CFG(QPHY_RX_IDLE_DTCT_CNTRL, 0x4c), 225 QMP_PHY_INIT_CFG(QPHY_PWRUP_RESET_DLY_TIME_AUXCLK, 0x00), 226 QMP_PHY_INIT_CFG(QPHY_LP_WAKEUP_DLY_TIME_AUXCLK, 0x01), 227 228 QMP_PHY_INIT_CFG_L(QPHY_PLL_LOCK_CHK_DLY_TIME, 0x05), 229 230 QMP_PHY_INIT_CFG(QPHY_ENDPOINT_REFCLK_DRIVE, 0x05), 231 QMP_PHY_INIT_CFG(QPHY_POWER_DOWN_CONTROL, 0x02), 232 QMP_PHY_INIT_CFG(QPHY_POWER_STATE_CONFIG4, 0x00), 233 QMP_PHY_INIT_CFG(QPHY_POWER_STATE_CONFIG1, 0xa3), 234 QMP_PHY_INIT_CFG(QPHY_TXDEEMPH_M3P5DB_V0, 0x0e), 235}; 236 237static const struct qmp_phy_init_tbl msm8996_usb3_serdes_tbl[] = { 238 QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_EN_SEL, 0x14), 239 QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CLKBUFLR_EN, 0x08), 240 QMP_PHY_INIT_CFG(QSERDES_COM_CLK_SELECT, 0x30), 241 QMP_PHY_INIT_CFG(QSERDES_COM_CMN_CONFIG, 0x06), 242 QMP_PHY_INIT_CFG(QSERDES_COM_SVS_MODE_CLK_SEL, 0x01), 243 QMP_PHY_INIT_CFG(QSERDES_COM_HSCLK_SEL, 0x00), 244 QMP_PHY_INIT_CFG(QSERDES_COM_BG_TRIM, 0x0f), 245 QMP_PHY_INIT_CFG(QSERDES_COM_PLL_IVCO, 0x0f), 246 QMP_PHY_INIT_CFG(QSERDES_COM_SYS_CLK_CTRL, 0x04), 247 /* PLL and Loop filter settings */ 248 QMP_PHY_INIT_CFG(QSERDES_COM_DEC_START_MODE0, 0x82), 249 QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START1_MODE0, 0x55), 250 QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START2_MODE0, 0x55), 251 QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START3_MODE0, 0x03), 252 QMP_PHY_INIT_CFG(QSERDES_COM_CP_CTRL_MODE0, 0x0b), 253 QMP_PHY_INIT_CFG(QSERDES_COM_PLL_RCTRL_MODE0, 0x16), 254 QMP_PHY_INIT_CFG(QSERDES_COM_PLL_CCTRL_MODE0, 0x28), 255 QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN0_MODE0, 0x80), 256 QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_CTRL, 0x00), 257 QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP1_MODE0, 0x15), 258 QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP2_MODE0, 0x34), 259 QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE0, 0x00), 260 QMP_PHY_INIT_CFG(QSERDES_COM_CORE_CLK_EN, 0x00), 261 QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_CFG, 0x00), 262 QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_MAP, 0x00), 263 QMP_PHY_INIT_CFG(QSERDES_COM_BG_TIMER, 0x0a), 264 /* SSC settings */ 265 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_EN_CENTER, 0x01), 266 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER1, 0x31), 267 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER2, 0x01), 268 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER1, 0x00), 269 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER2, 0x00), 270 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE1, 0xde), 271 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE2, 0x07), 272}; 273 274static const struct qmp_phy_init_tbl msm8996_usb3_tx_tbl[] = { 275 QMP_PHY_INIT_CFG(QSERDES_TX_HIGHZ_TRANSCEIVEREN_BIAS_DRVR_EN, 0x45), 276 QMP_PHY_INIT_CFG(QSERDES_TX_RCV_DETECT_LVL_2, 0x12), 277 QMP_PHY_INIT_CFG(QSERDES_TX_LANE_MODE, 0x06), 278}; 279 280static const struct qmp_phy_init_tbl msm8996_usb3_rx_tbl[] = { 281 QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_FASTLOCK_FO_GAIN, 0x0b), 282 QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SO_GAIN, 0x04), 283 QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL2, 0x02), 284 QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4c), 285 QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL4, 0xbb), 286 QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x77), 287 QMP_PHY_INIT_CFG(QSERDES_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80), 288 QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_CNTRL, 0x03), 289 QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_LVL, 0x18), 290 QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_DEGLITCH_CNTRL, 0x16), 291}; 292 293static const struct qmp_phy_init_tbl msm8996_usb3_pcs_tbl[] = { 294 /* FLL settings */ 295 QMP_PHY_INIT_CFG_L(QPHY_FLL_CNTRL2, 0x03), 296 QMP_PHY_INIT_CFG_L(QPHY_FLL_CNTRL1, 0x02), 297 QMP_PHY_INIT_CFG_L(QPHY_FLL_CNT_VAL_L, 0x09), 298 QMP_PHY_INIT_CFG_L(QPHY_FLL_CNT_VAL_H_TOL, 0x42), 299 QMP_PHY_INIT_CFG_L(QPHY_FLL_MAN_CODE, 0x85), 300 301 /* Lock Det settings */ 302 QMP_PHY_INIT_CFG(QPHY_LOCK_DETECT_CONFIG1, 0xd1), 303 QMP_PHY_INIT_CFG(QPHY_LOCK_DETECT_CONFIG2, 0x1f), 304 QMP_PHY_INIT_CFG(QPHY_LOCK_DETECT_CONFIG3, 0x47), 305 QMP_PHY_INIT_CFG(QPHY_POWER_STATE_CONFIG2, 0x08), 306}; 307 308static const struct qmp_phy_init_tbl ipq8074_pcie_serdes_tbl[] = { 309 QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CLKBUFLR_EN, 0x18), 310 QMP_PHY_INIT_CFG(QSERDES_COM_CLK_ENABLE1, 0x10), 311 QMP_PHY_INIT_CFG(QSERDES_COM_BG_TRIM, 0xf), 312 QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_EN, 0x1), 313 QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_MAP, 0x0), 314 QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_TIMER1, 0x1f), 315 QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_TIMER2, 0x3f), 316 QMP_PHY_INIT_CFG(QSERDES_COM_CMN_CONFIG, 0x6), 317 QMP_PHY_INIT_CFG(QSERDES_COM_PLL_IVCO, 0xf), 318 QMP_PHY_INIT_CFG(QSERDES_COM_HSCLK_SEL, 0x0), 319 QMP_PHY_INIT_CFG(QSERDES_COM_SVS_MODE_CLK_SEL, 0x1), 320 QMP_PHY_INIT_CFG(QSERDES_COM_CORE_CLK_EN, 0x20), 321 QMP_PHY_INIT_CFG(QSERDES_COM_CORECLK_DIV, 0xa), 322 QMP_PHY_INIT_CFG(QSERDES_COM_RESETSM_CNTRL, 0x20), 323 QMP_PHY_INIT_CFG(QSERDES_COM_BG_TIMER, 0xa), 324 QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_EN_SEL, 0xa), 325 QMP_PHY_INIT_CFG(QSERDES_COM_DEC_START_MODE0, 0x82), 326 QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START3_MODE0, 0x3), 327 QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START2_MODE0, 0x55), 328 QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START1_MODE0, 0x55), 329 QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE0, 0x0), 330 QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP2_MODE0, 0xD), 331 QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP1_MODE0, 0xD04), 332 QMP_PHY_INIT_CFG(QSERDES_COM_CLK_SELECT, 0x33), 333 QMP_PHY_INIT_CFG(QSERDES_COM_SYS_CLK_CTRL, 0x2), 334 QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_BUF_ENABLE, 0x1f), 335 QMP_PHY_INIT_CFG(QSERDES_COM_CP_CTRL_MODE0, 0xb), 336 QMP_PHY_INIT_CFG(QSERDES_COM_PLL_RCTRL_MODE0, 0x16), 337 QMP_PHY_INIT_CFG(QSERDES_COM_PLL_CCTRL_MODE0, 0x28), 338 QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN1_MODE0, 0x0), 339 QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN0_MODE0, 0x80), 340 QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CTRL_BY_PSM, 0x1), 341 QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_CTRL, 0xa), 342 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_EN_CENTER, 0x1), 343 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER1, 0x31), 344 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER2, 0x1), 345 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER1, 0x2), 346 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER2, 0x0), 347 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE1, 0x2f), 348 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE2, 0x19), 349 QMP_PHY_INIT_CFG(QSERDES_COM_CLK_EP_DIV, 0x19), 350 QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_CNTRL, 0x7), 351}; 352 353static const struct qmp_phy_init_tbl ipq8074_pcie_tx_tbl[] = { 354 QMP_PHY_INIT_CFG(QSERDES_TX_HIGHZ_TRANSCEIVEREN_BIAS_DRVR_EN, 0x45), 355 QMP_PHY_INIT_CFG(QSERDES_TX_LANE_MODE, 0x6), 356 QMP_PHY_INIT_CFG(QSERDES_TX_RES_CODE_LANE_OFFSET, 0x2), 357 QMP_PHY_INIT_CFG(QSERDES_TX_RCV_DETECT_LVL_2, 0x12), 358}; 359 360static const struct qmp_phy_init_tbl ipq8074_pcie_rx_tbl[] = { 361 QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_ENABLES, 0x1c), 362 QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_DEGLITCH_CNTRL, 0x14), 363 QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL2, 0x1), 364 QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL3, 0x0), 365 QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL4, 0xdb), 366 QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x4b), 367 QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SO_GAIN, 0x4), 368 QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SO_GAIN_HALF, 0x4), 369}; 370 371static const struct qmp_phy_init_tbl ipq8074_pcie_pcs_tbl[] = { 372 QMP_PHY_INIT_CFG(QPHY_ENDPOINT_REFCLK_DRIVE, 0x4), 373 QMP_PHY_INIT_CFG(QPHY_OSC_DTCT_ACTIONS, 0x0), 374 QMP_PHY_INIT_CFG(QPHY_PWRUP_RESET_DLY_TIME_AUXCLK, 0x40), 375 QMP_PHY_INIT_CFG(QPHY_L1SS_WAKEUP_DLY_TIME_AUXCLK_MSB, 0x0), 376 QMP_PHY_INIT_CFG(QPHY_L1SS_WAKEUP_DLY_TIME_AUXCLK_LSB, 0x40), 377 QMP_PHY_INIT_CFG(QPHY_PLL_LOCK_CHK_DLY_TIME_AUXCLK_LSB, 0x0), 378 QMP_PHY_INIT_CFG(QPHY_LP_WAKEUP_DLY_TIME_AUXCLK, 0x40), 379 QMP_PHY_INIT_CFG_L(QPHY_PLL_LOCK_CHK_DLY_TIME, 0x73), 380 QMP_PHY_INIT_CFG(QPHY_RX_SIGDET_LVL, 0x99), 381 QMP_PHY_INIT_CFG(QPHY_TXDEEMPH_M6DB_V0, 0x15), 382 QMP_PHY_INIT_CFG(QPHY_TXDEEMPH_M3P5DB_V0, 0xe), 383 QMP_PHY_INIT_CFG_L(QPHY_SW_RESET, 0x0), 384 QMP_PHY_INIT_CFG_L(QPHY_START_CTRL, 0x3), 385}; 386 387static const struct qmp_phy_init_tbl qmp_v3_usb3_serdes_tbl[] = { 388 QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_IVCO, 0x07), 389 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_EN_SEL, 0x14), 390 QMP_PHY_INIT_CFG(QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN, 0x08), 391 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x30), 392 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYS_CLK_CTRL, 0x02), 393 QMP_PHY_INIT_CFG(QSERDES_V3_COM_RESETSM_CNTRL2, 0x08), 394 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_CONFIG, 0x16), 395 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SVS_MODE_CLK_SEL, 0x01), 396 QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x80), 397 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x82), 398 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START1_MODE0, 0xab), 399 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0xea), 400 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x02), 401 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CP_CTRL_MODE0, 0x06), 402 QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_RCTRL_MODE0, 0x16), 403 QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_CCTRL_MODE0, 0x36), 404 QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE0, 0x00), 405 QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE0, 0x3f), 406 QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE2_MODE0, 0x01), 407 QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE1_MODE0, 0xc9), 408 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORECLK_DIV_MODE0, 0x0a), 409 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP3_MODE0, 0x00), 410 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x34), 411 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x15), 412 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x04), 413 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORE_CLK_EN, 0x00), 414 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_CFG, 0x00), 415 QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_MAP, 0x00), 416 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_BUF_ENABLE, 0x0a), 417 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_EN_CENTER, 0x01), 418 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER1, 0x31), 419 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER2, 0x01), 420 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER1, 0x00), 421 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER2, 0x00), 422 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE1, 0x85), 423 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE2, 0x07), 424}; 425 426static const struct qmp_phy_init_tbl qmp_v3_usb3_tx_tbl[] = { 427 QMP_PHY_INIT_CFG(QSERDES_V3_TX_HIGHZ_DRVR_EN, 0x10), 428 QMP_PHY_INIT_CFG(QSERDES_V3_TX_RCV_DETECT_LVL_2, 0x12), 429 QMP_PHY_INIT_CFG(QSERDES_V3_TX_LANE_MODE_1, 0x16), 430 QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_RX, 0x09), 431 QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_TX, 0x06), 432}; 433 434static const struct qmp_phy_init_tbl qmp_v3_usb3_rx_tbl[] = { 435 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_FO_GAIN, 0x0b), 436 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f), 437 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4e), 438 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL4, 0x18), 439 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x77), 440 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80), 441 QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_CNTRL, 0x03), 442 QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_DEGLITCH_CNTRL, 0x16), 443 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x75), 444}; 445 446static const struct qmp_phy_init_tbl qmp_v3_usb3_pcs_tbl[] = { 447 /* FLL settings */ 448 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL2, 0x83), 449 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_L, 0x09), 450 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_H_TOL, 0xa2), 451 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_MAN_CODE, 0x40), 452 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL1, 0x02), 453 454 /* Lock Det settings */ 455 QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG1, 0xd1), 456 QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG2, 0x1f), 457 QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG3, 0x47), 458 QMP_PHY_INIT_CFG(QPHY_V3_PCS_POWER_STATE_CONFIG2, 0x1b), 459 460 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_LVL, 0xba), 461 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V0, 0x9f), 462 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V1, 0x9f), 463 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V2, 0xb7), 464 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V3, 0x4e), 465 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V4, 0x65), 466 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_LS, 0x6b), 467 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V0, 0x15), 468 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V0, 0x0d), 469 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V1, 0x15), 470 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V1, 0x0d), 471 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V2, 0x15), 472 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V2, 0x0d), 473 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V3, 0x15), 474 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V3, 0x1d), 475 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V4, 0x15), 476 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V4, 0x0d), 477 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_LS, 0x15), 478 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_LS, 0x0d), 479 480 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RATE_SLEW_CNTRL, 0x02), 481 QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x04), 482 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TSYNC_RSYNC_TIME, 0x44), 483 QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x04), 484 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7), 485 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03), 486 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_L, 0x40), 487 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_H, 0x00), 488 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_WAIT_TIME, 0x75), 489 QMP_PHY_INIT_CFG(QPHY_V3_PCS_LFPS_TX_ECSTART_EQTLOCK, 0x86), 490 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_RUN_TIME, 0x13), 491}; 492 493static const struct qmp_phy_init_tbl qmp_v3_usb3_uniphy_serdes_tbl[] = { 494 QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_IVCO, 0x07), 495 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_EN_SEL, 0x14), 496 QMP_PHY_INIT_CFG(QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN, 0x04), 497 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x30), 498 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYS_CLK_CTRL, 0x02), 499 QMP_PHY_INIT_CFG(QSERDES_V3_COM_RESETSM_CNTRL2, 0x08), 500 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_CONFIG, 0x06), 501 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SVS_MODE_CLK_SEL, 0x01), 502 QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x80), 503 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x82), 504 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START1_MODE0, 0xab), 505 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0xea), 506 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x02), 507 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CP_CTRL_MODE0, 0x06), 508 QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_RCTRL_MODE0, 0x16), 509 QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_CCTRL_MODE0, 0x36), 510 QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE0, 0x00), 511 QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE0, 0x3f), 512 QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE2_MODE0, 0x01), 513 QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE1_MODE0, 0xc9), 514 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORECLK_DIV_MODE0, 0x0a), 515 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP3_MODE0, 0x00), 516 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x34), 517 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x15), 518 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x04), 519 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORE_CLK_EN, 0x00), 520 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_CFG, 0x00), 521 QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_MAP, 0x00), 522 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_BUF_ENABLE, 0x0a), 523 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_EN_CENTER, 0x01), 524 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER1, 0x31), 525 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER2, 0x01), 526 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER1, 0x00), 527 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER2, 0x00), 528 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE1, 0x85), 529 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE2, 0x07), 530}; 531 532static const struct qmp_phy_init_tbl qmp_v3_usb3_uniphy_tx_tbl[] = { 533 QMP_PHY_INIT_CFG(QSERDES_V3_TX_HIGHZ_DRVR_EN, 0x10), 534 QMP_PHY_INIT_CFG(QSERDES_V3_TX_RCV_DETECT_LVL_2, 0x12), 535 QMP_PHY_INIT_CFG(QSERDES_V3_TX_LANE_MODE_1, 0xc6), 536 QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_RX, 0x06), 537 QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_TX, 0x06), 538}; 539 540static const struct qmp_phy_init_tbl qmp_v3_usb3_uniphy_rx_tbl[] = { 541 QMP_PHY_INIT_CFG(QSERDES_V3_RX_VGA_CAL_CNTRL2, 0x0c), 542 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_MODE_00, 0x50), 543 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_FO_GAIN, 0x0b), 544 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0e), 545 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4e), 546 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL4, 0x18), 547 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x77), 548 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80), 549 QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_CNTRL, 0x03), 550 QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_DEGLITCH_CNTRL, 0x1c), 551 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x75), 552}; 553 554static const struct qmp_phy_init_tbl qmp_v3_usb3_uniphy_pcs_tbl[] = { 555 /* FLL settings */ 556 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL2, 0x83), 557 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_L, 0x09), 558 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_H_TOL, 0xa2), 559 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_MAN_CODE, 0x40), 560 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL1, 0x02), 561 562 /* Lock Det settings */ 563 QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG1, 0xd1), 564 QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG2, 0x1f), 565 QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG3, 0x47), 566 QMP_PHY_INIT_CFG(QPHY_V3_PCS_POWER_STATE_CONFIG2, 0x1b), 567 568 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_LVL, 0xba), 569 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V0, 0x9f), 570 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V1, 0x9f), 571 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V2, 0xb5), 572 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V3, 0x4c), 573 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V4, 0x64), 574 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_LS, 0x6a), 575 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V0, 0x15), 576 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V0, 0x0d), 577 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V1, 0x15), 578 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V1, 0x0d), 579 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V2, 0x15), 580 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V2, 0x0d), 581 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V3, 0x15), 582 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V3, 0x1d), 583 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V4, 0x15), 584 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V4, 0x0d), 585 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_LS, 0x15), 586 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_LS, 0x0d), 587 588 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RATE_SLEW_CNTRL, 0x02), 589 QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x04), 590 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TSYNC_RSYNC_TIME, 0x44), 591 QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x04), 592 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7), 593 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03), 594 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_L, 0x40), 595 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_H, 0x00), 596 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_WAIT_TIME, 0x75), 597 QMP_PHY_INIT_CFG(QPHY_V3_PCS_LFPS_TX_ECSTART_EQTLOCK, 0x86), 598 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_RUN_TIME, 0x13), 599 600 QMP_PHY_INIT_CFG(QPHY_V3_PCS_REFGEN_REQ_CONFIG1, 0x21), 601 QMP_PHY_INIT_CFG(QPHY_V3_PCS_REFGEN_REQ_CONFIG2, 0x60), 602}; 603 604 605/* struct qmp_phy_cfg - per-PHY initialization config */ 606struct qmp_phy_cfg { 607 /* phy-type - PCIE/UFS/USB */ 608 unsigned int type; 609 /* number of lanes provided by phy */ 610 int nlanes; 611 612 /* Init sequence for PHY blocks - serdes, tx, rx, pcs */ 613 const struct qmp_phy_init_tbl *serdes_tbl; 614 int serdes_tbl_num; 615 const struct qmp_phy_init_tbl *tx_tbl; 616 int tx_tbl_num; 617 const struct qmp_phy_init_tbl *rx_tbl; 618 int rx_tbl_num; 619 const struct qmp_phy_init_tbl *pcs_tbl; 620 int pcs_tbl_num; 621 622 /* clock ids to be requested */ 623 const char * const *clk_list; 624 int num_clks; 625 /* resets to be requested */ 626 const char * const *reset_list; 627 int num_resets; 628 /* regulators to be requested */ 629 const char * const *vreg_list; 630 int num_vregs; 631 632 /* array of registers with different offsets */ 633 const unsigned int *regs; 634 635 unsigned int start_ctrl; 636 unsigned int pwrdn_ctrl; 637 unsigned int mask_pcs_ready; 638 unsigned int mask_com_pcs_ready; 639 640 /* true, if PHY has a separate PHY_COM control block */ 641 bool has_phy_com_ctrl; 642 /* true, if PHY has a reset for individual lanes */ 643 bool has_lane_rst; 644 /* true, if PHY needs delay after POWER_DOWN */ 645 bool has_pwrdn_delay; 646 /* power_down delay in usec */ 647 int pwrdn_delay_min; 648 int pwrdn_delay_max; 649 650 /* true, if PHY has a separate DP_COM control block */ 651 bool has_phy_dp_com_ctrl; 652 /* Register offset of secondary tx/rx lanes for USB DP combo PHY */ 653 unsigned int tx_b_lane_offset; 654 unsigned int rx_b_lane_offset; 655}; 656 657/** 658 * struct qmp_phy - per-lane phy descriptor 659 * 660 * @phy: generic phy 661 * @tx: iomapped memory space for lane's tx 662 * @rx: iomapped memory space for lane's rx 663 * @pcs: iomapped memory space for lane's pcs 664 * @pcs_misc: iomapped memory space for lane's pcs_misc 665 * @pipe_clk: pipe lock 666 * @index: lane index 667 * @qmp: QMP phy to which this lane belongs 668 * @lane_rst: lane's reset controller 669 */ 670struct qmp_phy { 671 struct phy *phy; 672 void __iomem *tx; 673 void __iomem *rx; 674 void __iomem *pcs; 675 void __iomem *pcs_misc; 676 struct clk *pipe_clk; 677 unsigned int index; 678 struct qcom_qmp *qmp; 679 struct reset_control *lane_rst; 680}; 681 682/** 683 * struct qcom_qmp - structure holding QMP phy block attributes 684 * 685 * @dev: device 686 * @serdes: iomapped memory space for phy's serdes 687 * @dp_com: iomapped memory space for phy's dp_com control block 688 * 689 * @clks: array of clocks required by phy 690 * @resets: array of resets required by phy 691 * @vregs: regulator supplies bulk data 692 * 693 * @cfg: phy specific configuration 694 * @phys: array of per-lane phy descriptors 695 * @phy_mutex: mutex lock for PHY common block initialization 696 * @init_count: phy common block initialization count 697 * @phy_initialized: indicate if PHY has been initialized 698 * @mode: current PHY mode 699 */ 700struct qcom_qmp { 701 struct device *dev; 702 void __iomem *serdes; 703 void __iomem *dp_com; 704 705 struct clk_bulk_data *clks; 706 struct reset_control **resets; 707 struct regulator_bulk_data *vregs; 708 709 const struct qmp_phy_cfg *cfg; 710 struct qmp_phy **phys; 711 712 struct mutex phy_mutex; 713 int init_count; 714 bool phy_initialized; 715 enum phy_mode mode; 716}; 717 718static inline void qphy_setbits(void __iomem *base, u32 offset, u32 val) 719{ 720 u32 reg; 721 722 reg = readl(base + offset); 723 reg |= val; 724 writel(reg, base + offset); 725 726 /* ensure that above write is through */ 727 readl(base + offset); 728} 729 730static inline void qphy_clrbits(void __iomem *base, u32 offset, u32 val) 731{ 732 u32 reg; 733 734 reg = readl(base + offset); 735 reg &= ~val; 736 writel(reg, base + offset); 737 738 /* ensure that above write is through */ 739 readl(base + offset); 740} 741 742/* list of clocks required by phy */ 743static const char * const msm8996_phy_clk_l[] = { 744 "aux", "cfg_ahb", "ref", 745}; 746 747static const char * const qmp_v3_phy_clk_l[] = { 748 "aux", "cfg_ahb", "ref", "com_aux", 749}; 750 751/* list of resets */ 752static const char * const msm8996_pciephy_reset_l[] = { 753 "phy", "common", "cfg", 754}; 755 756static const char * const msm8996_usb3phy_reset_l[] = { 757 "phy", "common", 758}; 759 760/* list of regulators */ 761static const char * const msm8996_phy_vreg_l[] = { 762 "vdda-phy", "vdda-pll", 763}; 764 765static const struct qmp_phy_cfg msm8996_pciephy_cfg = { 766 .type = PHY_TYPE_PCIE, 767 .nlanes = 3, 768 769 .serdes_tbl = msm8996_pcie_serdes_tbl, 770 .serdes_tbl_num = ARRAY_SIZE(msm8996_pcie_serdes_tbl), 771 .tx_tbl = msm8996_pcie_tx_tbl, 772 .tx_tbl_num = ARRAY_SIZE(msm8996_pcie_tx_tbl), 773 .rx_tbl = msm8996_pcie_rx_tbl, 774 .rx_tbl_num = ARRAY_SIZE(msm8996_pcie_rx_tbl), 775 .pcs_tbl = msm8996_pcie_pcs_tbl, 776 .pcs_tbl_num = ARRAY_SIZE(msm8996_pcie_pcs_tbl), 777 .clk_list = msm8996_phy_clk_l, 778 .num_clks = ARRAY_SIZE(msm8996_phy_clk_l), 779 .reset_list = msm8996_pciephy_reset_l, 780 .num_resets = ARRAY_SIZE(msm8996_pciephy_reset_l), 781 .vreg_list = msm8996_phy_vreg_l, 782 .num_vregs = ARRAY_SIZE(msm8996_phy_vreg_l), 783 .regs = pciephy_regs_layout, 784 785 .start_ctrl = PCS_START | PLL_READY_GATE_EN, 786 .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL, 787 .mask_com_pcs_ready = PCS_READY, 788 789 .has_phy_com_ctrl = true, 790 .has_lane_rst = true, 791 .has_pwrdn_delay = true, 792 .pwrdn_delay_min = POWER_DOWN_DELAY_US_MIN, 793 .pwrdn_delay_max = POWER_DOWN_DELAY_US_MAX, 794}; 795 796static const struct qmp_phy_cfg msm8996_usb3phy_cfg = { 797 .type = PHY_TYPE_USB3, 798 .nlanes = 1, 799 800 .serdes_tbl = msm8996_usb3_serdes_tbl, 801 .serdes_tbl_num = ARRAY_SIZE(msm8996_usb3_serdes_tbl), 802 .tx_tbl = msm8996_usb3_tx_tbl, 803 .tx_tbl_num = ARRAY_SIZE(msm8996_usb3_tx_tbl), 804 .rx_tbl = msm8996_usb3_rx_tbl, 805 .rx_tbl_num = ARRAY_SIZE(msm8996_usb3_rx_tbl), 806 .pcs_tbl = msm8996_usb3_pcs_tbl, 807 .pcs_tbl_num = ARRAY_SIZE(msm8996_usb3_pcs_tbl), 808 .clk_list = msm8996_phy_clk_l, 809 .num_clks = ARRAY_SIZE(msm8996_phy_clk_l), 810 .reset_list = msm8996_usb3phy_reset_l, 811 .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l), 812 .vreg_list = msm8996_phy_vreg_l, 813 .num_vregs = ARRAY_SIZE(msm8996_phy_vreg_l), 814 .regs = usb3phy_regs_layout, 815 816 .start_ctrl = SERDES_START | PCS_START, 817 .pwrdn_ctrl = SW_PWRDN, 818 .mask_pcs_ready = PHYSTATUS, 819}; 820 821/* list of resets */ 822static const char * const ipq8074_pciephy_reset_l[] = { 823 "phy", "common", 824}; 825 826static const struct qmp_phy_cfg ipq8074_pciephy_cfg = { 827 .type = PHY_TYPE_PCIE, 828 .nlanes = 1, 829 830 .serdes_tbl = ipq8074_pcie_serdes_tbl, 831 .serdes_tbl_num = ARRAY_SIZE(ipq8074_pcie_serdes_tbl), 832 .tx_tbl = ipq8074_pcie_tx_tbl, 833 .tx_tbl_num = ARRAY_SIZE(ipq8074_pcie_tx_tbl), 834 .rx_tbl = ipq8074_pcie_rx_tbl, 835 .rx_tbl_num = ARRAY_SIZE(ipq8074_pcie_rx_tbl), 836 .pcs_tbl = ipq8074_pcie_pcs_tbl, 837 .pcs_tbl_num = ARRAY_SIZE(ipq8074_pcie_pcs_tbl), 838 .clk_list = NULL, 839 .num_clks = 0, 840 .reset_list = ipq8074_pciephy_reset_l, 841 .num_resets = ARRAY_SIZE(ipq8074_pciephy_reset_l), 842 .vreg_list = NULL, 843 .num_vregs = 0, 844 .regs = pciephy_regs_layout, 845 846 .start_ctrl = SERDES_START | PCS_START, 847 .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL, 848 .mask_pcs_ready = PHYSTATUS, 849 850 .has_phy_com_ctrl = false, 851 .has_lane_rst = false, 852 .has_pwrdn_delay = true, 853 .pwrdn_delay_min = 995, /* us */ 854 .pwrdn_delay_max = 1005, /* us */ 855}; 856 857static const struct qmp_phy_cfg qmp_v3_usb3phy_cfg = { 858 .type = PHY_TYPE_USB3, 859 .nlanes = 1, 860 861 .serdes_tbl = qmp_v3_usb3_serdes_tbl, 862 .serdes_tbl_num = ARRAY_SIZE(qmp_v3_usb3_serdes_tbl), 863 .tx_tbl = qmp_v3_usb3_tx_tbl, 864 .tx_tbl_num = ARRAY_SIZE(qmp_v3_usb3_tx_tbl), 865 .rx_tbl = qmp_v3_usb3_rx_tbl, 866 .rx_tbl_num = ARRAY_SIZE(qmp_v3_usb3_rx_tbl), 867 .pcs_tbl = qmp_v3_usb3_pcs_tbl, 868 .pcs_tbl_num = ARRAY_SIZE(qmp_v3_usb3_pcs_tbl), 869 .clk_list = qmp_v3_phy_clk_l, 870 .num_clks = ARRAY_SIZE(qmp_v3_phy_clk_l), 871 .reset_list = msm8996_usb3phy_reset_l, 872 .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l), 873 .vreg_list = msm8996_phy_vreg_l, 874 .num_vregs = ARRAY_SIZE(msm8996_phy_vreg_l), 875 .regs = qmp_v3_usb3phy_regs_layout, 876 877 .start_ctrl = SERDES_START | PCS_START, 878 .pwrdn_ctrl = SW_PWRDN, 879 .mask_pcs_ready = PHYSTATUS, 880 881 .has_pwrdn_delay = true, 882 .pwrdn_delay_min = POWER_DOWN_DELAY_US_MIN, 883 .pwrdn_delay_max = POWER_DOWN_DELAY_US_MAX, 884 885 .has_phy_dp_com_ctrl = true, 886 .tx_b_lane_offset = 0x400, 887 .rx_b_lane_offset = 0x400, 888}; 889 890static const struct qmp_phy_cfg qmp_v3_usb3_uniphy_cfg = { 891 .type = PHY_TYPE_USB3, 892 .nlanes = 1, 893 894 .serdes_tbl = qmp_v3_usb3_uniphy_serdes_tbl, 895 .serdes_tbl_num = ARRAY_SIZE(qmp_v3_usb3_uniphy_serdes_tbl), 896 .tx_tbl = qmp_v3_usb3_uniphy_tx_tbl, 897 .tx_tbl_num = ARRAY_SIZE(qmp_v3_usb3_uniphy_tx_tbl), 898 .rx_tbl = qmp_v3_usb3_uniphy_rx_tbl, 899 .rx_tbl_num = ARRAY_SIZE(qmp_v3_usb3_uniphy_rx_tbl), 900 .pcs_tbl = qmp_v3_usb3_uniphy_pcs_tbl, 901 .pcs_tbl_num = ARRAY_SIZE(qmp_v3_usb3_uniphy_pcs_tbl), 902 .clk_list = qmp_v3_phy_clk_l, 903 .num_clks = ARRAY_SIZE(qmp_v3_phy_clk_l), 904 .reset_list = msm8996_usb3phy_reset_l, 905 .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l), 906 .vreg_list = msm8996_phy_vreg_l, 907 .num_vregs = ARRAY_SIZE(msm8996_phy_vreg_l), 908 .regs = qmp_v3_usb3phy_regs_layout, 909 910 .start_ctrl = SERDES_START | PCS_START, 911 .pwrdn_ctrl = SW_PWRDN, 912 .mask_pcs_ready = PHYSTATUS, 913 914 .has_pwrdn_delay = true, 915 .pwrdn_delay_min = POWER_DOWN_DELAY_US_MIN, 916 .pwrdn_delay_max = POWER_DOWN_DELAY_US_MAX, 917}; 918 919static void qcom_qmp_phy_configure(void __iomem *base, 920 const unsigned int *regs, 921 const struct qmp_phy_init_tbl tbl[], 922 int num) 923{ 924 int i; 925 const struct qmp_phy_init_tbl *t = tbl; 926 927 if (!t) 928 return; 929 930 for (i = 0; i < num; i++, t++) { 931 if (t->in_layout) 932 writel(t->val, base + regs[t->offset]); 933 else 934 writel(t->val, base + t->offset); 935 } 936} 937 938static int qcom_qmp_phy_com_init(struct qcom_qmp *qmp) 939{ 940 const struct qmp_phy_cfg *cfg = qmp->cfg; 941 void __iomem *serdes = qmp->serdes; 942 void __iomem *dp_com = qmp->dp_com; 943 int ret, i; 944 945 mutex_lock(&qmp->phy_mutex); 946 if (qmp->init_count++) { 947 mutex_unlock(&qmp->phy_mutex); 948 return 0; 949 } 950 951 /* turn on regulator supplies */ 952 ret = regulator_bulk_enable(cfg->num_vregs, qmp->vregs); 953 if (ret) { 954 dev_err(qmp->dev, "failed to enable regulators, err=%d\n", ret); 955 goto err_reg_enable; 956 } 957 958 for (i = 0; i < cfg->num_resets; i++) { 959 ret = reset_control_assert(qmp->resets[i]); 960 if (ret) { 961 dev_err(qmp->dev, "%s reset assert failed\n", 962 cfg->reset_list[i]); 963 goto err_rst_assert; 964 } 965 } 966 967 for (i = cfg->num_resets - 1; i >= 0; i--) { 968 ret = reset_control_deassert(qmp->resets[i]); 969 if (ret) { 970 dev_err(qmp->dev, "%s reset deassert failed\n", 971 qmp->cfg->reset_list[i]); 972 goto err_rst; 973 } 974 } 975 976 ret = clk_bulk_prepare_enable(cfg->num_clks, qmp->clks); 977 if (ret) { 978 dev_err(qmp->dev, "failed to enable clks, err=%d\n", ret); 979 goto err_rst; 980 } 981 982 if (cfg->has_phy_com_ctrl) 983 qphy_setbits(serdes, cfg->regs[QPHY_COM_POWER_DOWN_CONTROL], 984 SW_PWRDN); 985 986 if (cfg->has_phy_dp_com_ctrl) { 987 qphy_setbits(dp_com, QPHY_V3_DP_COM_POWER_DOWN_CTRL, 988 SW_PWRDN); 989 /* override hardware control for reset of qmp phy */ 990 qphy_setbits(dp_com, QPHY_V3_DP_COM_RESET_OVRD_CTRL, 991 SW_DPPHY_RESET_MUX | SW_DPPHY_RESET | 992 SW_USB3PHY_RESET_MUX | SW_USB3PHY_RESET); 993 994 qphy_setbits(dp_com, QPHY_V3_DP_COM_PHY_MODE_CTRL, 995 USB3_MODE | DP_MODE); 996 997 /* bring both QMP USB and QMP DP PHYs PCS block out of reset */ 998 qphy_clrbits(dp_com, QPHY_V3_DP_COM_RESET_OVRD_CTRL, 999 SW_DPPHY_RESET_MUX | SW_DPPHY_RESET | 1000 SW_USB3PHY_RESET_MUX | SW_USB3PHY_RESET); 1001 } 1002 1003 /* Serdes configuration */ 1004 qcom_qmp_phy_configure(serdes, cfg->regs, cfg->serdes_tbl, 1005 cfg->serdes_tbl_num); 1006 1007 if (cfg->has_phy_com_ctrl) { 1008 void __iomem *status; 1009 unsigned int mask, val; 1010 1011 qphy_clrbits(serdes, cfg->regs[QPHY_COM_SW_RESET], SW_RESET); 1012 qphy_setbits(serdes, cfg->regs[QPHY_COM_START_CONTROL], 1013 SERDES_START | PCS_START); 1014 1015 status = serdes + cfg->regs[QPHY_COM_PCS_READY_STATUS]; 1016 mask = cfg->mask_com_pcs_ready; 1017 1018 ret = readl_poll_timeout(status, val, (val & mask), 10, 1019 PHY_INIT_COMPLETE_TIMEOUT); 1020 if (ret) { 1021 dev_err(qmp->dev, 1022 "phy common block init timed-out\n"); 1023 goto err_com_init; 1024 } 1025 } 1026 1027 mutex_unlock(&qmp->phy_mutex); 1028 1029 return 0; 1030 1031err_com_init: 1032 clk_bulk_disable_unprepare(cfg->num_clks, qmp->clks); 1033err_rst: 1034 while (++i < cfg->num_resets) 1035 reset_control_assert(qmp->resets[i]); 1036err_rst_assert: 1037 regulator_bulk_disable(cfg->num_vregs, qmp->vregs); 1038err_reg_enable: 1039 mutex_unlock(&qmp->phy_mutex); 1040 1041 return ret; 1042} 1043 1044static int qcom_qmp_phy_com_exit(struct qcom_qmp *qmp) 1045{ 1046 const struct qmp_phy_cfg *cfg = qmp->cfg; 1047 void __iomem *serdes = qmp->serdes; 1048 int i = cfg->num_resets; 1049 1050 mutex_lock(&qmp->phy_mutex); 1051 if (--qmp->init_count) { 1052 mutex_unlock(&qmp->phy_mutex); 1053 return 0; 1054 } 1055 1056 if (cfg->has_phy_com_ctrl) { 1057 qphy_setbits(serdes, cfg->regs[QPHY_COM_START_CONTROL], 1058 SERDES_START | PCS_START); 1059 qphy_clrbits(serdes, cfg->regs[QPHY_COM_SW_RESET], 1060 SW_RESET); 1061 qphy_setbits(serdes, cfg->regs[QPHY_COM_POWER_DOWN_CONTROL], 1062 SW_PWRDN); 1063 } 1064 1065 while (--i >= 0) 1066 reset_control_assert(qmp->resets[i]); 1067 1068 clk_bulk_disable_unprepare(cfg->num_clks, qmp->clks); 1069 1070 regulator_bulk_disable(cfg->num_vregs, qmp->vregs); 1071 1072 mutex_unlock(&qmp->phy_mutex); 1073 1074 return 0; 1075} 1076 1077/* PHY Initialization */ 1078static int qcom_qmp_phy_init(struct phy *phy) 1079{ 1080 struct qmp_phy *qphy = phy_get_drvdata(phy); 1081 struct qcom_qmp *qmp = qphy->qmp; 1082 const struct qmp_phy_cfg *cfg = qmp->cfg; 1083 void __iomem *tx = qphy->tx; 1084 void __iomem *rx = qphy->rx; 1085 void __iomem *pcs = qphy->pcs; 1086 void __iomem *dp_com = qmp->dp_com; 1087 void __iomem *status; 1088 unsigned int mask, val; 1089 int ret; 1090 1091 dev_vdbg(qmp->dev, "Initializing QMP phy\n"); 1092 1093 ret = qcom_qmp_phy_com_init(qmp); 1094 if (ret) 1095 return ret; 1096 1097 if (cfg->has_lane_rst) { 1098 ret = reset_control_deassert(qphy->lane_rst); 1099 if (ret) { 1100 dev_err(qmp->dev, "lane%d reset deassert failed\n", 1101 qphy->index); 1102 goto err_lane_rst; 1103 } 1104 } 1105 1106 ret = clk_prepare_enable(qphy->pipe_clk); 1107 if (ret) { 1108 dev_err(qmp->dev, "pipe_clk enable failed err=%d\n", ret); 1109 goto err_clk_enable; 1110 } 1111 1112 /* Tx, Rx, and PCS configurations */ 1113 qcom_qmp_phy_configure(tx, cfg->regs, cfg->tx_tbl, cfg->tx_tbl_num); 1114 /* Configuration for other LANE for USB-DP combo PHY */ 1115 if (cfg->has_phy_dp_com_ctrl) 1116 qcom_qmp_phy_configure(tx + cfg->tx_b_lane_offset, cfg->regs, 1117 cfg->tx_tbl, cfg->tx_tbl_num); 1118 1119 qcom_qmp_phy_configure(rx, cfg->regs, cfg->rx_tbl, cfg->rx_tbl_num); 1120 if (cfg->has_phy_dp_com_ctrl) 1121 qcom_qmp_phy_configure(rx + cfg->rx_b_lane_offset, cfg->regs, 1122 cfg->rx_tbl, cfg->rx_tbl_num); 1123 1124 qcom_qmp_phy_configure(pcs, cfg->regs, cfg->pcs_tbl, cfg->pcs_tbl_num); 1125 1126 /* 1127 * Pull out PHY from POWER DOWN state. 1128 * This is active low enable signal to power-down PHY. 1129 */ 1130 qphy_setbits(pcs, QPHY_POWER_DOWN_CONTROL, cfg->pwrdn_ctrl); 1131 1132 if (cfg->has_pwrdn_delay) 1133 usleep_range(cfg->pwrdn_delay_min, cfg->pwrdn_delay_max); 1134 1135 /* Pull PHY out of reset state */ 1136 qphy_clrbits(pcs, cfg->regs[QPHY_SW_RESET], SW_RESET); 1137 if (cfg->has_phy_dp_com_ctrl) 1138 qphy_clrbits(dp_com, QPHY_V3_DP_COM_SW_RESET, SW_RESET); 1139 1140 /* start SerDes and Phy-Coding-Sublayer */ 1141 qphy_setbits(pcs, cfg->regs[QPHY_START_CTRL], cfg->start_ctrl); 1142 1143 status = pcs + cfg->regs[QPHY_PCS_READY_STATUS]; 1144 mask = cfg->mask_pcs_ready; 1145 1146 ret = readl_poll_timeout(status, val, !(val & mask), 1, 1147 PHY_INIT_COMPLETE_TIMEOUT); 1148 if (ret) { 1149 dev_err(qmp->dev, "phy initialization timed-out\n"); 1150 goto err_pcs_ready; 1151 } 1152 qmp->phy_initialized = true; 1153 1154 return ret; 1155 1156err_pcs_ready: 1157 clk_disable_unprepare(qphy->pipe_clk); 1158err_clk_enable: 1159 if (cfg->has_lane_rst) 1160 reset_control_assert(qphy->lane_rst); 1161err_lane_rst: 1162 qcom_qmp_phy_com_exit(qmp); 1163 1164 return ret; 1165} 1166 1167static int qcom_qmp_phy_exit(struct phy *phy) 1168{ 1169 struct qmp_phy *qphy = phy_get_drvdata(phy); 1170 struct qcom_qmp *qmp = qphy->qmp; 1171 const struct qmp_phy_cfg *cfg = qmp->cfg; 1172 1173 clk_disable_unprepare(qphy->pipe_clk); 1174 1175 /* PHY reset */ 1176 qphy_setbits(qphy->pcs, cfg->regs[QPHY_SW_RESET], SW_RESET); 1177 1178 /* stop SerDes and Phy-Coding-Sublayer */ 1179 qphy_clrbits(qphy->pcs, cfg->regs[QPHY_START_CTRL], cfg->start_ctrl); 1180 1181 /* Put PHY into POWER DOWN state: active low */ 1182 qphy_clrbits(qphy->pcs, QPHY_POWER_DOWN_CONTROL, cfg->pwrdn_ctrl); 1183 1184 if (cfg->has_lane_rst) 1185 reset_control_assert(qphy->lane_rst); 1186 1187 qcom_qmp_phy_com_exit(qmp); 1188 1189 qmp->phy_initialized = false; 1190 1191 return 0; 1192} 1193 1194static int qcom_qmp_phy_set_mode(struct phy *phy, enum phy_mode mode) 1195{ 1196 struct qmp_phy *qphy = phy_get_drvdata(phy); 1197 struct qcom_qmp *qmp = qphy->qmp; 1198 1199 qmp->mode = mode; 1200 1201 return 0; 1202} 1203 1204static void qcom_qmp_phy_enable_autonomous_mode(struct qmp_phy *qphy) 1205{ 1206 struct qcom_qmp *qmp = qphy->qmp; 1207 const struct qmp_phy_cfg *cfg = qmp->cfg; 1208 void __iomem *pcs = qphy->pcs; 1209 void __iomem *pcs_misc = qphy->pcs_misc; 1210 u32 intr_mask; 1211 1212 if (qmp->mode == PHY_MODE_USB_HOST_SS || 1213 qmp->mode == PHY_MODE_USB_DEVICE_SS) 1214 intr_mask = ARCVR_DTCT_EN | ALFPS_DTCT_EN; 1215 else 1216 intr_mask = ARCVR_DTCT_EN | ARCVR_DTCT_EVENT_SEL; 1217 1218 /* Clear any pending interrupts status */ 1219 qphy_setbits(pcs, cfg->regs[QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR], IRQ_CLEAR); 1220 /* Writing 1 followed by 0 clears the interrupt */ 1221 qphy_clrbits(pcs, cfg->regs[QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR], IRQ_CLEAR); 1222 1223 qphy_clrbits(pcs, cfg->regs[QPHY_PCS_AUTONOMOUS_MODE_CTRL], 1224 ARCVR_DTCT_EN | ALFPS_DTCT_EN | ARCVR_DTCT_EVENT_SEL); 1225 1226 /* Enable required PHY autonomous mode interrupts */ 1227 qphy_setbits(pcs, cfg->regs[QPHY_PCS_AUTONOMOUS_MODE_CTRL], intr_mask); 1228 1229 /* Enable i/o clamp_n for autonomous mode */ 1230 if (pcs_misc) 1231 qphy_clrbits(pcs_misc, QPHY_V3_PCS_MISC_CLAMP_ENABLE, CLAMP_EN); 1232} 1233 1234static void qcom_qmp_phy_disable_autonomous_mode(struct qmp_phy *qphy) 1235{ 1236 struct qcom_qmp *qmp = qphy->qmp; 1237 const struct qmp_phy_cfg *cfg = qmp->cfg; 1238 void __iomem *pcs = qphy->pcs; 1239 void __iomem *pcs_misc = qphy->pcs_misc; 1240 1241 /* Disable i/o clamp_n on resume for normal mode */ 1242 if (pcs_misc) 1243 qphy_setbits(pcs_misc, QPHY_V3_PCS_MISC_CLAMP_ENABLE, CLAMP_EN); 1244 1245 qphy_clrbits(pcs, cfg->regs[QPHY_PCS_AUTONOMOUS_MODE_CTRL], 1246 ARCVR_DTCT_EN | ARCVR_DTCT_EVENT_SEL | ALFPS_DTCT_EN); 1247 1248 qphy_setbits(pcs, cfg->regs[QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR], IRQ_CLEAR); 1249 /* Writing 1 followed by 0 clears the interrupt */ 1250 qphy_clrbits(pcs, cfg->regs[QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR], IRQ_CLEAR); 1251} 1252 1253static int __maybe_unused qcom_qmp_phy_runtime_suspend(struct device *dev) 1254{ 1255 struct qcom_qmp *qmp = dev_get_drvdata(dev); 1256 struct qmp_phy *qphy = qmp->phys[0]; 1257 const struct qmp_phy_cfg *cfg = qmp->cfg; 1258 1259 dev_vdbg(dev, "Suspending QMP phy, mode:%d\n", qmp->mode); 1260 1261 /* Supported only for USB3 PHY */ 1262 if (cfg->type != PHY_TYPE_USB3) 1263 return 0; 1264 1265 if (!qmp->phy_initialized) { 1266 dev_vdbg(dev, "PHY not initialized, bailing out\n"); 1267 return 0; 1268 } 1269 1270 qcom_qmp_phy_enable_autonomous_mode(qphy); 1271 1272 clk_disable_unprepare(qphy->pipe_clk); 1273 clk_bulk_disable_unprepare(cfg->num_clks, qmp->clks); 1274 1275 return 0; 1276} 1277 1278static int __maybe_unused qcom_qmp_phy_runtime_resume(struct device *dev) 1279{ 1280 struct qcom_qmp *qmp = dev_get_drvdata(dev); 1281 struct qmp_phy *qphy = qmp->phys[0]; 1282 const struct qmp_phy_cfg *cfg = qmp->cfg; 1283 int ret = 0; 1284 1285 dev_vdbg(dev, "Resuming QMP phy, mode:%d\n", qmp->mode); 1286 1287 /* Supported only for USB3 PHY */ 1288 if (cfg->type != PHY_TYPE_USB3) 1289 return 0; 1290 1291 if (!qmp->phy_initialized) { 1292 dev_vdbg(dev, "PHY not initialized, bailing out\n"); 1293 return 0; 1294 } 1295 1296 ret = clk_bulk_prepare_enable(cfg->num_clks, qmp->clks); 1297 if (ret) { 1298 dev_err(qmp->dev, "failed to enable clks, err=%d\n", ret); 1299 return ret; 1300 } 1301 1302 ret = clk_prepare_enable(qphy->pipe_clk); 1303 if (ret) { 1304 dev_err(dev, "pipe_clk enable failed, err=%d\n", ret); 1305 clk_bulk_disable_unprepare(cfg->num_clks, qmp->clks); 1306 return ret; 1307 } 1308 1309 qcom_qmp_phy_disable_autonomous_mode(qphy); 1310 1311 return 0; 1312} 1313 1314static int qcom_qmp_phy_vreg_init(struct device *dev) 1315{ 1316 struct qcom_qmp *qmp = dev_get_drvdata(dev); 1317 int num = qmp->cfg->num_vregs; 1318 int i; 1319 1320 qmp->vregs = devm_kcalloc(dev, num, sizeof(*qmp->vregs), GFP_KERNEL); 1321 if (!qmp->vregs) 1322 return -ENOMEM; 1323 1324 for (i = 0; i < num; i++) 1325 qmp->vregs[i].supply = qmp->cfg->vreg_list[i]; 1326 1327 return devm_regulator_bulk_get(dev, num, qmp->vregs); 1328} 1329 1330static int qcom_qmp_phy_reset_init(struct device *dev) 1331{ 1332 struct qcom_qmp *qmp = dev_get_drvdata(dev); 1333 int i; 1334 1335 qmp->resets = devm_kcalloc(dev, qmp->cfg->num_resets, 1336 sizeof(*qmp->resets), GFP_KERNEL); 1337 if (!qmp->resets) 1338 return -ENOMEM; 1339 1340 for (i = 0; i < qmp->cfg->num_resets; i++) { 1341 struct reset_control *rst; 1342 const char *name = qmp->cfg->reset_list[i]; 1343 1344 rst = devm_reset_control_get(dev, name); 1345 if (IS_ERR(rst)) { 1346 dev_err(dev, "failed to get %s reset\n", name); 1347 return PTR_ERR(rst); 1348 } 1349 qmp->resets[i] = rst; 1350 } 1351 1352 return 0; 1353} 1354 1355static int qcom_qmp_phy_clk_init(struct device *dev) 1356{ 1357 struct qcom_qmp *qmp = dev_get_drvdata(dev); 1358 int num = qmp->cfg->num_clks; 1359 int i; 1360 1361 qmp->clks = devm_kcalloc(dev, num, sizeof(*qmp->clks), GFP_KERNEL); 1362 if (!qmp->clks) 1363 return -ENOMEM; 1364 1365 for (i = 0; i < num; i++) 1366 qmp->clks[i].id = qmp->cfg->clk_list[i]; 1367 1368 return devm_clk_bulk_get(dev, num, qmp->clks); 1369} 1370 1371/* 1372 * Register a fixed rate pipe clock. 1373 * 1374 * The <s>_pipe_clksrc generated by PHY goes to the GCC that gate 1375 * controls it. The <s>_pipe_clk coming out of the GCC is requested 1376 * by the PHY driver for its operations. 1377 * We register the <s>_pipe_clksrc here. The gcc driver takes care 1378 * of assigning this <s>_pipe_clksrc as parent to <s>_pipe_clk. 1379 * Below picture shows this relationship. 1380 * 1381 * +---------------+ 1382 * | PHY block |<<---------------------------------------+ 1383 * | | | 1384 * | +-------+ | +-----+ | 1385 * I/P---^-->| PLL |---^--->pipe_clksrc--->| GCC |--->pipe_clk---+ 1386 * clk | +-------+ | +-----+ 1387 * +---------------+ 1388 */ 1389static int phy_pipe_clk_register(struct qcom_qmp *qmp, struct device_node *np) 1390{ 1391 struct clk_fixed_rate *fixed; 1392 struct clk_init_data init = { }; 1393 int ret; 1394 1395 if ((qmp->cfg->type != PHY_TYPE_USB3) && 1396 (qmp->cfg->type != PHY_TYPE_PCIE)) { 1397 /* not all phys register pipe clocks, so return success */ 1398 return 0; 1399 } 1400 1401 ret = of_property_read_string(np, "clock-output-names", &init.name); 1402 if (ret) { 1403 dev_err(qmp->dev, "%s: No clock-output-names\n", np->name); 1404 return ret; 1405 } 1406 1407 fixed = devm_kzalloc(qmp->dev, sizeof(*fixed), GFP_KERNEL); 1408 if (!fixed) 1409 return -ENOMEM; 1410 1411 init.ops = &clk_fixed_rate_ops; 1412 1413 /* controllers using QMP phys use 125MHz pipe clock interface */ 1414 fixed->fixed_rate = 125000000; 1415 fixed->hw.init = &init; 1416 1417 return devm_clk_hw_register(qmp->dev, &fixed->hw); 1418} 1419 1420static const struct phy_ops qcom_qmp_phy_gen_ops = { 1421 .init = qcom_qmp_phy_init, 1422 .exit = qcom_qmp_phy_exit, 1423 .set_mode = qcom_qmp_phy_set_mode, 1424 .owner = THIS_MODULE, 1425}; 1426 1427static 1428int qcom_qmp_phy_create(struct device *dev, struct device_node *np, int id) 1429{ 1430 struct qcom_qmp *qmp = dev_get_drvdata(dev); 1431 struct phy *generic_phy; 1432 struct qmp_phy *qphy; 1433 char prop_name[MAX_PROP_NAME]; 1434 int ret; 1435 1436 qphy = devm_kzalloc(dev, sizeof(*qphy), GFP_KERNEL); 1437 if (!qphy) 1438 return -ENOMEM; 1439 1440 /* 1441 * Get memory resources for each phy lane: 1442 * Resources are indexed as: tx -> 0; rx -> 1; pcs -> 2; and 1443 * pcs_misc (optional) -> 3. 1444 */ 1445 qphy->tx = of_iomap(np, 0); 1446 if (!qphy->tx) 1447 return -ENOMEM; 1448 1449 qphy->rx = of_iomap(np, 1); 1450 if (!qphy->rx) 1451 return -ENOMEM; 1452 1453 qphy->pcs = of_iomap(np, 2); 1454 if (!qphy->pcs) 1455 return -ENOMEM; 1456 1457 qphy->pcs_misc = of_iomap(np, 3); 1458 if (!qphy->pcs_misc) 1459 dev_vdbg(dev, "PHY pcs_misc-reg not used\n"); 1460 1461 /* 1462 * Get PHY's Pipe clock, if any. USB3 and PCIe are PIPE3 1463 * based phys, so they essentially have pipe clock. So, 1464 * we return error in case phy is USB3 or PIPE type. 1465 * Otherwise, we initialize pipe clock to NULL for 1466 * all phys that don't need this. 1467 */ 1468 snprintf(prop_name, sizeof(prop_name), "pipe%d", id); 1469 qphy->pipe_clk = of_clk_get_by_name(np, prop_name); 1470 if (IS_ERR(qphy->pipe_clk)) { 1471 if (qmp->cfg->type == PHY_TYPE_PCIE || 1472 qmp->cfg->type == PHY_TYPE_USB3) { 1473 ret = PTR_ERR(qphy->pipe_clk); 1474 if (ret != -EPROBE_DEFER) 1475 dev_err(dev, 1476 "failed to get lane%d pipe_clk, %d\n", 1477 id, ret); 1478 return ret; 1479 } 1480 qphy->pipe_clk = NULL; 1481 } 1482 1483 /* Get lane reset, if any */ 1484 if (qmp->cfg->has_lane_rst) { 1485 snprintf(prop_name, sizeof(prop_name), "lane%d", id); 1486 qphy->lane_rst = of_reset_control_get(np, prop_name); 1487 if (IS_ERR(qphy->lane_rst)) { 1488 dev_err(dev, "failed to get lane%d reset\n", id); 1489 return PTR_ERR(qphy->lane_rst); 1490 } 1491 } 1492 1493 generic_phy = devm_phy_create(dev, np, &qcom_qmp_phy_gen_ops); 1494 if (IS_ERR(generic_phy)) { 1495 ret = PTR_ERR(generic_phy); 1496 dev_err(dev, "failed to create qphy %d\n", ret); 1497 return ret; 1498 } 1499 1500 qphy->phy = generic_phy; 1501 qphy->index = id; 1502 qphy->qmp = qmp; 1503 qmp->phys[id] = qphy; 1504 phy_set_drvdata(generic_phy, qphy); 1505 1506 return 0; 1507} 1508 1509static const struct of_device_id qcom_qmp_phy_of_match_table[] = { 1510 { 1511 .compatible = "qcom,msm8996-qmp-pcie-phy", 1512 .data = &msm8996_pciephy_cfg, 1513 }, { 1514 .compatible = "qcom,msm8996-qmp-usb3-phy", 1515 .data = &msm8996_usb3phy_cfg, 1516 }, { 1517 .compatible = "qcom,ipq8074-qmp-pcie-phy", 1518 .data = &ipq8074_pciephy_cfg, 1519 }, { 1520 .compatible = "qcom,sdm845-qmp-usb3-phy", 1521 .data = &qmp_v3_usb3phy_cfg, 1522 }, { 1523 .compatible = "qcom,sdm845-qmp-usb3-uni-phy", 1524 .data = &qmp_v3_usb3_uniphy_cfg, 1525 }, 1526 { }, 1527}; 1528MODULE_DEVICE_TABLE(of, qcom_qmp_phy_of_match_table); 1529 1530static const struct dev_pm_ops qcom_qmp_phy_pm_ops = { 1531 SET_RUNTIME_PM_OPS(qcom_qmp_phy_runtime_suspend, 1532 qcom_qmp_phy_runtime_resume, NULL) 1533}; 1534 1535static int qcom_qmp_phy_probe(struct platform_device *pdev) 1536{ 1537 struct qcom_qmp *qmp; 1538 struct device *dev = &pdev->dev; 1539 struct resource *res; 1540 struct device_node *child; 1541 struct phy_provider *phy_provider; 1542 void __iomem *base; 1543 int num, id; 1544 int ret; 1545 1546 qmp = devm_kzalloc(dev, sizeof(*qmp), GFP_KERNEL); 1547 if (!qmp) 1548 return -ENOMEM; 1549 1550 qmp->dev = dev; 1551 dev_set_drvdata(dev, qmp); 1552 1553 /* Get the specific init parameters of QMP phy */ 1554 qmp->cfg = of_device_get_match_data(dev); 1555 if (!qmp->cfg) 1556 return -EINVAL; 1557 1558 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1559 base = devm_ioremap_resource(dev, res); 1560 if (IS_ERR(base)) 1561 return PTR_ERR(base); 1562 1563 /* per PHY serdes; usually located at base address */ 1564 qmp->serdes = base; 1565 1566 /* per PHY dp_com; if PHY has dp_com control block */ 1567 if (qmp->cfg->has_phy_dp_com_ctrl) { 1568 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, 1569 "dp_com"); 1570 base = devm_ioremap_resource(dev, res); 1571 if (IS_ERR(base)) 1572 return PTR_ERR(base); 1573 1574 qmp->dp_com = base; 1575 } 1576 1577 mutex_init(&qmp->phy_mutex); 1578 1579 ret = qcom_qmp_phy_clk_init(dev); 1580 if (ret) 1581 return ret; 1582 1583 ret = qcom_qmp_phy_reset_init(dev); 1584 if (ret) 1585 return ret; 1586 1587 ret = qcom_qmp_phy_vreg_init(dev); 1588 if (ret) { 1589 dev_err(dev, "failed to get regulator supplies\n"); 1590 return ret; 1591 } 1592 1593 num = of_get_available_child_count(dev->of_node); 1594 /* do we have a rogue child node ? */ 1595 if (num > qmp->cfg->nlanes) 1596 return -EINVAL; 1597 1598 qmp->phys = devm_kcalloc(dev, num, sizeof(*qmp->phys), GFP_KERNEL); 1599 if (!qmp->phys) 1600 return -ENOMEM; 1601 1602 id = 0; 1603 pm_runtime_set_active(dev); 1604 pm_runtime_enable(dev); 1605 /* 1606 * Prevent runtime pm from being ON by default. Users can enable 1607 * it using power/control in sysfs. 1608 */ 1609 pm_runtime_forbid(dev); 1610 1611 for_each_available_child_of_node(dev->of_node, child) { 1612 /* Create per-lane phy */ 1613 ret = qcom_qmp_phy_create(dev, child, id); 1614 if (ret) { 1615 dev_err(dev, "failed to create lane%d phy, %d\n", 1616 id, ret); 1617 pm_runtime_disable(dev); 1618 return ret; 1619 } 1620 1621 /* 1622 * Register the pipe clock provided by phy. 1623 * See function description to see details of this pipe clock. 1624 */ 1625 ret = phy_pipe_clk_register(qmp, child); 1626 if (ret) { 1627 dev_err(qmp->dev, 1628 "failed to register pipe clock source\n"); 1629 pm_runtime_disable(dev); 1630 return ret; 1631 } 1632 id++; 1633 } 1634 1635 phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate); 1636 if (!IS_ERR(phy_provider)) 1637 dev_info(dev, "Registered Qcom-QMP phy\n"); 1638 else 1639 pm_runtime_disable(dev); 1640 1641 return PTR_ERR_OR_ZERO(phy_provider); 1642} 1643 1644static struct platform_driver qcom_qmp_phy_driver = { 1645 .probe = qcom_qmp_phy_probe, 1646 .driver = { 1647 .name = "qcom-qmp-phy", 1648 .pm = &qcom_qmp_phy_pm_ops, 1649 .of_match_table = qcom_qmp_phy_of_match_table, 1650 }, 1651}; 1652 1653module_platform_driver(qcom_qmp_phy_driver); 1654 1655MODULE_AUTHOR("Vivek Gautam <vivek.gautam@codeaurora.org>"); 1656MODULE_DESCRIPTION("Qualcomm QMP PHY driver"); 1657MODULE_LICENSE("GPL v2");