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1Qualcomm QMP PHY controller
2===========================
3
4QMP phy controller supports physical layer functionality for a number of
5controllers on Qualcomm chipsets, such as, PCIe, UFS, and USB.
6
7Required properties:
8 - compatible: compatible list, contains:
9 "qcom,ipq8074-qmp-pcie-phy" for PCIe phy on IPQ8074
10 "qcom,msm8996-qmp-pcie-phy" for 14nm PCIe phy on msm8996,
11 "qcom,msm8996-qmp-usb3-phy" for 14nm USB3 phy on msm8996,
12 "qcom,sdm845-qmp-usb3-phy" for USB3 QMP V3 phy on sdm845,
13 "qcom,sdm845-qmp-usb3-uni-phy" for USB3 QMP V3 UNI phy on sdm845.
14
15 - reg: offset and length of register set for PHY's common serdes block.
16
17 - #clock-cells: must be 1
18 - Phy pll outputs a bunch of clocks for Tx, Rx and Pipe
19 interface (for pipe based PHYs). These clock are then gate-controlled
20 by gcc.
21 - #address-cells: must be 1
22 - #size-cells: must be 1
23 - ranges: must be present
24
25 - clocks: a list of phandles and clock-specifier pairs,
26 one for each entry in clock-names.
27 - clock-names: "cfg_ahb" for phy config clock,
28 "aux" for phy aux clock,
29 "ref" for 19.2 MHz ref clk,
30 "com_aux" for phy common block aux clock,
31 For "qcom,msm8996-qmp-pcie-phy" must contain:
32 "aux", "cfg_ahb", "ref".
33 For "qcom,msm8996-qmp-usb3-phy" must contain:
34 "aux", "cfg_ahb", "ref".
35 For "qcom,qmp-v3-usb3-phy" must contain:
36 "aux", "cfg_ahb", "ref", "com_aux".
37
38 - resets: a list of phandles and reset controller specifier pairs,
39 one for each entry in reset-names.
40 - reset-names: "phy" for reset of phy block,
41 "common" for phy common block reset,
42 "cfg" for phy's ahb cfg block reset (Optional).
43 For "qcom,msm8996-qmp-pcie-phy" must contain:
44 "phy", "common", "cfg".
45 For "qcom,msm8996-qmp-usb3-phy" must contain
46 "phy", "common".
47 For "qcom,ipq8074-qmp-pcie-phy" must contain:
48 "phy", "common".
49
50 - vdda-phy-supply: Phandle to a regulator supply to PHY core block.
51 - vdda-pll-supply: Phandle to 1.8V regulator supply to PHY refclk pll block.
52
53Optional properties:
54 - vddp-ref-clk-supply: Phandle to a regulator supply to any specific refclk
55 pll block.
56
57Required nodes:
58 - Each device node of QMP phy is required to have as many child nodes as
59 the number of lanes the PHY has.
60
61Required properties for child node:
62 - reg: list of offset and length pairs of register sets for PHY blocks -
63 tx, rx and pcs.
64
65 - #phy-cells: must be 0
66
67 - clocks: a list of phandles and clock-specifier pairs,
68 one for each entry in clock-names.
69 - clock-names: Must contain following for pcie and usb qmp phys:
70 "pipe<lane-number>" for pipe clock specific to each lane.
71 - clock-output-names: Name of the PHY clock that will be the parent for
72 the above pipe clock.
73
74 For "qcom,ipq8074-qmp-pcie-phy":
75 - "pcie20_phy0_pipe_clk" Pipe Clock parent
76 (or)
77 "pcie20_phy1_pipe_clk"
78
79 - resets: a list of phandles and reset controller specifier pairs,
80 one for each entry in reset-names.
81 - reset-names: Must contain following for pcie qmp phys:
82 "lane<lane-number>" for reset specific to each lane.
83
84Example:
85 phy@34000 {
86 compatible = "qcom,msm8996-qmp-pcie-phy";
87 reg = <0x34000 0x488>;
88 #clock-cells = <1>;
89 #address-cells = <1>;
90 #size-cells = <1>;
91 ranges;
92
93 clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>,
94 <&gcc GCC_PCIE_PHY_CFG_AHB_CLK>,
95 <&gcc GCC_PCIE_CLKREF_CLK>;
96 clock-names = "aux", "cfg_ahb", "ref";
97
98 vdda-phy-supply = <&pm8994_l28>;
99 vdda-pll-supply = <&pm8994_l12>;
100
101 resets = <&gcc GCC_PCIE_PHY_BCR>,
102 <&gcc GCC_PCIE_PHY_COM_BCR>,
103 <&gcc GCC_PCIE_PHY_COM_NOCSR_BCR>;
104 reset-names = "phy", "common", "cfg";
105
106 pciephy_0: lane@35000 {
107 reg = <0x35000 0x130>,
108 <0x35200 0x200>,
109 <0x35400 0x1dc>;
110 #phy-cells = <0>;
111
112 clocks = <&gcc GCC_PCIE_0_PIPE_CLK>;
113 clock-names = "pipe0";
114 clock-output-names = "pcie_0_pipe_clk_src";
115 resets = <&gcc GCC_PCIE_0_PHY_BCR>;
116 reset-names = "lane0";
117 };
118
119 pciephy_1: lane@36000 {
120 ...
121 ...
122 };