Linux kernel mirror (for testing)
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linux
1/* SPDX-License-Identifier: GPL-2.0 */
2#ifndef _LINUX_BRCMPHY_H
3#define _LINUX_BRCMPHY_H
4
5#include <linux/phy.h>
6
7/* All Broadcom Ethernet switches have a pseudo-PHY at address 30 which is used
8 * to configure the switch internal registers via MDIO accesses.
9 */
10#define BRCM_PSEUDO_PHY_ADDR 30
11
12#define PHY_ID_BCM50610 0x0143bd60
13#define PHY_ID_BCM50610M 0x0143bd70
14#define PHY_ID_BCM5241 0x0143bc30
15#define PHY_ID_BCMAC131 0x0143bc70
16#define PHY_ID_BCM5481 0x0143bca0
17#define PHY_ID_BCM5395 0x0143bcf0
18#define PHY_ID_BCM54810 0x03625d00
19#define PHY_ID_BCM5482 0x0143bcb0
20#define PHY_ID_BCM5411 0x00206070
21#define PHY_ID_BCM5421 0x002060e0
22#define PHY_ID_BCM54210E 0x600d84a0
23#define PHY_ID_BCM5464 0x002060b0
24#define PHY_ID_BCM5461 0x002060c0
25#define PHY_ID_BCM54612E 0x03625e60
26#define PHY_ID_BCM54616S 0x03625d10
27#define PHY_ID_BCM57780 0x03625d90
28#define PHY_ID_BCM89610 0x03625cd0
29
30#define PHY_ID_BCM7250 0xae025280
31#define PHY_ID_BCM7260 0xae025190
32#define PHY_ID_BCM7268 0xae025090
33#define PHY_ID_BCM7271 0xae0253b0
34#define PHY_ID_BCM7278 0xae0251a0
35#define PHY_ID_BCM7364 0xae025260
36#define PHY_ID_BCM7366 0x600d8490
37#define PHY_ID_BCM7346 0x600d8650
38#define PHY_ID_BCM7362 0x600d84b0
39#define PHY_ID_BCM7425 0x600d86b0
40#define PHY_ID_BCM7429 0x600d8730
41#define PHY_ID_BCM7435 0x600d8750
42#define PHY_ID_BCM74371 0xae0252e0
43#define PHY_ID_BCM7439 0x600d8480
44#define PHY_ID_BCM7439_2 0xae025080
45#define PHY_ID_BCM7445 0x600d8510
46
47#define PHY_ID_BCM_CYGNUS 0xae025200
48
49#define PHY_BCM_OUI_MASK 0xfffffc00
50#define PHY_BCM_OUI_1 0x00206000
51#define PHY_BCM_OUI_2 0x0143bc00
52#define PHY_BCM_OUI_3 0x03625c00
53#define PHY_BCM_OUI_4 0x600d8400
54#define PHY_BCM_OUI_5 0x03625e00
55#define PHY_BCM_OUI_6 0xae025000
56
57#define PHY_BCM_FLAGS_MODE_COPPER 0x00000001
58#define PHY_BCM_FLAGS_MODE_1000BX 0x00000002
59#define PHY_BCM_FLAGS_INTF_SGMII 0x00000010
60#define PHY_BCM_FLAGS_INTF_XAUI 0x00000020
61#define PHY_BRCM_WIRESPEED_ENABLE 0x00000100
62#define PHY_BRCM_AUTO_PWRDWN_ENABLE 0x00000200
63#define PHY_BRCM_RX_REFCLK_UNUSED 0x00000400
64#define PHY_BRCM_STD_IBND_DISABLE 0x00000800
65#define PHY_BRCM_EXT_IBND_RX_ENABLE 0x00001000
66#define PHY_BRCM_EXT_IBND_TX_ENABLE 0x00002000
67#define PHY_BRCM_CLEAR_RGMII_MODE 0x00004000
68#define PHY_BRCM_DIS_TXCRXC_NOENRGY 0x00008000
69#define PHY_BRCM_EN_MASTER_MODE 0x00010000
70
71/* Broadcom BCM7xxx specific workarounds */
72#define PHY_BRCM_7XXX_REV(x) (((x) >> 8) & 0xff)
73#define PHY_BRCM_7XXX_PATCH(x) ((x) & 0xff)
74#define PHY_BCM_FLAGS_VALID 0x80000000
75
76/* Broadcom BCM54XX register definitions, common to most Broadcom PHYs */
77#define MII_BCM54XX_ECR 0x10 /* BCM54xx extended control register */
78#define MII_BCM54XX_ECR_IM 0x1000 /* Interrupt mask */
79#define MII_BCM54XX_ECR_IF 0x0800 /* Interrupt force */
80
81#define MII_BCM54XX_ESR 0x11 /* BCM54xx extended status register */
82#define MII_BCM54XX_ESR_IS 0x1000 /* Interrupt status */
83
84#define MII_BCM54XX_EXP_DATA 0x15 /* Expansion register data */
85#define MII_BCM54XX_EXP_SEL 0x17 /* Expansion register select */
86#define MII_BCM54XX_EXP_SEL_SSD 0x0e00 /* Secondary SerDes select */
87#define MII_BCM54XX_EXP_SEL_ER 0x0f00 /* Expansion register select */
88
89#define MII_BCM54XX_AUX_CTL 0x18 /* Auxiliary control register */
90#define MII_BCM54XX_ISR 0x1a /* BCM54xx interrupt status register */
91#define MII_BCM54XX_IMR 0x1b /* BCM54xx interrupt mask register */
92#define MII_BCM54XX_INT_CRCERR 0x0001 /* CRC error */
93#define MII_BCM54XX_INT_LINK 0x0002 /* Link status changed */
94#define MII_BCM54XX_INT_SPEED 0x0004 /* Link speed change */
95#define MII_BCM54XX_INT_DUPLEX 0x0008 /* Duplex mode changed */
96#define MII_BCM54XX_INT_LRS 0x0010 /* Local receiver status changed */
97#define MII_BCM54XX_INT_RRS 0x0020 /* Remote receiver status changed */
98#define MII_BCM54XX_INT_SSERR 0x0040 /* Scrambler synchronization error */
99#define MII_BCM54XX_INT_UHCD 0x0080 /* Unsupported HCD negotiated */
100#define MII_BCM54XX_INT_NHCD 0x0100 /* No HCD */
101#define MII_BCM54XX_INT_NHCDL 0x0200 /* No HCD link */
102#define MII_BCM54XX_INT_ANPR 0x0400 /* Auto-negotiation page received */
103#define MII_BCM54XX_INT_LC 0x0800 /* All counters below 128 */
104#define MII_BCM54XX_INT_HC 0x1000 /* Counter above 32768 */
105#define MII_BCM54XX_INT_MDIX 0x2000 /* MDIX status change */
106#define MII_BCM54XX_INT_PSERR 0x4000 /* Pair swap error */
107
108#define MII_BCM54XX_SHD 0x1c /* 0x1c shadow registers */
109#define MII_BCM54XX_SHD_WRITE 0x8000
110#define MII_BCM54XX_SHD_VAL(x) ((x & 0x1f) << 10)
111#define MII_BCM54XX_SHD_DATA(x) ((x & 0x3ff) << 0)
112
113/*
114 * AUXILIARY CONTROL SHADOW ACCESS REGISTERS. (PHY REG 0x18)
115 */
116#define MII_BCM54XX_AUXCTL_SHDWSEL_AUXCTL 0x00
117#define MII_BCM54XX_AUXCTL_ACTL_TX_6DB 0x0400
118#define MII_BCM54XX_AUXCTL_ACTL_SMDSP_ENA 0x0800
119
120#define MII_BCM54XX_AUXCTL_SHDWSEL_MISC 0x07
121#define MII_BCM54XX_AUXCTL_SHDWSEL_MISC_WIRESPEED_EN 0x0010
122#define MII_BCM54XX_AUXCTL_SHDWSEL_MISC_RGMII_SKEW_EN 0x0100
123#define MII_BCM54XX_AUXCTL_MISC_FORCE_AMDIX 0x0200
124#define MII_BCM54XX_AUXCTL_MISC_WREN 0x8000
125
126#define MII_BCM54XX_AUXCTL_SHDWSEL_READ_SHIFT 12
127#define MII_BCM54XX_AUXCTL_SHDWSEL_MASK 0x0007
128
129/*
130 * Broadcom LED source encodings. These are used in BCM5461, BCM5481,
131 * BCM5482, and possibly some others.
132 */
133#define BCM_LED_SRC_LINKSPD1 0x0
134#define BCM_LED_SRC_LINKSPD2 0x1
135#define BCM_LED_SRC_XMITLED 0x2
136#define BCM_LED_SRC_ACTIVITYLED 0x3
137#define BCM_LED_SRC_FDXLED 0x4
138#define BCM_LED_SRC_SLAVE 0x5
139#define BCM_LED_SRC_INTR 0x6
140#define BCM_LED_SRC_QUALITY 0x7
141#define BCM_LED_SRC_RCVLED 0x8
142#define BCM_LED_SRC_WIRESPEED 0x9
143#define BCM_LED_SRC_MULTICOLOR1 0xa
144#define BCM_LED_SRC_OPENSHORT 0xb
145#define BCM_LED_SRC_OFF 0xe /* Tied high */
146#define BCM_LED_SRC_ON 0xf /* Tied low */
147
148
149/*
150 * BCM5482: Shadow registers
151 * Shadow values go into bits [14:10] of register 0x1c to select a shadow
152 * register to access.
153 */
154
155/* 00100: Reserved control register 2 */
156#define BCM54XX_SHD_SCR2 0x04
157#define BCM54XX_SHD_SCR2_WSPD_RTRY_DIS 0x100
158#define BCM54XX_SHD_SCR2_WSPD_RTRY_LMT_SHIFT 2
159#define BCM54XX_SHD_SCR2_WSPD_RTRY_LMT_OFFSET 2
160#define BCM54XX_SHD_SCR2_WSPD_RTRY_LMT_MASK 0x7
161
162/* 00101: Spare Control Register 3 */
163#define BCM54XX_SHD_SCR3 0x05
164#define BCM54XX_SHD_SCR3_DEF_CLK125 0x0001
165#define BCM54XX_SHD_SCR3_DLLAPD_DIS 0x0002
166#define BCM54XX_SHD_SCR3_TRDDAPD 0x0004
167
168/* 01010: Auto Power-Down */
169#define BCM54XX_SHD_APD 0x0a
170#define BCM_APD_CLR_MASK 0xFE9F /* clear bits 5, 6 & 8 */
171#define BCM54XX_SHD_APD_EN 0x0020
172#define BCM_NO_ANEG_APD_EN 0x0060 /* bits 5 & 6 */
173#define BCM_APD_SINGLELP_EN 0x0100 /* Bit 8 */
174
175#define BCM5482_SHD_LEDS1 0x0d /* 01101: LED Selector 1 */
176 /* LED3 / ~LINKSPD[2] selector */
177#define BCM5482_SHD_LEDS1_LED3(src) ((src & 0xf) << 4)
178 /* LED1 / ~LINKSPD[1] selector */
179#define BCM5482_SHD_LEDS1_LED1(src) ((src & 0xf) << 0)
180#define BCM54XX_SHD_RGMII_MODE 0x0b /* 01011: RGMII Mode Selector */
181#define BCM5482_SHD_SSD 0x14 /* 10100: Secondary SerDes control */
182#define BCM5482_SHD_SSD_LEDM 0x0008 /* SSD LED Mode enable */
183#define BCM5482_SHD_SSD_EN 0x0001 /* SSD enable */
184#define BCM5482_SHD_MODE 0x1f /* 11111: Mode Control Register */
185#define BCM5482_SHD_MODE_1000BX 0x0001 /* Enable 1000BASE-X registers */
186
187
188/*
189 * EXPANSION SHADOW ACCESS REGISTERS. (PHY REG 0x15, 0x16, and 0x17)
190 */
191#define MII_BCM54XX_EXP_AADJ1CH0 0x001f
192#define MII_BCM54XX_EXP_AADJ1CH0_SWP_ABCD_OEN 0x0200
193#define MII_BCM54XX_EXP_AADJ1CH0_SWSEL_THPF 0x0100
194#define MII_BCM54XX_EXP_AADJ1CH3 0x601f
195#define MII_BCM54XX_EXP_AADJ1CH3_ADCCKADJ 0x0002
196#define MII_BCM54XX_EXP_EXP08 0x0F08
197#define MII_BCM54XX_EXP_EXP08_RJCT_2MHZ 0x0001
198#define MII_BCM54XX_EXP_EXP08_EARLY_DAC_WAKE 0x0200
199#define MII_BCM54XX_EXP_EXP75 0x0f75
200#define MII_BCM54XX_EXP_EXP75_VDACCTRL 0x003c
201#define MII_BCM54XX_EXP_EXP75_CM_OSC 0x0001
202#define MII_BCM54XX_EXP_EXP96 0x0f96
203#define MII_BCM54XX_EXP_EXP96_MYST 0x0010
204#define MII_BCM54XX_EXP_EXP97 0x0f97
205#define MII_BCM54XX_EXP_EXP97_MYST 0x0c0c
206
207/*
208 * BCM5482: Secondary SerDes registers
209 */
210#define BCM5482_SSD_1000BX_CTL 0x00 /* 1000BASE-X Control */
211#define BCM5482_SSD_1000BX_CTL_PWRDOWN 0x0800 /* Power-down SSD */
212#define BCM5482_SSD_SGMII_SLAVE 0x15 /* SGMII Slave Register */
213#define BCM5482_SSD_SGMII_SLAVE_EN 0x0002 /* Slave mode enable */
214#define BCM5482_SSD_SGMII_SLAVE_AD 0x0001 /* Slave auto-detection */
215
216/* BCM54810 Registers */
217#define BCM54810_EXP_BROADREACH_LRE_MISC_CTL (MII_BCM54XX_EXP_SEL_ER + 0x90)
218#define BCM54810_EXP_BROADREACH_LRE_MISC_CTL_EN (1 << 0)
219#define BCM54810_SHD_CLK_CTL 0x3
220#define BCM54810_SHD_CLK_CTL_GTXCLK_EN (1 << 9)
221
222
223/*****************************************************************************/
224/* Fast Ethernet Transceiver definitions. */
225/*****************************************************************************/
226
227#define MII_BRCM_FET_INTREG 0x1a /* Interrupt register */
228#define MII_BRCM_FET_IR_MASK 0x0100 /* Mask all interrupts */
229#define MII_BRCM_FET_IR_LINK_EN 0x0200 /* Link status change enable */
230#define MII_BRCM_FET_IR_SPEED_EN 0x0400 /* Link speed change enable */
231#define MII_BRCM_FET_IR_DUPLEX_EN 0x0800 /* Duplex mode change enable */
232#define MII_BRCM_FET_IR_ENABLE 0x4000 /* Interrupt enable */
233
234#define MII_BRCM_FET_BRCMTEST 0x1f /* Brcm test register */
235#define MII_BRCM_FET_BT_SRE 0x0080 /* Shadow register enable */
236
237
238/*** Shadow register definitions ***/
239
240#define MII_BRCM_FET_SHDW_MISCCTRL 0x10 /* Shadow misc ctrl */
241#define MII_BRCM_FET_SHDW_MC_FAME 0x4000 /* Force Auto MDIX enable */
242
243#define MII_BRCM_FET_SHDW_AUXMODE4 0x1a /* Auxiliary mode 4 */
244#define MII_BRCM_FET_SHDW_AM4_LED_MASK 0x0003
245#define MII_BRCM_FET_SHDW_AM4_LED_MODE1 0x0001
246
247#define MII_BRCM_FET_SHDW_AUXSTAT2 0x1b /* Auxiliary status 2 */
248#define MII_BRCM_FET_SHDW_AS2_APDE 0x0020 /* Auto power down enable */
249
250#define BRCM_CL45VEN_EEE_CONTROL 0x803d
251#define LPI_FEATURE_EN 0x8000
252#define LPI_FEATURE_EN_DIG1000X 0x4000
253
254/* Core register definitions*/
255#define MII_BRCM_CORE_BASE12 0x12
256#define MII_BRCM_CORE_BASE13 0x13
257#define MII_BRCM_CORE_BASE14 0x14
258#define MII_BRCM_CORE_BASE1E 0x1E
259#define MII_BRCM_CORE_EXPB0 0xB0
260#define MII_BRCM_CORE_EXPB1 0xB1
261
262#endif /* _LINUX_BRCMPHY_H */