tjh.dev
Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
1/*
2 * omap iommu: main structures
3 *
4 * Copyright (C) 2008-2009 Nokia Corporation
5 *
6 * Written by Hiroshi DOYU <Hiroshi.DOYU@nokia.com>
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 */
12
13#ifndef _OMAP_IOMMU_H
14#define _OMAP_IOMMU_H
15
16#include <linux/bitops.h>
17#include <linux/iommu.h>
18
19#define for_each_iotlb_cr(obj, n, __i, cr) \
20 for (__i = 0; \
21 (__i < (n)) && (cr = __iotlb_read_cr((obj), __i), true); \
22 __i++)
23
24struct iotlb_entry {
25 u32 da;
26 u32 pa;
27 u32 pgsz, prsvd, valid;
28 u32 endian, elsz, mixed;
29};
30
31/**
32 * struct omap_iommu_device - omap iommu device data
33 * @pgtable: page table used by an omap iommu attached to a domain
34 * @iommu_dev: pointer to store an omap iommu instance attached to a domain
35 */
36struct omap_iommu_device {
37 u32 *pgtable;
38 struct omap_iommu *iommu_dev;
39};
40
41/**
42 * struct omap_iommu_domain - omap iommu domain
43 * @num_iommus: number of iommus in this domain
44 * @iommus: omap iommu device data for all iommus in this domain
45 * @dev: Device using this domain.
46 * @lock: domain lock, should be taken when attaching/detaching
47 * @domain: generic domain handle used by iommu core code
48 */
49struct omap_iommu_domain {
50 u32 num_iommus;
51 struct omap_iommu_device *iommus;
52 struct device *dev;
53 spinlock_t lock;
54 struct iommu_domain domain;
55};
56
57struct omap_iommu {
58 const char *name;
59 void __iomem *regbase;
60 struct regmap *syscfg;
61 struct device *dev;
62 struct iommu_domain *domain;
63 struct dentry *debug_dir;
64
65 spinlock_t iommu_lock; /* global for this whole object */
66
67 /*
68 * We don't change iopgd for a situation like pgd for a task,
69 * but share it globally for each iommu.
70 */
71 u32 *iopgd;
72 spinlock_t page_table_lock; /* protect iopgd */
73 dma_addr_t pd_dma;
74
75 int nr_tlb_entries;
76
77 void *ctx; /* iommu context: registres saved area */
78
79 int has_bus_err_back;
80 u32 id;
81
82 struct iommu_device iommu;
83 struct iommu_group *group;
84};
85
86/**
87 * struct omap_iommu_arch_data - omap iommu private data
88 * @iommu_dev: handle of the iommu device
89 *
90 * This is an omap iommu private data object, which binds an iommu user
91 * to its iommu device. This object should be placed at the iommu user's
92 * dev_archdata so generic IOMMU API can be used without having to
93 * utilize omap-specific plumbing anymore.
94 */
95struct omap_iommu_arch_data {
96 struct omap_iommu *iommu_dev;
97};
98
99struct cr_regs {
100 u32 cam;
101 u32 ram;
102};
103
104struct iotlb_lock {
105 short base;
106 short vict;
107};
108
109/*
110 * MMU Register offsets
111 */
112#define MMU_REVISION 0x00
113#define MMU_IRQSTATUS 0x18
114#define MMU_IRQENABLE 0x1c
115#define MMU_WALKING_ST 0x40
116#define MMU_CNTL 0x44
117#define MMU_FAULT_AD 0x48
118#define MMU_TTB 0x4c
119#define MMU_LOCK 0x50
120#define MMU_LD_TLB 0x54
121#define MMU_CAM 0x58
122#define MMU_RAM 0x5c
123#define MMU_GFLUSH 0x60
124#define MMU_FLUSH_ENTRY 0x64
125#define MMU_READ_CAM 0x68
126#define MMU_READ_RAM 0x6c
127#define MMU_EMU_FAULT_AD 0x70
128#define MMU_GP_REG 0x88
129
130#define MMU_REG_SIZE 256
131
132/*
133 * MMU Register bit definitions
134 */
135/* IRQSTATUS & IRQENABLE */
136#define MMU_IRQ_MULTIHITFAULT BIT(4)
137#define MMU_IRQ_TABLEWALKFAULT BIT(3)
138#define MMU_IRQ_EMUMISS BIT(2)
139#define MMU_IRQ_TRANSLATIONFAULT BIT(1)
140#define MMU_IRQ_TLBMISS BIT(0)
141
142#define __MMU_IRQ_FAULT \
143 (MMU_IRQ_MULTIHITFAULT | MMU_IRQ_EMUMISS | MMU_IRQ_TRANSLATIONFAULT)
144#define MMU_IRQ_MASK \
145 (__MMU_IRQ_FAULT | MMU_IRQ_TABLEWALKFAULT | MMU_IRQ_TLBMISS)
146#define MMU_IRQ_TWL_MASK (__MMU_IRQ_FAULT | MMU_IRQ_TABLEWALKFAULT)
147#define MMU_IRQ_TLB_MISS_MASK (__MMU_IRQ_FAULT | MMU_IRQ_TLBMISS)
148
149/* MMU_CNTL */
150#define MMU_CNTL_SHIFT 1
151#define MMU_CNTL_MASK (7 << MMU_CNTL_SHIFT)
152#define MMU_CNTL_EML_TLB BIT(3)
153#define MMU_CNTL_TWL_EN BIT(2)
154#define MMU_CNTL_MMU_EN BIT(1)
155
156/* CAM */
157#define MMU_CAM_VATAG_SHIFT 12
158#define MMU_CAM_VATAG_MASK \
159 ((~0UL >> MMU_CAM_VATAG_SHIFT) << MMU_CAM_VATAG_SHIFT)
160#define MMU_CAM_P BIT(3)
161#define MMU_CAM_V BIT(2)
162#define MMU_CAM_PGSZ_MASK 3
163#define MMU_CAM_PGSZ_1M (0 << 0)
164#define MMU_CAM_PGSZ_64K (1 << 0)
165#define MMU_CAM_PGSZ_4K (2 << 0)
166#define MMU_CAM_PGSZ_16M (3 << 0)
167
168/* RAM */
169#define MMU_RAM_PADDR_SHIFT 12
170#define MMU_RAM_PADDR_MASK \
171 ((~0UL >> MMU_RAM_PADDR_SHIFT) << MMU_RAM_PADDR_SHIFT)
172
173#define MMU_RAM_ENDIAN_SHIFT 9
174#define MMU_RAM_ENDIAN_MASK BIT(MMU_RAM_ENDIAN_SHIFT)
175#define MMU_RAM_ENDIAN_LITTLE (0 << MMU_RAM_ENDIAN_SHIFT)
176#define MMU_RAM_ENDIAN_BIG BIT(MMU_RAM_ENDIAN_SHIFT)
177
178#define MMU_RAM_ELSZ_SHIFT 7
179#define MMU_RAM_ELSZ_MASK (3 << MMU_RAM_ELSZ_SHIFT)
180#define MMU_RAM_ELSZ_8 (0 << MMU_RAM_ELSZ_SHIFT)
181#define MMU_RAM_ELSZ_16 (1 << MMU_RAM_ELSZ_SHIFT)
182#define MMU_RAM_ELSZ_32 (2 << MMU_RAM_ELSZ_SHIFT)
183#define MMU_RAM_ELSZ_NONE (3 << MMU_RAM_ELSZ_SHIFT)
184#define MMU_RAM_MIXED_SHIFT 6
185#define MMU_RAM_MIXED_MASK BIT(MMU_RAM_MIXED_SHIFT)
186#define MMU_RAM_MIXED MMU_RAM_MIXED_MASK
187
188#define MMU_GP_REG_BUS_ERR_BACK_EN 0x1
189
190#define get_cam_va_mask(pgsz) \
191 (((pgsz) == MMU_CAM_PGSZ_16M) ? 0xff000000 : \
192 ((pgsz) == MMU_CAM_PGSZ_1M) ? 0xfff00000 : \
193 ((pgsz) == MMU_CAM_PGSZ_64K) ? 0xffff0000 : \
194 ((pgsz) == MMU_CAM_PGSZ_4K) ? 0xfffff000 : 0)
195
196/*
197 * DSP_SYSTEM registers and bit definitions (applicable only for DRA7xx DSP)
198 */
199#define DSP_SYS_REVISION 0x00
200#define DSP_SYS_MMU_CONFIG 0x18
201#define DSP_SYS_MMU_CONFIG_EN_SHIFT 4
202
203/*
204 * utilities for super page(16MB, 1MB, 64KB and 4KB)
205 */
206
207#define iopgsz_max(bytes) \
208 (((bytes) >= SZ_16M) ? SZ_16M : \
209 ((bytes) >= SZ_1M) ? SZ_1M : \
210 ((bytes) >= SZ_64K) ? SZ_64K : \
211 ((bytes) >= SZ_4K) ? SZ_4K : 0)
212
213#define bytes_to_iopgsz(bytes) \
214 (((bytes) == SZ_16M) ? MMU_CAM_PGSZ_16M : \
215 ((bytes) == SZ_1M) ? MMU_CAM_PGSZ_1M : \
216 ((bytes) == SZ_64K) ? MMU_CAM_PGSZ_64K : \
217 ((bytes) == SZ_4K) ? MMU_CAM_PGSZ_4K : -1)
218
219#define iopgsz_to_bytes(iopgsz) \
220 (((iopgsz) == MMU_CAM_PGSZ_16M) ? SZ_16M : \
221 ((iopgsz) == MMU_CAM_PGSZ_1M) ? SZ_1M : \
222 ((iopgsz) == MMU_CAM_PGSZ_64K) ? SZ_64K : \
223 ((iopgsz) == MMU_CAM_PGSZ_4K) ? SZ_4K : 0)
224
225#define iopgsz_ok(bytes) (bytes_to_iopgsz(bytes) >= 0)
226
227/*
228 * global functions
229 */
230
231struct cr_regs __iotlb_read_cr(struct omap_iommu *obj, int n);
232void iotlb_lock_get(struct omap_iommu *obj, struct iotlb_lock *l);
233void iotlb_lock_set(struct omap_iommu *obj, struct iotlb_lock *l);
234
235#ifdef CONFIG_OMAP_IOMMU_DEBUG
236void omap_iommu_debugfs_init(void);
237void omap_iommu_debugfs_exit(void);
238
239void omap_iommu_debugfs_add(struct omap_iommu *obj);
240void omap_iommu_debugfs_remove(struct omap_iommu *obj);
241#else
242static inline void omap_iommu_debugfs_init(void) { }
243static inline void omap_iommu_debugfs_exit(void) { }
244
245static inline void omap_iommu_debugfs_add(struct omap_iommu *obj) { }
246static inline void omap_iommu_debugfs_remove(struct omap_iommu *obj) { }
247#endif
248
249/*
250 * register accessors
251 */
252static inline u32 iommu_read_reg(struct omap_iommu *obj, size_t offs)
253{
254 return __raw_readl(obj->regbase + offs);
255}
256
257static inline void iommu_write_reg(struct omap_iommu *obj, u32 val, size_t offs)
258{
259 __raw_writel(val, obj->regbase + offs);
260}
261
262static inline int iotlb_cr_valid(struct cr_regs *cr)
263{
264 if (!cr)
265 return -EINVAL;
266
267 return cr->cam & MMU_CAM_V;
268}
269
270#endif /* _OMAP_IOMMU_H */