Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
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linux
1/*
2 * Copyright (C) 2012 ARM Ltd.
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope that it will be useful,
9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
12 *
13 * You should have received a copy of the GNU General Public License
14 * along with this program. If not, see <http://www.gnu.org/licenses/>.
15 */
16#ifndef __ASM_CACHE_H
17#define __ASM_CACHE_H
18
19#include <asm/cputype.h>
20
21#define CTR_L1IP_SHIFT 14
22#define CTR_L1IP_MASK 3
23#define CTR_DMINLINE_SHIFT 16
24#define CTR_ERG_SHIFT 20
25#define CTR_CWG_SHIFT 24
26#define CTR_CWG_MASK 15
27#define CTR_IDC_SHIFT 28
28#define CTR_DIC_SHIFT 29
29
30#define CTR_L1IP(ctr) (((ctr) >> CTR_L1IP_SHIFT) & CTR_L1IP_MASK)
31
32#define ICACHE_POLICY_VPIPT 0
33#define ICACHE_POLICY_VIPT 2
34#define ICACHE_POLICY_PIPT 3
35
36#define L1_CACHE_SHIFT 7
37#define L1_CACHE_BYTES (1 << L1_CACHE_SHIFT)
38
39/*
40 * Memory returned by kmalloc() may be used for DMA, so we must make
41 * sure that all such allocations are cache aligned. Otherwise,
42 * unrelated code may cause parts of the buffer to be read into the
43 * cache before the transfer is done, causing old data to be seen by
44 * the CPU.
45 */
46#define ARCH_DMA_MINALIGN L1_CACHE_BYTES
47
48#ifndef __ASSEMBLY__
49
50#include <linux/bitops.h>
51
52#define ICACHEF_ALIASING 0
53#define ICACHEF_VPIPT 1
54extern unsigned long __icache_flags;
55
56/*
57 * Whilst the D-side always behaves as PIPT on AArch64, aliasing is
58 * permitted in the I-cache.
59 */
60static inline int icache_is_aliasing(void)
61{
62 return test_bit(ICACHEF_ALIASING, &__icache_flags);
63}
64
65static inline int icache_is_vpipt(void)
66{
67 return test_bit(ICACHEF_VPIPT, &__icache_flags);
68}
69
70static inline u32 cache_type_cwg(void)
71{
72 return (read_cpuid_cachetype() >> CTR_CWG_SHIFT) & CTR_CWG_MASK;
73}
74
75#define __read_mostly __attribute__((__section__(".data..read_mostly")))
76
77static inline int cache_line_size(void)
78{
79 u32 cwg = cache_type_cwg();
80 return cwg ? 4 << cwg : L1_CACHE_BYTES;
81}
82
83#endif /* __ASSEMBLY__ */
84
85#endif