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1* STMicroelectronics STM32 lcd-tft display controller
2
3- ltdc: lcd-tft display controller host
4 Required properties:
5 - compatible: "st,stm32-ltdc"
6 - reg: Physical base address of the IP registers and length of memory mapped region.
7 - clocks: A list of phandle + clock-specifier pairs, one for each
8 entry in 'clock-names'.
9 - clock-names: A list of clock names. For ltdc it should contain:
10 - "lcd" for the clock feeding the output pixel clock & IP clock.
11 - resets: reset to be used by the device (defined by use of RCC macro).
12 Required nodes:
13 - Video port for DPI RGB output: ltdc has one video port with up to 2
14 endpoints:
15 - for external dpi rgb panel or bridge, using gpios.
16 - for internal dpi input of the MIPI DSI host controller.
17 Note: These 2 endpoints cannot be activated simultaneously.
18
19* STMicroelectronics STM32 DSI controller specific extensions to Synopsys
20 DesignWare MIPI DSI host controller
21
22The STMicroelectronics STM32 DSI controller uses the Synopsys DesignWare MIPI
23DSI host controller. For all mandatory properties & nodes, please refer
24to the related documentation in [5].
25
26Mandatory properties specific to STM32 DSI:
27- #address-cells: Should be <1>.
28- #size-cells: Should be <0>.
29- compatible: "st,stm32-dsi".
30- clock-names:
31 - phy pll reference clock string name, must be "ref".
32- resets: see [5].
33- reset-names: see [5].
34
35Mandatory nodes specific to STM32 DSI:
36- ports: A node containing DSI input & output port nodes with endpoint
37 definitions as documented in [3] & [4].
38 - port@0: DSI input port node, connected to the ltdc rgb output port.
39 - port@1: DSI output port node, connected to a panel or a bridge input port.
40- panel or bridge node: A node containing the panel or bridge description as
41 documented in [6].
42 - port: panel or bridge port node, connected to the DSI output port (port@1).
43
44Note: You can find more documentation in the following references
45[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
46[2] Documentation/devicetree/bindings/reset/reset.txt
47[3] Documentation/devicetree/bindings/media/video-interfaces.txt
48[4] Documentation/devicetree/bindings/graph.txt
49[5] Documentation/devicetree/bindings/display/bridge/dw_mipi_dsi.txt
50[6] Documentation/devicetree/bindings/display/mipi-dsi-bus.txt
51
52Example 1: RGB panel
53/ {
54 ...
55 soc {
56 ...
57 ltdc: display-controller@40016800 {
58 compatible = "st,stm32-ltdc";
59 reg = <0x40016800 0x200>;
60 interrupts = <88>, <89>;
61 resets = <&rcc STM32F4_APB2_RESET(LTDC)>;
62 clocks = <&rcc 1 CLK_LCD>;
63 clock-names = "lcd";
64
65 port {
66 ltdc_out_rgb: endpoint {
67 };
68 };
69 };
70 };
71};
72
73Example 2: DSI panel
74
75/ {
76 ...
77 soc {
78 ...
79 ltdc: display-controller@40016800 {
80 compatible = "st,stm32-ltdc";
81 reg = <0x40016800 0x200>;
82 interrupts = <88>, <89>;
83 resets = <&rcc STM32F4_APB2_RESET(LTDC)>;
84 clocks = <&rcc 1 CLK_LCD>;
85 clock-names = "lcd";
86
87 port {
88 ltdc_out_dsi: endpoint {
89 remote-endpoint = <&dsi_in>;
90 };
91 };
92 };
93
94
95 dsi: dsi@40016c00 {
96 #address-cells = <1>;
97 #size-cells = <0>;
98 compatible = "st,stm32-dsi";
99 reg = <0x40016c00 0x800>;
100 clocks = <&rcc 1 CLK_F469_DSI>, <&clk_hse>;
101 clock-names = "pclk", "ref";
102 resets = <&rcc STM32F4_APB2_RESET(DSI)>;
103 reset-names = "apb";
104
105 ports {
106 #address-cells = <1>;
107 #size-cells = <0>;
108
109 port@0 {
110 reg = <0>;
111 dsi_in: endpoint {
112 remote-endpoint = <<dc_out_dsi>;
113 };
114 };
115
116 port@1 {
117 reg = <1>;
118 dsi_out: endpoint {
119 remote-endpoint = <&dsi_in_panel>;
120 };
121 };
122
123 };
124
125 panel-dsi@0 {
126 reg = <0>; /* dsi virtual channel (0..3) */
127 compatible = ...;
128 enable-gpios = ...;
129
130 port {
131 dsi_in_panel: endpoint {
132 remote-endpoint = <&dsi_out>;
133 };
134 };
135
136 };
137
138 };
139
140 };
141};