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1* Renesas Clock Pulse Generator / Module Standby and Software Reset
2
3On Renesas ARM SoCs (SH/R-Mobile, R-Car, RZ), the CPG (Clock Pulse Generator)
4and MSSR (Module Standby and Software Reset) blocks are intimately connected,
5and share the same register block.
6
7They provide the following functionalities:
8 - The CPG block generates various core clocks,
9 - The MSSR block provides two functions:
10 1. Module Standby, providing a Clock Domain to control the clock supply
11 to individual SoC devices,
12 2. Reset Control, to perform a software reset of individual SoC devices.
13
14Required Properties:
15 - compatible: Must be one of:
16 - "renesas,r8a7743-cpg-mssr" for the r8a7743 SoC (RZ/G1M)
17 - "renesas,r8a7745-cpg-mssr" for the r8a7745 SoC (RZ/G1E)
18 - "renesas,r8a7790-cpg-mssr" for the r8a7790 SoC (R-Car H2)
19 - "renesas,r8a7791-cpg-mssr" for the r8a7791 SoC (R-Car M2-W)
20 - "renesas,r8a7792-cpg-mssr" for the r8a7792 SoC (R-Car V2H)
21 - "renesas,r8a7793-cpg-mssr" for the r8a7793 SoC (R-Car M2-N)
22 - "renesas,r8a7794-cpg-mssr" for the r8a7794 SoC (R-Car E2)
23 - "renesas,r8a7795-cpg-mssr" for the r8a7795 SoC (R-Car H3)
24 - "renesas,r8a7796-cpg-mssr" for the r8a7796 SoC (R-Car M3-W)
25 - "renesas,r8a77965-cpg-mssr" for the r8a77965 SoC (R-Car M3-N)
26 - "renesas,r8a77970-cpg-mssr" for the r8a77970 SoC (R-Car V3M)
27 - "renesas,r8a77980-cpg-mssr" for the r8a77980 SoC (R-Car V3H)
28 - "renesas,r8a77995-cpg-mssr" for the r8a77995 SoC (R-Car D3)
29
30 - reg: Base address and length of the memory resource used by the CPG/MSSR
31 block
32
33 - clocks: References to external parent clocks, one entry for each entry in
34 clock-names
35 - clock-names: List of external parent clock names. Valid names are:
36 - "extal" (r8a7743, r8a7745, r8a7790, r8a7791, r8a7792, r8a7793, r8a7794,
37 r8a7795, r8a7796, r8a77965, r8a77970, r8a77980, r8a77995)
38 - "extalr" (r8a7795, r8a7796, r8a77965, r8a77970, r8a77980)
39 - "usb_extal" (r8a7743, r8a7745, r8a7790, r8a7791, r8a7793, r8a7794)
40
41 - #clock-cells: Must be 2
42 - For CPG core clocks, the two clock specifier cells must be "CPG_CORE"
43 and a core clock reference, as defined in
44 <dt-bindings/clock/*-cpg-mssr.h>.
45 - For module clocks, the two clock specifier cells must be "CPG_MOD" and
46 a module number, as defined in the datasheet.
47
48 - #power-domain-cells: Must be 0
49 - SoC devices that are part of the CPG/MSSR Clock Domain and can be
50 power-managed through Module Standby should refer to the CPG device
51 node in their "power-domains" property, as documented by the generic PM
52 Domain bindings in
53 Documentation/devicetree/bindings/power/power_domain.txt.
54
55 - #reset-cells: Must be 1
56 - The single reset specifier cell must be the module number, as defined
57 in the datasheet.
58
59
60Examples
61--------
62
63 - CPG device node:
64
65 cpg: clock-controller@e6150000 {
66 compatible = "renesas,r8a7795-cpg-mssr";
67 reg = <0 0xe6150000 0 0x1000>;
68 clocks = <&extal_clk>, <&extalr_clk>;
69 clock-names = "extal", "extalr";
70 #clock-cells = <2>;
71 #power-domain-cells = <0>;
72 #reset-cells = <1>;
73 };
74
75
76 - CPG/MSSR Clock Domain member device node:
77
78 scif2: serial@e6e88000 {
79 compatible = "renesas,scif-r8a7795", "renesas,scif";
80 reg = <0 0xe6e88000 0 64>;
81 interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>;
82 clocks = <&cpg CPG_MOD 310>;
83 clock-names = "fck";
84 dmas = <&dmac1 0x13>, <&dmac1 0x12>;
85 dma-names = "tx", "rx";
86 power-domains = <&cpg>;
87 resets = <&cpg 310>;
88 };