tjh.dev
Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Copyright (c) 2017, The Linux Foundation. All rights reserved.
4 */
5
6#include <linux/clk.h>
7#include <linux/clk-provider.h>
8#include <linux/delay.h>
9#include <linux/err.h>
10#include <linux/io.h>
11#include <linux/iopoll.h>
12#include <linux/kernel.h>
13#include <linux/module.h>
14#include <linux/of.h>
15#include <linux/of_device.h>
16#include <linux/of_address.h>
17#include <linux/phy/phy.h>
18#include <linux/platform_device.h>
19#include <linux/regulator/consumer.h>
20#include <linux/reset.h>
21#include <linux/slab.h>
22
23#include <dt-bindings/phy/phy.h>
24
25#include "phy-qcom-qmp.h"
26
27/* QPHY_SW_RESET bit */
28#define SW_RESET BIT(0)
29/* QPHY_POWER_DOWN_CONTROL */
30#define SW_PWRDN BIT(0)
31#define REFCLK_DRV_DSBL BIT(1)
32/* QPHY_START_CONTROL bits */
33#define SERDES_START BIT(0)
34#define PCS_START BIT(1)
35#define PLL_READY_GATE_EN BIT(3)
36/* QPHY_PCS_STATUS bit */
37#define PHYSTATUS BIT(6)
38/* QPHY_COM_PCS_READY_STATUS bit */
39#define PCS_READY BIT(0)
40
41/* QPHY_V3_DP_COM_RESET_OVRD_CTRL register bits */
42/* DP PHY soft reset */
43#define SW_DPPHY_RESET BIT(0)
44/* mux to select DP PHY reset control, 0:HW control, 1: software reset */
45#define SW_DPPHY_RESET_MUX BIT(1)
46/* USB3 PHY soft reset */
47#define SW_USB3PHY_RESET BIT(2)
48/* mux to select USB3 PHY reset control, 0:HW control, 1: software reset */
49#define SW_USB3PHY_RESET_MUX BIT(3)
50
51/* QPHY_V3_DP_COM_PHY_MODE_CTRL register bits */
52#define USB3_MODE BIT(0) /* enables USB3 mode */
53#define DP_MODE BIT(1) /* enables DP mode */
54
55/* QPHY_PCS_AUTONOMOUS_MODE_CTRL register bits */
56#define ARCVR_DTCT_EN BIT(0)
57#define ALFPS_DTCT_EN BIT(1)
58#define ARCVR_DTCT_EVENT_SEL BIT(4)
59
60/* QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR register bits */
61#define IRQ_CLEAR BIT(0)
62
63/* QPHY_PCS_LFPS_RXTERM_IRQ_STATUS register bits */
64#define RCVR_DETECT BIT(0)
65
66/* QPHY_V3_PCS_MISC_CLAMP_ENABLE register bits */
67#define CLAMP_EN BIT(0) /* enables i/o clamp_n */
68
69#define PHY_INIT_COMPLETE_TIMEOUT 1000
70#define POWER_DOWN_DELAY_US_MIN 10
71#define POWER_DOWN_DELAY_US_MAX 11
72
73#define MAX_PROP_NAME 32
74
75struct qmp_phy_init_tbl {
76 unsigned int offset;
77 unsigned int val;
78 /*
79 * register part of layout ?
80 * if yes, then offset gives index in the reg-layout
81 */
82 int in_layout;
83};
84
85#define QMP_PHY_INIT_CFG(o, v) \
86 { \
87 .offset = o, \
88 .val = v, \
89 }
90
91#define QMP_PHY_INIT_CFG_L(o, v) \
92 { \
93 .offset = o, \
94 .val = v, \
95 .in_layout = 1, \
96 }
97
98/* set of registers with offsets different per-PHY */
99enum qphy_reg_layout {
100 /* Common block control registers */
101 QPHY_COM_SW_RESET,
102 QPHY_COM_POWER_DOWN_CONTROL,
103 QPHY_COM_START_CONTROL,
104 QPHY_COM_PCS_READY_STATUS,
105 /* PCS registers */
106 QPHY_PLL_LOCK_CHK_DLY_TIME,
107 QPHY_FLL_CNTRL1,
108 QPHY_FLL_CNTRL2,
109 QPHY_FLL_CNT_VAL_L,
110 QPHY_FLL_CNT_VAL_H_TOL,
111 QPHY_FLL_MAN_CODE,
112 QPHY_SW_RESET,
113 QPHY_START_CTRL,
114 QPHY_PCS_READY_STATUS,
115 QPHY_PCS_AUTONOMOUS_MODE_CTRL,
116 QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR,
117 QPHY_PCS_LFPS_RXTERM_IRQ_STATUS,
118};
119
120static const unsigned int pciephy_regs_layout[] = {
121 [QPHY_COM_SW_RESET] = 0x400,
122 [QPHY_COM_POWER_DOWN_CONTROL] = 0x404,
123 [QPHY_COM_START_CONTROL] = 0x408,
124 [QPHY_COM_PCS_READY_STATUS] = 0x448,
125 [QPHY_PLL_LOCK_CHK_DLY_TIME] = 0xa8,
126 [QPHY_FLL_CNTRL1] = 0xc4,
127 [QPHY_FLL_CNTRL2] = 0xc8,
128 [QPHY_FLL_CNT_VAL_L] = 0xcc,
129 [QPHY_FLL_CNT_VAL_H_TOL] = 0xd0,
130 [QPHY_FLL_MAN_CODE] = 0xd4,
131 [QPHY_SW_RESET] = 0x00,
132 [QPHY_START_CTRL] = 0x08,
133 [QPHY_PCS_READY_STATUS] = 0x174,
134};
135
136static const unsigned int usb3phy_regs_layout[] = {
137 [QPHY_FLL_CNTRL1] = 0xc0,
138 [QPHY_FLL_CNTRL2] = 0xc4,
139 [QPHY_FLL_CNT_VAL_L] = 0xc8,
140 [QPHY_FLL_CNT_VAL_H_TOL] = 0xcc,
141 [QPHY_FLL_MAN_CODE] = 0xd0,
142 [QPHY_SW_RESET] = 0x00,
143 [QPHY_START_CTRL] = 0x08,
144 [QPHY_PCS_READY_STATUS] = 0x17c,
145 [QPHY_PCS_AUTONOMOUS_MODE_CTRL] = 0x0d4,
146 [QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR] = 0x0d8,
147 [QPHY_PCS_LFPS_RXTERM_IRQ_STATUS] = 0x178,
148};
149
150static const unsigned int qmp_v3_usb3phy_regs_layout[] = {
151 [QPHY_SW_RESET] = 0x00,
152 [QPHY_START_CTRL] = 0x08,
153 [QPHY_PCS_READY_STATUS] = 0x174,
154 [QPHY_PCS_AUTONOMOUS_MODE_CTRL] = 0x0d8,
155 [QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR] = 0x0dc,
156 [QPHY_PCS_LFPS_RXTERM_IRQ_STATUS] = 0x170,
157};
158
159static const struct qmp_phy_init_tbl msm8996_pcie_serdes_tbl[] = {
160 QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CLKBUFLR_EN, 0x1c),
161 QMP_PHY_INIT_CFG(QSERDES_COM_CLK_ENABLE1, 0x10),
162 QMP_PHY_INIT_CFG(QSERDES_COM_CLK_SELECT, 0x33),
163 QMP_PHY_INIT_CFG(QSERDES_COM_CMN_CONFIG, 0x06),
164 QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_EN, 0x42),
165 QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_MAP, 0x00),
166 QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_TIMER1, 0xff),
167 QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_TIMER2, 0x1f),
168 QMP_PHY_INIT_CFG(QSERDES_COM_HSCLK_SEL, 0x01),
169 QMP_PHY_INIT_CFG(QSERDES_COM_SVS_MODE_CLK_SEL, 0x01),
170 QMP_PHY_INIT_CFG(QSERDES_COM_CORE_CLK_EN, 0x00),
171 QMP_PHY_INIT_CFG(QSERDES_COM_CORECLK_DIV, 0x0a),
172 QMP_PHY_INIT_CFG(QSERDES_COM_BG_TIMER, 0x09),
173 QMP_PHY_INIT_CFG(QSERDES_COM_DEC_START_MODE0, 0x82),
174 QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START3_MODE0, 0x03),
175 QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START2_MODE0, 0x55),
176 QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START1_MODE0, 0x55),
177 QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE0, 0x00),
178 QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP2_MODE0, 0x1a),
179 QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP1_MODE0, 0x0a),
180 QMP_PHY_INIT_CFG(QSERDES_COM_CLK_SELECT, 0x33),
181 QMP_PHY_INIT_CFG(QSERDES_COM_SYS_CLK_CTRL, 0x02),
182 QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_BUF_ENABLE, 0x1f),
183 QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_EN_SEL, 0x04),
184 QMP_PHY_INIT_CFG(QSERDES_COM_CP_CTRL_MODE0, 0x0b),
185 QMP_PHY_INIT_CFG(QSERDES_COM_PLL_RCTRL_MODE0, 0x16),
186 QMP_PHY_INIT_CFG(QSERDES_COM_PLL_CCTRL_MODE0, 0x28),
187 QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN1_MODE0, 0x00),
188 QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN0_MODE0, 0x80),
189 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_EN_CENTER, 0x01),
190 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER1, 0x31),
191 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER2, 0x01),
192 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER1, 0x02),
193 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER2, 0x00),
194 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE1, 0x2f),
195 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE2, 0x19),
196 QMP_PHY_INIT_CFG(QSERDES_COM_RESCODE_DIV_NUM, 0x15),
197 QMP_PHY_INIT_CFG(QSERDES_COM_BG_TRIM, 0x0f),
198 QMP_PHY_INIT_CFG(QSERDES_COM_PLL_IVCO, 0x0f),
199 QMP_PHY_INIT_CFG(QSERDES_COM_CLK_EP_DIV, 0x19),
200 QMP_PHY_INIT_CFG(QSERDES_COM_CLK_ENABLE1, 0x10),
201 QMP_PHY_INIT_CFG(QSERDES_COM_HSCLK_SEL, 0x00),
202 QMP_PHY_INIT_CFG(QSERDES_COM_RESCODE_DIV_NUM, 0x40),
203};
204
205static const struct qmp_phy_init_tbl msm8996_pcie_tx_tbl[] = {
206 QMP_PHY_INIT_CFG(QSERDES_TX_HIGHZ_TRANSCEIVEREN_BIAS_DRVR_EN, 0x45),
207 QMP_PHY_INIT_CFG(QSERDES_TX_LANE_MODE, 0x06),
208};
209
210static const struct qmp_phy_init_tbl msm8996_pcie_rx_tbl[] = {
211 QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_ENABLES, 0x1c),
212 QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL2, 0x01),
213 QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL3, 0x00),
214 QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL4, 0xdb),
215 QMP_PHY_INIT_CFG(QSERDES_RX_RX_BAND, 0x18),
216 QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SO_GAIN, 0x04),
217 QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SO_GAIN_HALF, 0x04),
218 QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x4b),
219 QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_DEGLITCH_CNTRL, 0x14),
220 QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_LVL, 0x19),
221};
222
223static const struct qmp_phy_init_tbl msm8996_pcie_pcs_tbl[] = {
224 QMP_PHY_INIT_CFG(QPHY_RX_IDLE_DTCT_CNTRL, 0x4c),
225 QMP_PHY_INIT_CFG(QPHY_PWRUP_RESET_DLY_TIME_AUXCLK, 0x00),
226 QMP_PHY_INIT_CFG(QPHY_LP_WAKEUP_DLY_TIME_AUXCLK, 0x01),
227
228 QMP_PHY_INIT_CFG_L(QPHY_PLL_LOCK_CHK_DLY_TIME, 0x05),
229
230 QMP_PHY_INIT_CFG(QPHY_ENDPOINT_REFCLK_DRIVE, 0x05),
231 QMP_PHY_INIT_CFG(QPHY_POWER_DOWN_CONTROL, 0x02),
232 QMP_PHY_INIT_CFG(QPHY_POWER_STATE_CONFIG4, 0x00),
233 QMP_PHY_INIT_CFG(QPHY_POWER_STATE_CONFIG1, 0xa3),
234 QMP_PHY_INIT_CFG(QPHY_TXDEEMPH_M3P5DB_V0, 0x0e),
235};
236
237static const struct qmp_phy_init_tbl msm8996_usb3_serdes_tbl[] = {
238 QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_EN_SEL, 0x14),
239 QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CLKBUFLR_EN, 0x08),
240 QMP_PHY_INIT_CFG(QSERDES_COM_CLK_SELECT, 0x30),
241 QMP_PHY_INIT_CFG(QSERDES_COM_CMN_CONFIG, 0x06),
242 QMP_PHY_INIT_CFG(QSERDES_COM_SVS_MODE_CLK_SEL, 0x01),
243 QMP_PHY_INIT_CFG(QSERDES_COM_HSCLK_SEL, 0x00),
244 QMP_PHY_INIT_CFG(QSERDES_COM_BG_TRIM, 0x0f),
245 QMP_PHY_INIT_CFG(QSERDES_COM_PLL_IVCO, 0x0f),
246 QMP_PHY_INIT_CFG(QSERDES_COM_SYS_CLK_CTRL, 0x04),
247 /* PLL and Loop filter settings */
248 QMP_PHY_INIT_CFG(QSERDES_COM_DEC_START_MODE0, 0x82),
249 QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START1_MODE0, 0x55),
250 QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START2_MODE0, 0x55),
251 QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START3_MODE0, 0x03),
252 QMP_PHY_INIT_CFG(QSERDES_COM_CP_CTRL_MODE0, 0x0b),
253 QMP_PHY_INIT_CFG(QSERDES_COM_PLL_RCTRL_MODE0, 0x16),
254 QMP_PHY_INIT_CFG(QSERDES_COM_PLL_CCTRL_MODE0, 0x28),
255 QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN0_MODE0, 0x80),
256 QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_CTRL, 0x00),
257 QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP1_MODE0, 0x15),
258 QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP2_MODE0, 0x34),
259 QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE0, 0x00),
260 QMP_PHY_INIT_CFG(QSERDES_COM_CORE_CLK_EN, 0x00),
261 QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_CFG, 0x00),
262 QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_MAP, 0x00),
263 QMP_PHY_INIT_CFG(QSERDES_COM_BG_TIMER, 0x0a),
264 /* SSC settings */
265 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_EN_CENTER, 0x01),
266 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER1, 0x31),
267 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER2, 0x01),
268 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER1, 0x00),
269 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER2, 0x00),
270 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE1, 0xde),
271 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE2, 0x07),
272};
273
274static const struct qmp_phy_init_tbl msm8996_usb3_tx_tbl[] = {
275 QMP_PHY_INIT_CFG(QSERDES_TX_HIGHZ_TRANSCEIVEREN_BIAS_DRVR_EN, 0x45),
276 QMP_PHY_INIT_CFG(QSERDES_TX_RCV_DETECT_LVL_2, 0x12),
277 QMP_PHY_INIT_CFG(QSERDES_TX_LANE_MODE, 0x06),
278};
279
280static const struct qmp_phy_init_tbl msm8996_usb3_rx_tbl[] = {
281 QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_FASTLOCK_FO_GAIN, 0x0b),
282 QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SO_GAIN, 0x04),
283 QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL2, 0x02),
284 QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4c),
285 QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL4, 0xbb),
286 QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x77),
287 QMP_PHY_INIT_CFG(QSERDES_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
288 QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_CNTRL, 0x03),
289 QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_LVL, 0x18),
290 QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_DEGLITCH_CNTRL, 0x16),
291};
292
293static const struct qmp_phy_init_tbl msm8996_usb3_pcs_tbl[] = {
294 /* FLL settings */
295 QMP_PHY_INIT_CFG_L(QPHY_FLL_CNTRL2, 0x03),
296 QMP_PHY_INIT_CFG_L(QPHY_FLL_CNTRL1, 0x02),
297 QMP_PHY_INIT_CFG_L(QPHY_FLL_CNT_VAL_L, 0x09),
298 QMP_PHY_INIT_CFG_L(QPHY_FLL_CNT_VAL_H_TOL, 0x42),
299 QMP_PHY_INIT_CFG_L(QPHY_FLL_MAN_CODE, 0x85),
300
301 /* Lock Det settings */
302 QMP_PHY_INIT_CFG(QPHY_LOCK_DETECT_CONFIG1, 0xd1),
303 QMP_PHY_INIT_CFG(QPHY_LOCK_DETECT_CONFIG2, 0x1f),
304 QMP_PHY_INIT_CFG(QPHY_LOCK_DETECT_CONFIG3, 0x47),
305 QMP_PHY_INIT_CFG(QPHY_POWER_STATE_CONFIG2, 0x08),
306};
307
308static const struct qmp_phy_init_tbl ipq8074_pcie_serdes_tbl[] = {
309 QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CLKBUFLR_EN, 0x18),
310 QMP_PHY_INIT_CFG(QSERDES_COM_CLK_ENABLE1, 0x10),
311 QMP_PHY_INIT_CFG(QSERDES_COM_BG_TRIM, 0xf),
312 QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_EN, 0x1),
313 QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_MAP, 0x0),
314 QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_TIMER1, 0x1f),
315 QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_TIMER2, 0x3f),
316 QMP_PHY_INIT_CFG(QSERDES_COM_CMN_CONFIG, 0x6),
317 QMP_PHY_INIT_CFG(QSERDES_COM_PLL_IVCO, 0xf),
318 QMP_PHY_INIT_CFG(QSERDES_COM_HSCLK_SEL, 0x0),
319 QMP_PHY_INIT_CFG(QSERDES_COM_SVS_MODE_CLK_SEL, 0x1),
320 QMP_PHY_INIT_CFG(QSERDES_COM_CORE_CLK_EN, 0x20),
321 QMP_PHY_INIT_CFG(QSERDES_COM_CORECLK_DIV, 0xa),
322 QMP_PHY_INIT_CFG(QSERDES_COM_RESETSM_CNTRL, 0x20),
323 QMP_PHY_INIT_CFG(QSERDES_COM_BG_TIMER, 0xa),
324 QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_EN_SEL, 0xa),
325 QMP_PHY_INIT_CFG(QSERDES_COM_DEC_START_MODE0, 0x82),
326 QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START3_MODE0, 0x3),
327 QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START2_MODE0, 0x55),
328 QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START1_MODE0, 0x55),
329 QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE0, 0x0),
330 QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP2_MODE0, 0xD),
331 QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP1_MODE0, 0xD04),
332 QMP_PHY_INIT_CFG(QSERDES_COM_CLK_SELECT, 0x33),
333 QMP_PHY_INIT_CFG(QSERDES_COM_SYS_CLK_CTRL, 0x2),
334 QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_BUF_ENABLE, 0x1f),
335 QMP_PHY_INIT_CFG(QSERDES_COM_CP_CTRL_MODE0, 0xb),
336 QMP_PHY_INIT_CFG(QSERDES_COM_PLL_RCTRL_MODE0, 0x16),
337 QMP_PHY_INIT_CFG(QSERDES_COM_PLL_CCTRL_MODE0, 0x28),
338 QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN1_MODE0, 0x0),
339 QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN0_MODE0, 0x80),
340 QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CTRL_BY_PSM, 0x1),
341 QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_CTRL, 0xa),
342 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_EN_CENTER, 0x1),
343 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER1, 0x31),
344 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER2, 0x1),
345 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER1, 0x2),
346 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER2, 0x0),
347 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE1, 0x2f),
348 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE2, 0x19),
349 QMP_PHY_INIT_CFG(QSERDES_COM_CLK_EP_DIV, 0x19),
350 QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_CNTRL, 0x7),
351};
352
353static const struct qmp_phy_init_tbl ipq8074_pcie_tx_tbl[] = {
354 QMP_PHY_INIT_CFG(QSERDES_TX_HIGHZ_TRANSCEIVEREN_BIAS_DRVR_EN, 0x45),
355 QMP_PHY_INIT_CFG(QSERDES_TX_LANE_MODE, 0x6),
356 QMP_PHY_INIT_CFG(QSERDES_TX_RES_CODE_LANE_OFFSET, 0x2),
357 QMP_PHY_INIT_CFG(QSERDES_TX_RCV_DETECT_LVL_2, 0x12),
358};
359
360static const struct qmp_phy_init_tbl ipq8074_pcie_rx_tbl[] = {
361 QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_ENABLES, 0x1c),
362 QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_DEGLITCH_CNTRL, 0x14),
363 QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL2, 0x1),
364 QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL3, 0x0),
365 QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL4, 0xdb),
366 QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x4b),
367 QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SO_GAIN, 0x4),
368 QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SO_GAIN_HALF, 0x4),
369};
370
371static const struct qmp_phy_init_tbl ipq8074_pcie_pcs_tbl[] = {
372 QMP_PHY_INIT_CFG(QPHY_ENDPOINT_REFCLK_DRIVE, 0x4),
373 QMP_PHY_INIT_CFG(QPHY_OSC_DTCT_ACTIONS, 0x0),
374 QMP_PHY_INIT_CFG(QPHY_PWRUP_RESET_DLY_TIME_AUXCLK, 0x40),
375 QMP_PHY_INIT_CFG(QPHY_L1SS_WAKEUP_DLY_TIME_AUXCLK_MSB, 0x0),
376 QMP_PHY_INIT_CFG(QPHY_L1SS_WAKEUP_DLY_TIME_AUXCLK_LSB, 0x40),
377 QMP_PHY_INIT_CFG(QPHY_PLL_LOCK_CHK_DLY_TIME_AUXCLK_LSB, 0x0),
378 QMP_PHY_INIT_CFG(QPHY_LP_WAKEUP_DLY_TIME_AUXCLK, 0x40),
379 QMP_PHY_INIT_CFG_L(QPHY_PLL_LOCK_CHK_DLY_TIME, 0x73),
380 QMP_PHY_INIT_CFG(QPHY_RX_SIGDET_LVL, 0x99),
381 QMP_PHY_INIT_CFG(QPHY_TXDEEMPH_M6DB_V0, 0x15),
382 QMP_PHY_INIT_CFG(QPHY_TXDEEMPH_M3P5DB_V0, 0xe),
383 QMP_PHY_INIT_CFG_L(QPHY_SW_RESET, 0x0),
384 QMP_PHY_INIT_CFG_L(QPHY_START_CTRL, 0x3),
385};
386
387static const struct qmp_phy_init_tbl qmp_v3_usb3_serdes_tbl[] = {
388 QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_IVCO, 0x07),
389 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_EN_SEL, 0x14),
390 QMP_PHY_INIT_CFG(QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN, 0x08),
391 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x30),
392 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYS_CLK_CTRL, 0x02),
393 QMP_PHY_INIT_CFG(QSERDES_V3_COM_RESETSM_CNTRL2, 0x08),
394 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_CONFIG, 0x16),
395 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SVS_MODE_CLK_SEL, 0x01),
396 QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x80),
397 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x82),
398 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START1_MODE0, 0xab),
399 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0xea),
400 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x02),
401 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CP_CTRL_MODE0, 0x06),
402 QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_RCTRL_MODE0, 0x16),
403 QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_CCTRL_MODE0, 0x36),
404 QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE0, 0x00),
405 QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE0, 0x3f),
406 QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE2_MODE0, 0x01),
407 QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE1_MODE0, 0xc9),
408 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORECLK_DIV_MODE0, 0x0a),
409 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP3_MODE0, 0x00),
410 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x34),
411 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x15),
412 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x04),
413 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORE_CLK_EN, 0x00),
414 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_CFG, 0x00),
415 QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_MAP, 0x00),
416 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_BUF_ENABLE, 0x0a),
417 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_EN_CENTER, 0x01),
418 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER1, 0x31),
419 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER2, 0x01),
420 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER1, 0x00),
421 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER2, 0x00),
422 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE1, 0x85),
423 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE2, 0x07),
424};
425
426static const struct qmp_phy_init_tbl qmp_v3_usb3_tx_tbl[] = {
427 QMP_PHY_INIT_CFG(QSERDES_V3_TX_HIGHZ_DRVR_EN, 0x10),
428 QMP_PHY_INIT_CFG(QSERDES_V3_TX_RCV_DETECT_LVL_2, 0x12),
429 QMP_PHY_INIT_CFG(QSERDES_V3_TX_LANE_MODE_1, 0x16),
430 QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_RX, 0x09),
431 QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_TX, 0x06),
432};
433
434static const struct qmp_phy_init_tbl qmp_v3_usb3_rx_tbl[] = {
435 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_FO_GAIN, 0x0b),
436 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f),
437 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4e),
438 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL4, 0x18),
439 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x77),
440 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
441 QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_CNTRL, 0x03),
442 QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_DEGLITCH_CNTRL, 0x16),
443 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x75),
444};
445
446static const struct qmp_phy_init_tbl qmp_v3_usb3_pcs_tbl[] = {
447 /* FLL settings */
448 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL2, 0x83),
449 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_L, 0x09),
450 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_H_TOL, 0xa2),
451 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_MAN_CODE, 0x40),
452 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL1, 0x02),
453
454 /* Lock Det settings */
455 QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG1, 0xd1),
456 QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG2, 0x1f),
457 QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG3, 0x47),
458 QMP_PHY_INIT_CFG(QPHY_V3_PCS_POWER_STATE_CONFIG2, 0x1b),
459
460 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_LVL, 0xba),
461 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V0, 0x9f),
462 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V1, 0x9f),
463 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V2, 0xb7),
464 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V3, 0x4e),
465 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V4, 0x65),
466 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_LS, 0x6b),
467 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V0, 0x15),
468 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V0, 0x0d),
469 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V1, 0x15),
470 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V1, 0x0d),
471 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V2, 0x15),
472 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V2, 0x0d),
473 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V3, 0x15),
474 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V3, 0x1d),
475 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V4, 0x15),
476 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V4, 0x0d),
477 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_LS, 0x15),
478 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_LS, 0x0d),
479
480 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RATE_SLEW_CNTRL, 0x02),
481 QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x04),
482 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TSYNC_RSYNC_TIME, 0x44),
483 QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x04),
484 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7),
485 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03),
486 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_L, 0x40),
487 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_H, 0x00),
488 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_WAIT_TIME, 0x75),
489 QMP_PHY_INIT_CFG(QPHY_V3_PCS_LFPS_TX_ECSTART_EQTLOCK, 0x86),
490 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_RUN_TIME, 0x13),
491};
492
493/* struct qmp_phy_cfg - per-PHY initialization config */
494struct qmp_phy_cfg {
495 /* phy-type - PCIE/UFS/USB */
496 unsigned int type;
497 /* number of lanes provided by phy */
498 int nlanes;
499
500 /* Init sequence for PHY blocks - serdes, tx, rx, pcs */
501 const struct qmp_phy_init_tbl *serdes_tbl;
502 int serdes_tbl_num;
503 const struct qmp_phy_init_tbl *tx_tbl;
504 int tx_tbl_num;
505 const struct qmp_phy_init_tbl *rx_tbl;
506 int rx_tbl_num;
507 const struct qmp_phy_init_tbl *pcs_tbl;
508 int pcs_tbl_num;
509
510 /* clock ids to be requested */
511 const char * const *clk_list;
512 int num_clks;
513 /* resets to be requested */
514 const char * const *reset_list;
515 int num_resets;
516 /* regulators to be requested */
517 const char * const *vreg_list;
518 int num_vregs;
519
520 /* array of registers with different offsets */
521 const unsigned int *regs;
522
523 unsigned int start_ctrl;
524 unsigned int pwrdn_ctrl;
525 unsigned int mask_pcs_ready;
526 unsigned int mask_com_pcs_ready;
527
528 /* true, if PHY has a separate PHY_COM control block */
529 bool has_phy_com_ctrl;
530 /* true, if PHY has a reset for individual lanes */
531 bool has_lane_rst;
532 /* true, if PHY needs delay after POWER_DOWN */
533 bool has_pwrdn_delay;
534 /* power_down delay in usec */
535 int pwrdn_delay_min;
536 int pwrdn_delay_max;
537
538 /* true, if PHY has a separate DP_COM control block */
539 bool has_phy_dp_com_ctrl;
540 /* Register offset of secondary tx/rx lanes for USB DP combo PHY */
541 unsigned int tx_b_lane_offset;
542 unsigned int rx_b_lane_offset;
543};
544
545/**
546 * struct qmp_phy - per-lane phy descriptor
547 *
548 * @phy: generic phy
549 * @tx: iomapped memory space for lane's tx
550 * @rx: iomapped memory space for lane's rx
551 * @pcs: iomapped memory space for lane's pcs
552 * @pcs_misc: iomapped memory space for lane's pcs_misc
553 * @pipe_clk: pipe lock
554 * @index: lane index
555 * @qmp: QMP phy to which this lane belongs
556 * @lane_rst: lane's reset controller
557 */
558struct qmp_phy {
559 struct phy *phy;
560 void __iomem *tx;
561 void __iomem *rx;
562 void __iomem *pcs;
563 void __iomem *pcs_misc;
564 struct clk *pipe_clk;
565 unsigned int index;
566 struct qcom_qmp *qmp;
567 struct reset_control *lane_rst;
568};
569
570/**
571 * struct qcom_qmp - structure holding QMP phy block attributes
572 *
573 * @dev: device
574 * @serdes: iomapped memory space for phy's serdes
575 * @dp_com: iomapped memory space for phy's dp_com control block
576 *
577 * @clks: array of clocks required by phy
578 * @resets: array of resets required by phy
579 * @vregs: regulator supplies bulk data
580 *
581 * @cfg: phy specific configuration
582 * @phys: array of per-lane phy descriptors
583 * @phy_mutex: mutex lock for PHY common block initialization
584 * @init_count: phy common block initialization count
585 * @phy_initialized: indicate if PHY has been initialized
586 * @mode: current PHY mode
587 */
588struct qcom_qmp {
589 struct device *dev;
590 void __iomem *serdes;
591 void __iomem *dp_com;
592
593 struct clk_bulk_data *clks;
594 struct reset_control **resets;
595 struct regulator_bulk_data *vregs;
596
597 const struct qmp_phy_cfg *cfg;
598 struct qmp_phy **phys;
599
600 struct mutex phy_mutex;
601 int init_count;
602 bool phy_initialized;
603 enum phy_mode mode;
604};
605
606static inline void qphy_setbits(void __iomem *base, u32 offset, u32 val)
607{
608 u32 reg;
609
610 reg = readl(base + offset);
611 reg |= val;
612 writel(reg, base + offset);
613
614 /* ensure that above write is through */
615 readl(base + offset);
616}
617
618static inline void qphy_clrbits(void __iomem *base, u32 offset, u32 val)
619{
620 u32 reg;
621
622 reg = readl(base + offset);
623 reg &= ~val;
624 writel(reg, base + offset);
625
626 /* ensure that above write is through */
627 readl(base + offset);
628}
629
630/* list of clocks required by phy */
631static const char * const msm8996_phy_clk_l[] = {
632 "aux", "cfg_ahb", "ref",
633};
634
635static const char * const qmp_v3_phy_clk_l[] = {
636 "aux", "cfg_ahb", "ref", "com_aux",
637};
638
639/* list of resets */
640static const char * const msm8996_pciephy_reset_l[] = {
641 "phy", "common", "cfg",
642};
643
644static const char * const msm8996_usb3phy_reset_l[] = {
645 "phy", "common",
646};
647
648/* list of regulators */
649static const char * const msm8996_phy_vreg_l[] = {
650 "vdda-phy", "vdda-pll",
651};
652
653static const struct qmp_phy_cfg msm8996_pciephy_cfg = {
654 .type = PHY_TYPE_PCIE,
655 .nlanes = 3,
656
657 .serdes_tbl = msm8996_pcie_serdes_tbl,
658 .serdes_tbl_num = ARRAY_SIZE(msm8996_pcie_serdes_tbl),
659 .tx_tbl = msm8996_pcie_tx_tbl,
660 .tx_tbl_num = ARRAY_SIZE(msm8996_pcie_tx_tbl),
661 .rx_tbl = msm8996_pcie_rx_tbl,
662 .rx_tbl_num = ARRAY_SIZE(msm8996_pcie_rx_tbl),
663 .pcs_tbl = msm8996_pcie_pcs_tbl,
664 .pcs_tbl_num = ARRAY_SIZE(msm8996_pcie_pcs_tbl),
665 .clk_list = msm8996_phy_clk_l,
666 .num_clks = ARRAY_SIZE(msm8996_phy_clk_l),
667 .reset_list = msm8996_pciephy_reset_l,
668 .num_resets = ARRAY_SIZE(msm8996_pciephy_reset_l),
669 .vreg_list = msm8996_phy_vreg_l,
670 .num_vregs = ARRAY_SIZE(msm8996_phy_vreg_l),
671 .regs = pciephy_regs_layout,
672
673 .start_ctrl = PCS_START | PLL_READY_GATE_EN,
674 .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL,
675 .mask_com_pcs_ready = PCS_READY,
676
677 .has_phy_com_ctrl = true,
678 .has_lane_rst = true,
679 .has_pwrdn_delay = true,
680 .pwrdn_delay_min = POWER_DOWN_DELAY_US_MIN,
681 .pwrdn_delay_max = POWER_DOWN_DELAY_US_MAX,
682};
683
684static const struct qmp_phy_cfg msm8996_usb3phy_cfg = {
685 .type = PHY_TYPE_USB3,
686 .nlanes = 1,
687
688 .serdes_tbl = msm8996_usb3_serdes_tbl,
689 .serdes_tbl_num = ARRAY_SIZE(msm8996_usb3_serdes_tbl),
690 .tx_tbl = msm8996_usb3_tx_tbl,
691 .tx_tbl_num = ARRAY_SIZE(msm8996_usb3_tx_tbl),
692 .rx_tbl = msm8996_usb3_rx_tbl,
693 .rx_tbl_num = ARRAY_SIZE(msm8996_usb3_rx_tbl),
694 .pcs_tbl = msm8996_usb3_pcs_tbl,
695 .pcs_tbl_num = ARRAY_SIZE(msm8996_usb3_pcs_tbl),
696 .clk_list = msm8996_phy_clk_l,
697 .num_clks = ARRAY_SIZE(msm8996_phy_clk_l),
698 .reset_list = msm8996_usb3phy_reset_l,
699 .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l),
700 .vreg_list = msm8996_phy_vreg_l,
701 .num_vregs = ARRAY_SIZE(msm8996_phy_vreg_l),
702 .regs = usb3phy_regs_layout,
703
704 .start_ctrl = SERDES_START | PCS_START,
705 .pwrdn_ctrl = SW_PWRDN,
706 .mask_pcs_ready = PHYSTATUS,
707};
708
709/* list of resets */
710static const char * const ipq8074_pciephy_reset_l[] = {
711 "phy", "common",
712};
713
714static const struct qmp_phy_cfg ipq8074_pciephy_cfg = {
715 .type = PHY_TYPE_PCIE,
716 .nlanes = 1,
717
718 .serdes_tbl = ipq8074_pcie_serdes_tbl,
719 .serdes_tbl_num = ARRAY_SIZE(ipq8074_pcie_serdes_tbl),
720 .tx_tbl = ipq8074_pcie_tx_tbl,
721 .tx_tbl_num = ARRAY_SIZE(ipq8074_pcie_tx_tbl),
722 .rx_tbl = ipq8074_pcie_rx_tbl,
723 .rx_tbl_num = ARRAY_SIZE(ipq8074_pcie_rx_tbl),
724 .pcs_tbl = ipq8074_pcie_pcs_tbl,
725 .pcs_tbl_num = ARRAY_SIZE(ipq8074_pcie_pcs_tbl),
726 .clk_list = NULL,
727 .num_clks = 0,
728 .reset_list = ipq8074_pciephy_reset_l,
729 .num_resets = ARRAY_SIZE(ipq8074_pciephy_reset_l),
730 .vreg_list = NULL,
731 .num_vregs = 0,
732 .regs = pciephy_regs_layout,
733
734 .start_ctrl = SERDES_START | PCS_START,
735 .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL,
736 .mask_pcs_ready = PHYSTATUS,
737
738 .has_phy_com_ctrl = false,
739 .has_lane_rst = false,
740 .has_pwrdn_delay = true,
741 .pwrdn_delay_min = 995, /* us */
742 .pwrdn_delay_max = 1005, /* us */
743};
744
745static const struct qmp_phy_cfg qmp_v3_usb3phy_cfg = {
746 .type = PHY_TYPE_USB3,
747 .nlanes = 1,
748
749 .serdes_tbl = qmp_v3_usb3_serdes_tbl,
750 .serdes_tbl_num = ARRAY_SIZE(qmp_v3_usb3_serdes_tbl),
751 .tx_tbl = qmp_v3_usb3_tx_tbl,
752 .tx_tbl_num = ARRAY_SIZE(qmp_v3_usb3_tx_tbl),
753 .rx_tbl = qmp_v3_usb3_rx_tbl,
754 .rx_tbl_num = ARRAY_SIZE(qmp_v3_usb3_rx_tbl),
755 .pcs_tbl = qmp_v3_usb3_pcs_tbl,
756 .pcs_tbl_num = ARRAY_SIZE(qmp_v3_usb3_pcs_tbl),
757 .clk_list = qmp_v3_phy_clk_l,
758 .num_clks = ARRAY_SIZE(qmp_v3_phy_clk_l),
759 .reset_list = msm8996_usb3phy_reset_l,
760 .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l),
761 .vreg_list = msm8996_phy_vreg_l,
762 .num_vregs = ARRAY_SIZE(msm8996_phy_vreg_l),
763 .regs = qmp_v3_usb3phy_regs_layout,
764
765 .start_ctrl = SERDES_START | PCS_START,
766 .pwrdn_ctrl = SW_PWRDN,
767 .mask_pcs_ready = PHYSTATUS,
768
769 .pwrdn_delay_min = POWER_DOWN_DELAY_US_MIN,
770 .pwrdn_delay_max = POWER_DOWN_DELAY_US_MAX,
771
772 .has_phy_dp_com_ctrl = true,
773 .tx_b_lane_offset = 0x400,
774 .rx_b_lane_offset = 0x400,
775};
776
777static void qcom_qmp_phy_configure(void __iomem *base,
778 const unsigned int *regs,
779 const struct qmp_phy_init_tbl tbl[],
780 int num)
781{
782 int i;
783 const struct qmp_phy_init_tbl *t = tbl;
784
785 if (!t)
786 return;
787
788 for (i = 0; i < num; i++, t++) {
789 if (t->in_layout)
790 writel(t->val, base + regs[t->offset]);
791 else
792 writel(t->val, base + t->offset);
793 }
794}
795
796static int qcom_qmp_phy_poweron(struct phy *phy)
797{
798 struct qmp_phy *qphy = phy_get_drvdata(phy);
799 struct qcom_qmp *qmp = qphy->qmp;
800 int ret;
801
802 ret = clk_prepare_enable(qphy->pipe_clk);
803 if (ret)
804 dev_err(qmp->dev, "pipe_clk enable failed, err=%d\n", ret);
805
806 return ret;
807}
808
809static int qcom_qmp_phy_com_init(struct qcom_qmp *qmp)
810{
811 const struct qmp_phy_cfg *cfg = qmp->cfg;
812 void __iomem *serdes = qmp->serdes;
813 void __iomem *dp_com = qmp->dp_com;
814 int ret, i;
815
816 mutex_lock(&qmp->phy_mutex);
817 if (qmp->init_count++) {
818 mutex_unlock(&qmp->phy_mutex);
819 return 0;
820 }
821
822 /* turn on regulator supplies */
823 ret = regulator_bulk_enable(cfg->num_vregs, qmp->vregs);
824 if (ret) {
825 dev_err(qmp->dev, "failed to enable regulators, err=%d\n", ret);
826 goto err_reg_enable;
827 }
828
829 for (i = 0; i < cfg->num_resets; i++) {
830 ret = reset_control_assert(qmp->resets[i]);
831 if (ret) {
832 dev_err(qmp->dev, "%s reset assert failed\n",
833 cfg->reset_list[i]);
834 goto err_rst_assert;
835 }
836 }
837
838 for (i = cfg->num_resets - 1; i >= 0; i--) {
839 ret = reset_control_deassert(qmp->resets[i]);
840 if (ret) {
841 dev_err(qmp->dev, "%s reset deassert failed\n",
842 qmp->cfg->reset_list[i]);
843 goto err_rst;
844 }
845 }
846
847 ret = clk_bulk_prepare_enable(cfg->num_clks, qmp->clks);
848 if (ret) {
849 dev_err(qmp->dev, "failed to enable clks, err=%d\n", ret);
850 goto err_rst;
851 }
852
853 if (cfg->has_phy_com_ctrl)
854 qphy_setbits(serdes, cfg->regs[QPHY_COM_POWER_DOWN_CONTROL],
855 SW_PWRDN);
856
857 if (cfg->has_phy_dp_com_ctrl) {
858 qphy_setbits(dp_com, QPHY_V3_DP_COM_POWER_DOWN_CTRL,
859 SW_PWRDN);
860 /* override hardware control for reset of qmp phy */
861 qphy_setbits(dp_com, QPHY_V3_DP_COM_RESET_OVRD_CTRL,
862 SW_DPPHY_RESET_MUX | SW_DPPHY_RESET |
863 SW_USB3PHY_RESET_MUX | SW_USB3PHY_RESET);
864
865 qphy_setbits(dp_com, QPHY_V3_DP_COM_PHY_MODE_CTRL,
866 USB3_MODE | DP_MODE);
867
868 /* bring both QMP USB and QMP DP PHYs PCS block out of reset */
869 qphy_clrbits(dp_com, QPHY_V3_DP_COM_RESET_OVRD_CTRL,
870 SW_DPPHY_RESET_MUX | SW_DPPHY_RESET |
871 SW_USB3PHY_RESET_MUX | SW_USB3PHY_RESET);
872 }
873
874 /* Serdes configuration */
875 qcom_qmp_phy_configure(serdes, cfg->regs, cfg->serdes_tbl,
876 cfg->serdes_tbl_num);
877
878 if (cfg->has_phy_com_ctrl) {
879 void __iomem *status;
880 unsigned int mask, val;
881
882 qphy_clrbits(serdes, cfg->regs[QPHY_COM_SW_RESET], SW_RESET);
883 qphy_setbits(serdes, cfg->regs[QPHY_COM_START_CONTROL],
884 SERDES_START | PCS_START);
885
886 status = serdes + cfg->regs[QPHY_COM_PCS_READY_STATUS];
887 mask = cfg->mask_com_pcs_ready;
888
889 ret = readl_poll_timeout(status, val, (val & mask), 10,
890 PHY_INIT_COMPLETE_TIMEOUT);
891 if (ret) {
892 dev_err(qmp->dev,
893 "phy common block init timed-out\n");
894 goto err_com_init;
895 }
896 }
897
898 mutex_unlock(&qmp->phy_mutex);
899
900 return 0;
901
902err_com_init:
903 clk_bulk_disable_unprepare(cfg->num_clks, qmp->clks);
904err_rst:
905 while (++i < cfg->num_resets)
906 reset_control_assert(qmp->resets[i]);
907err_rst_assert:
908 regulator_bulk_disable(cfg->num_vregs, qmp->vregs);
909err_reg_enable:
910 mutex_unlock(&qmp->phy_mutex);
911
912 return ret;
913}
914
915static int qcom_qmp_phy_com_exit(struct qcom_qmp *qmp)
916{
917 const struct qmp_phy_cfg *cfg = qmp->cfg;
918 void __iomem *serdes = qmp->serdes;
919 int i = cfg->num_resets;
920
921 mutex_lock(&qmp->phy_mutex);
922 if (--qmp->init_count) {
923 mutex_unlock(&qmp->phy_mutex);
924 return 0;
925 }
926
927 if (cfg->has_phy_com_ctrl) {
928 qphy_setbits(serdes, cfg->regs[QPHY_COM_START_CONTROL],
929 SERDES_START | PCS_START);
930 qphy_clrbits(serdes, cfg->regs[QPHY_COM_SW_RESET],
931 SW_RESET);
932 qphy_setbits(serdes, cfg->regs[QPHY_COM_POWER_DOWN_CONTROL],
933 SW_PWRDN);
934 }
935
936 while (--i >= 0)
937 reset_control_assert(qmp->resets[i]);
938
939 clk_bulk_disable_unprepare(cfg->num_clks, qmp->clks);
940
941 regulator_bulk_disable(cfg->num_vregs, qmp->vregs);
942
943 mutex_unlock(&qmp->phy_mutex);
944
945 return 0;
946}
947
948/* PHY Initialization */
949static int qcom_qmp_phy_init(struct phy *phy)
950{
951 struct qmp_phy *qphy = phy_get_drvdata(phy);
952 struct qcom_qmp *qmp = qphy->qmp;
953 const struct qmp_phy_cfg *cfg = qmp->cfg;
954 void __iomem *tx = qphy->tx;
955 void __iomem *rx = qphy->rx;
956 void __iomem *pcs = qphy->pcs;
957 void __iomem *dp_com = qmp->dp_com;
958 void __iomem *status;
959 unsigned int mask, val;
960 int ret;
961
962 dev_vdbg(qmp->dev, "Initializing QMP phy\n");
963
964 ret = qcom_qmp_phy_com_init(qmp);
965 if (ret)
966 return ret;
967
968 if (cfg->has_lane_rst) {
969 ret = reset_control_deassert(qphy->lane_rst);
970 if (ret) {
971 dev_err(qmp->dev, "lane%d reset deassert failed\n",
972 qphy->index);
973 goto err_lane_rst;
974 }
975 }
976
977 /* Tx, Rx, and PCS configurations */
978 qcom_qmp_phy_configure(tx, cfg->regs, cfg->tx_tbl, cfg->tx_tbl_num);
979 /* Configuration for other LANE for USB-DP combo PHY */
980 if (cfg->has_phy_dp_com_ctrl)
981 qcom_qmp_phy_configure(tx + cfg->tx_b_lane_offset, cfg->regs,
982 cfg->tx_tbl, cfg->tx_tbl_num);
983
984 qcom_qmp_phy_configure(rx, cfg->regs, cfg->rx_tbl, cfg->rx_tbl_num);
985 if (cfg->has_phy_dp_com_ctrl)
986 qcom_qmp_phy_configure(rx + cfg->rx_b_lane_offset, cfg->regs,
987 cfg->rx_tbl, cfg->rx_tbl_num);
988
989 qcom_qmp_phy_configure(pcs, cfg->regs, cfg->pcs_tbl, cfg->pcs_tbl_num);
990
991 /*
992 * Pull out PHY from POWER DOWN state.
993 * This is active low enable signal to power-down PHY.
994 */
995 qphy_setbits(pcs, QPHY_POWER_DOWN_CONTROL, cfg->pwrdn_ctrl);
996
997 if (cfg->has_pwrdn_delay)
998 usleep_range(cfg->pwrdn_delay_min, cfg->pwrdn_delay_max);
999
1000 /* Pull PHY out of reset state */
1001 qphy_clrbits(pcs, cfg->regs[QPHY_SW_RESET], SW_RESET);
1002 if (cfg->has_phy_dp_com_ctrl)
1003 qphy_clrbits(dp_com, QPHY_V3_DP_COM_SW_RESET, SW_RESET);
1004
1005 /* start SerDes and Phy-Coding-Sublayer */
1006 qphy_setbits(pcs, cfg->regs[QPHY_START_CTRL], cfg->start_ctrl);
1007
1008 status = pcs + cfg->regs[QPHY_PCS_READY_STATUS];
1009 mask = cfg->mask_pcs_ready;
1010
1011 ret = readl_poll_timeout(status, val, !(val & mask), 1,
1012 PHY_INIT_COMPLETE_TIMEOUT);
1013 if (ret) {
1014 dev_err(qmp->dev, "phy initialization timed-out\n");
1015 goto err_pcs_ready;
1016 }
1017 qmp->phy_initialized = true;
1018
1019 return ret;
1020
1021err_pcs_ready:
1022 if (cfg->has_lane_rst)
1023 reset_control_assert(qphy->lane_rst);
1024err_lane_rst:
1025 qcom_qmp_phy_com_exit(qmp);
1026
1027 return ret;
1028}
1029
1030static int qcom_qmp_phy_exit(struct phy *phy)
1031{
1032 struct qmp_phy *qphy = phy_get_drvdata(phy);
1033 struct qcom_qmp *qmp = qphy->qmp;
1034 const struct qmp_phy_cfg *cfg = qmp->cfg;
1035
1036 clk_disable_unprepare(qphy->pipe_clk);
1037
1038 /* PHY reset */
1039 qphy_setbits(qphy->pcs, cfg->regs[QPHY_SW_RESET], SW_RESET);
1040
1041 /* stop SerDes and Phy-Coding-Sublayer */
1042 qphy_clrbits(qphy->pcs, cfg->regs[QPHY_START_CTRL], cfg->start_ctrl);
1043
1044 /* Put PHY into POWER DOWN state: active low */
1045 qphy_clrbits(qphy->pcs, QPHY_POWER_DOWN_CONTROL, cfg->pwrdn_ctrl);
1046
1047 if (cfg->has_lane_rst)
1048 reset_control_assert(qphy->lane_rst);
1049
1050 qcom_qmp_phy_com_exit(qmp);
1051
1052 qmp->phy_initialized = false;
1053
1054 return 0;
1055}
1056
1057static int qcom_qmp_phy_set_mode(struct phy *phy, enum phy_mode mode)
1058{
1059 struct qmp_phy *qphy = phy_get_drvdata(phy);
1060 struct qcom_qmp *qmp = qphy->qmp;
1061
1062 qmp->mode = mode;
1063
1064 return 0;
1065}
1066
1067static void qcom_qmp_phy_enable_autonomous_mode(struct qmp_phy *qphy)
1068{
1069 struct qcom_qmp *qmp = qphy->qmp;
1070 const struct qmp_phy_cfg *cfg = qmp->cfg;
1071 void __iomem *pcs = qphy->pcs;
1072 void __iomem *pcs_misc = qphy->pcs_misc;
1073 u32 intr_mask;
1074
1075 if (qmp->mode == PHY_MODE_USB_HOST_SS ||
1076 qmp->mode == PHY_MODE_USB_DEVICE_SS)
1077 intr_mask = ARCVR_DTCT_EN | ALFPS_DTCT_EN;
1078 else
1079 intr_mask = ARCVR_DTCT_EN | ARCVR_DTCT_EVENT_SEL;
1080
1081 /* Clear any pending interrupts status */
1082 qphy_setbits(pcs, cfg->regs[QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR], IRQ_CLEAR);
1083 /* Writing 1 followed by 0 clears the interrupt */
1084 qphy_clrbits(pcs, cfg->regs[QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR], IRQ_CLEAR);
1085
1086 qphy_clrbits(pcs, cfg->regs[QPHY_PCS_AUTONOMOUS_MODE_CTRL],
1087 ARCVR_DTCT_EN | ALFPS_DTCT_EN | ARCVR_DTCT_EVENT_SEL);
1088
1089 /* Enable required PHY autonomous mode interrupts */
1090 qphy_setbits(pcs, cfg->regs[QPHY_PCS_AUTONOMOUS_MODE_CTRL], intr_mask);
1091
1092 /* Enable i/o clamp_n for autonomous mode */
1093 if (pcs_misc)
1094 qphy_clrbits(pcs_misc, QPHY_V3_PCS_MISC_CLAMP_ENABLE, CLAMP_EN);
1095}
1096
1097static void qcom_qmp_phy_disable_autonomous_mode(struct qmp_phy *qphy)
1098{
1099 struct qcom_qmp *qmp = qphy->qmp;
1100 const struct qmp_phy_cfg *cfg = qmp->cfg;
1101 void __iomem *pcs = qphy->pcs;
1102 void __iomem *pcs_misc = qphy->pcs_misc;
1103
1104 /* Disable i/o clamp_n on resume for normal mode */
1105 if (pcs_misc)
1106 qphy_setbits(pcs_misc, QPHY_V3_PCS_MISC_CLAMP_ENABLE, CLAMP_EN);
1107
1108 qphy_clrbits(pcs, cfg->regs[QPHY_PCS_AUTONOMOUS_MODE_CTRL],
1109 ARCVR_DTCT_EN | ARCVR_DTCT_EVENT_SEL | ALFPS_DTCT_EN);
1110
1111 qphy_setbits(pcs, cfg->regs[QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR], IRQ_CLEAR);
1112 /* Writing 1 followed by 0 clears the interrupt */
1113 qphy_clrbits(pcs, cfg->regs[QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR], IRQ_CLEAR);
1114}
1115
1116static int __maybe_unused qcom_qmp_phy_runtime_suspend(struct device *dev)
1117{
1118 struct qcom_qmp *qmp = dev_get_drvdata(dev);
1119 struct qmp_phy *qphy = qmp->phys[0];
1120 const struct qmp_phy_cfg *cfg = qmp->cfg;
1121
1122 dev_vdbg(dev, "Suspending QMP phy, mode:%d\n", qmp->mode);
1123
1124 /* Supported only for USB3 PHY */
1125 if (cfg->type != PHY_TYPE_USB3)
1126 return 0;
1127
1128 if (!qmp->phy_initialized) {
1129 dev_vdbg(dev, "PHY not initialized, bailing out\n");
1130 return 0;
1131 }
1132
1133 qcom_qmp_phy_enable_autonomous_mode(qphy);
1134
1135 clk_disable_unprepare(qphy->pipe_clk);
1136 clk_bulk_disable_unprepare(cfg->num_clks, qmp->clks);
1137
1138 return 0;
1139}
1140
1141static int __maybe_unused qcom_qmp_phy_runtime_resume(struct device *dev)
1142{
1143 struct qcom_qmp *qmp = dev_get_drvdata(dev);
1144 struct qmp_phy *qphy = qmp->phys[0];
1145 const struct qmp_phy_cfg *cfg = qmp->cfg;
1146 int ret = 0;
1147
1148 dev_vdbg(dev, "Resuming QMP phy, mode:%d\n", qmp->mode);
1149
1150 /* Supported only for USB3 PHY */
1151 if (cfg->type != PHY_TYPE_USB3)
1152 return 0;
1153
1154 if (!qmp->phy_initialized) {
1155 dev_vdbg(dev, "PHY not initialized, bailing out\n");
1156 return 0;
1157 }
1158
1159 ret = clk_bulk_prepare_enable(cfg->num_clks, qmp->clks);
1160 if (ret) {
1161 dev_err(qmp->dev, "failed to enable clks, err=%d\n", ret);
1162 return ret;
1163 }
1164
1165 ret = clk_prepare_enable(qphy->pipe_clk);
1166 if (ret) {
1167 dev_err(dev, "pipe_clk enable failed, err=%d\n", ret);
1168 clk_bulk_disable_unprepare(cfg->num_clks, qmp->clks);
1169 return ret;
1170 }
1171
1172 qcom_qmp_phy_disable_autonomous_mode(qphy);
1173
1174 return 0;
1175}
1176
1177static int qcom_qmp_phy_vreg_init(struct device *dev)
1178{
1179 struct qcom_qmp *qmp = dev_get_drvdata(dev);
1180 int num = qmp->cfg->num_vregs;
1181 int i;
1182
1183 qmp->vregs = devm_kcalloc(dev, num, sizeof(*qmp->vregs), GFP_KERNEL);
1184 if (!qmp->vregs)
1185 return -ENOMEM;
1186
1187 for (i = 0; i < num; i++)
1188 qmp->vregs[i].supply = qmp->cfg->vreg_list[i];
1189
1190 return devm_regulator_bulk_get(dev, num, qmp->vregs);
1191}
1192
1193static int qcom_qmp_phy_reset_init(struct device *dev)
1194{
1195 struct qcom_qmp *qmp = dev_get_drvdata(dev);
1196 int i;
1197
1198 qmp->resets = devm_kcalloc(dev, qmp->cfg->num_resets,
1199 sizeof(*qmp->resets), GFP_KERNEL);
1200 if (!qmp->resets)
1201 return -ENOMEM;
1202
1203 for (i = 0; i < qmp->cfg->num_resets; i++) {
1204 struct reset_control *rst;
1205 const char *name = qmp->cfg->reset_list[i];
1206
1207 rst = devm_reset_control_get(dev, name);
1208 if (IS_ERR(rst)) {
1209 dev_err(dev, "failed to get %s reset\n", name);
1210 return PTR_ERR(rst);
1211 }
1212 qmp->resets[i] = rst;
1213 }
1214
1215 return 0;
1216}
1217
1218static int qcom_qmp_phy_clk_init(struct device *dev)
1219{
1220 struct qcom_qmp *qmp = dev_get_drvdata(dev);
1221 int num = qmp->cfg->num_clks;
1222 int i;
1223
1224 qmp->clks = devm_kcalloc(dev, num, sizeof(*qmp->clks), GFP_KERNEL);
1225 if (!qmp->clks)
1226 return -ENOMEM;
1227
1228 for (i = 0; i < num; i++)
1229 qmp->clks[i].id = qmp->cfg->clk_list[i];
1230
1231 return devm_clk_bulk_get(dev, num, qmp->clks);
1232}
1233
1234/*
1235 * Register a fixed rate pipe clock.
1236 *
1237 * The <s>_pipe_clksrc generated by PHY goes to the GCC that gate
1238 * controls it. The <s>_pipe_clk coming out of the GCC is requested
1239 * by the PHY driver for its operations.
1240 * We register the <s>_pipe_clksrc here. The gcc driver takes care
1241 * of assigning this <s>_pipe_clksrc as parent to <s>_pipe_clk.
1242 * Below picture shows this relationship.
1243 *
1244 * +---------------+
1245 * | PHY block |<<---------------------------------------+
1246 * | | |
1247 * | +-------+ | +-----+ |
1248 * I/P---^-->| PLL |---^--->pipe_clksrc--->| GCC |--->pipe_clk---+
1249 * clk | +-------+ | +-----+
1250 * +---------------+
1251 */
1252static int phy_pipe_clk_register(struct qcom_qmp *qmp, struct device_node *np)
1253{
1254 struct clk_fixed_rate *fixed;
1255 struct clk_init_data init = { };
1256 int ret;
1257
1258 if ((qmp->cfg->type != PHY_TYPE_USB3) &&
1259 (qmp->cfg->type != PHY_TYPE_PCIE)) {
1260 /* not all phys register pipe clocks, so return success */
1261 return 0;
1262 }
1263
1264 ret = of_property_read_string(np, "clock-output-names", &init.name);
1265 if (ret) {
1266 dev_err(qmp->dev, "%s: No clock-output-names\n", np->name);
1267 return ret;
1268 }
1269
1270 fixed = devm_kzalloc(qmp->dev, sizeof(*fixed), GFP_KERNEL);
1271 if (!fixed)
1272 return -ENOMEM;
1273
1274 init.ops = &clk_fixed_rate_ops;
1275
1276 /* controllers using QMP phys use 125MHz pipe clock interface */
1277 fixed->fixed_rate = 125000000;
1278 fixed->hw.init = &init;
1279
1280 return devm_clk_hw_register(qmp->dev, &fixed->hw);
1281}
1282
1283static const struct phy_ops qcom_qmp_phy_gen_ops = {
1284 .init = qcom_qmp_phy_init,
1285 .exit = qcom_qmp_phy_exit,
1286 .power_on = qcom_qmp_phy_poweron,
1287 .set_mode = qcom_qmp_phy_set_mode,
1288 .owner = THIS_MODULE,
1289};
1290
1291static
1292int qcom_qmp_phy_create(struct device *dev, struct device_node *np, int id)
1293{
1294 struct qcom_qmp *qmp = dev_get_drvdata(dev);
1295 struct phy *generic_phy;
1296 struct qmp_phy *qphy;
1297 char prop_name[MAX_PROP_NAME];
1298 int ret;
1299
1300 qphy = devm_kzalloc(dev, sizeof(*qphy), GFP_KERNEL);
1301 if (!qphy)
1302 return -ENOMEM;
1303
1304 /*
1305 * Get memory resources for each phy lane:
1306 * Resources are indexed as: tx -> 0; rx -> 1; pcs -> 2; and
1307 * pcs_misc (optional) -> 3.
1308 */
1309 qphy->tx = of_iomap(np, 0);
1310 if (!qphy->tx)
1311 return -ENOMEM;
1312
1313 qphy->rx = of_iomap(np, 1);
1314 if (!qphy->rx)
1315 return -ENOMEM;
1316
1317 qphy->pcs = of_iomap(np, 2);
1318 if (!qphy->pcs)
1319 return -ENOMEM;
1320
1321 qphy->pcs_misc = of_iomap(np, 3);
1322 if (!qphy->pcs_misc)
1323 dev_vdbg(dev, "PHY pcs_misc-reg not used\n");
1324
1325 /*
1326 * Get PHY's Pipe clock, if any. USB3 and PCIe are PIPE3
1327 * based phys, so they essentially have pipe clock. So,
1328 * we return error in case phy is USB3 or PIPE type.
1329 * Otherwise, we initialize pipe clock to NULL for
1330 * all phys that don't need this.
1331 */
1332 snprintf(prop_name, sizeof(prop_name), "pipe%d", id);
1333 qphy->pipe_clk = of_clk_get_by_name(np, prop_name);
1334 if (IS_ERR(qphy->pipe_clk)) {
1335 if (qmp->cfg->type == PHY_TYPE_PCIE ||
1336 qmp->cfg->type == PHY_TYPE_USB3) {
1337 ret = PTR_ERR(qphy->pipe_clk);
1338 if (ret != -EPROBE_DEFER)
1339 dev_err(dev,
1340 "failed to get lane%d pipe_clk, %d\n",
1341 id, ret);
1342 return ret;
1343 }
1344 qphy->pipe_clk = NULL;
1345 }
1346
1347 /* Get lane reset, if any */
1348 if (qmp->cfg->has_lane_rst) {
1349 snprintf(prop_name, sizeof(prop_name), "lane%d", id);
1350 qphy->lane_rst = of_reset_control_get(np, prop_name);
1351 if (IS_ERR(qphy->lane_rst)) {
1352 dev_err(dev, "failed to get lane%d reset\n", id);
1353 return PTR_ERR(qphy->lane_rst);
1354 }
1355 }
1356
1357 generic_phy = devm_phy_create(dev, np, &qcom_qmp_phy_gen_ops);
1358 if (IS_ERR(generic_phy)) {
1359 ret = PTR_ERR(generic_phy);
1360 dev_err(dev, "failed to create qphy %d\n", ret);
1361 return ret;
1362 }
1363
1364 qphy->phy = generic_phy;
1365 qphy->index = id;
1366 qphy->qmp = qmp;
1367 qmp->phys[id] = qphy;
1368 phy_set_drvdata(generic_phy, qphy);
1369
1370 return 0;
1371}
1372
1373static const struct of_device_id qcom_qmp_phy_of_match_table[] = {
1374 {
1375 .compatible = "qcom,msm8996-qmp-pcie-phy",
1376 .data = &msm8996_pciephy_cfg,
1377 }, {
1378 .compatible = "qcom,msm8996-qmp-usb3-phy",
1379 .data = &msm8996_usb3phy_cfg,
1380 }, {
1381 .compatible = "qcom,ipq8074-qmp-pcie-phy",
1382 .data = &ipq8074_pciephy_cfg,
1383 }, {
1384 .compatible = "qcom,qmp-v3-usb3-phy",
1385 .data = &qmp_v3_usb3phy_cfg,
1386 },
1387 { },
1388};
1389MODULE_DEVICE_TABLE(of, qcom_qmp_phy_of_match_table);
1390
1391static const struct dev_pm_ops qcom_qmp_phy_pm_ops = {
1392 SET_RUNTIME_PM_OPS(qcom_qmp_phy_runtime_suspend,
1393 qcom_qmp_phy_runtime_resume, NULL)
1394};
1395
1396static int qcom_qmp_phy_probe(struct platform_device *pdev)
1397{
1398 struct qcom_qmp *qmp;
1399 struct device *dev = &pdev->dev;
1400 struct resource *res;
1401 struct device_node *child;
1402 struct phy_provider *phy_provider;
1403 void __iomem *base;
1404 int num, id;
1405 int ret;
1406
1407 qmp = devm_kzalloc(dev, sizeof(*qmp), GFP_KERNEL);
1408 if (!qmp)
1409 return -ENOMEM;
1410
1411 qmp->dev = dev;
1412 dev_set_drvdata(dev, qmp);
1413
1414 /* Get the specific init parameters of QMP phy */
1415 qmp->cfg = of_device_get_match_data(dev);
1416 if (!qmp->cfg)
1417 return -EINVAL;
1418
1419 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1420 base = devm_ioremap_resource(dev, res);
1421 if (IS_ERR(base))
1422 return PTR_ERR(base);
1423
1424 /* per PHY serdes; usually located at base address */
1425 qmp->serdes = base;
1426
1427 /* per PHY dp_com; if PHY has dp_com control block */
1428 if (qmp->cfg->has_phy_dp_com_ctrl) {
1429 res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
1430 "dp_com");
1431 base = devm_ioremap_resource(dev, res);
1432 if (IS_ERR(base))
1433 return PTR_ERR(base);
1434
1435 qmp->dp_com = base;
1436 }
1437
1438 mutex_init(&qmp->phy_mutex);
1439
1440 ret = qcom_qmp_phy_clk_init(dev);
1441 if (ret)
1442 return ret;
1443
1444 ret = qcom_qmp_phy_reset_init(dev);
1445 if (ret)
1446 return ret;
1447
1448 ret = qcom_qmp_phy_vreg_init(dev);
1449 if (ret) {
1450 dev_err(dev, "failed to get regulator supplies\n");
1451 return ret;
1452 }
1453
1454 num = of_get_available_child_count(dev->of_node);
1455 /* do we have a rogue child node ? */
1456 if (num > qmp->cfg->nlanes)
1457 return -EINVAL;
1458
1459 qmp->phys = devm_kcalloc(dev, num, sizeof(*qmp->phys), GFP_KERNEL);
1460 if (!qmp->phys)
1461 return -ENOMEM;
1462
1463 id = 0;
1464 pm_runtime_set_active(dev);
1465 pm_runtime_enable(dev);
1466 /*
1467 * Prevent runtime pm from being ON by default. Users can enable
1468 * it using power/control in sysfs.
1469 */
1470 pm_runtime_forbid(dev);
1471
1472 for_each_available_child_of_node(dev->of_node, child) {
1473 /* Create per-lane phy */
1474 ret = qcom_qmp_phy_create(dev, child, id);
1475 if (ret) {
1476 dev_err(dev, "failed to create lane%d phy, %d\n",
1477 id, ret);
1478 pm_runtime_disable(dev);
1479 return ret;
1480 }
1481
1482 /*
1483 * Register the pipe clock provided by phy.
1484 * See function description to see details of this pipe clock.
1485 */
1486 ret = phy_pipe_clk_register(qmp, child);
1487 if (ret) {
1488 dev_err(qmp->dev,
1489 "failed to register pipe clock source\n");
1490 pm_runtime_disable(dev);
1491 return ret;
1492 }
1493 id++;
1494 }
1495
1496 phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate);
1497 if (!IS_ERR(phy_provider))
1498 dev_info(dev, "Registered Qcom-QMP phy\n");
1499 else
1500 pm_runtime_disable(dev);
1501
1502 return PTR_ERR_OR_ZERO(phy_provider);
1503}
1504
1505static struct platform_driver qcom_qmp_phy_driver = {
1506 .probe = qcom_qmp_phy_probe,
1507 .driver = {
1508 .name = "qcom-qmp-phy",
1509 .pm = &qcom_qmp_phy_pm_ops,
1510 .of_match_table = qcom_qmp_phy_of_match_table,
1511 },
1512};
1513
1514module_platform_driver(qcom_qmp_phy_driver);
1515
1516MODULE_AUTHOR("Vivek Gautam <vivek.gautam@codeaurora.org>");
1517MODULE_DESCRIPTION("Qualcomm QMP PHY driver");
1518MODULE_LICENSE("GPL v2");