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1Qualcomm QMP PHY controller
2===========================
3
4QMP phy controller supports physical layer functionality for a number of
5controllers on Qualcomm chipsets, such as, PCIe, UFS, and USB.
6
7Required properties:
8 - compatible: compatible list, contains:
9 "qcom,ipq8074-qmp-pcie-phy" for PCIe phy on IPQ8074
10 "qcom,msm8996-qmp-pcie-phy" for 14nm PCIe phy on msm8996,
11 "qcom,msm8996-qmp-usb3-phy" for 14nm USB3 phy on msm8996,
12 "qcom,qmp-v3-usb3-phy" for USB3 QMP V3 phy.
13
14 - reg: offset and length of register set for PHY's common serdes block.
15
16 - #clock-cells: must be 1
17 - Phy pll outputs a bunch of clocks for Tx, Rx and Pipe
18 interface (for pipe based PHYs). These clock are then gate-controlled
19 by gcc.
20 - #address-cells: must be 1
21 - #size-cells: must be 1
22 - ranges: must be present
23
24 - clocks: a list of phandles and clock-specifier pairs,
25 one for each entry in clock-names.
26 - clock-names: "cfg_ahb" for phy config clock,
27 "aux" for phy aux clock,
28 "ref" for 19.2 MHz ref clk,
29 "com_aux" for phy common block aux clock,
30 For "qcom,msm8996-qmp-pcie-phy" must contain:
31 "aux", "cfg_ahb", "ref".
32 For "qcom,msm8996-qmp-usb3-phy" must contain:
33 "aux", "cfg_ahb", "ref".
34 For "qcom,qmp-v3-usb3-phy" must contain:
35 "aux", "cfg_ahb", "ref", "com_aux".
36
37 - resets: a list of phandles and reset controller specifier pairs,
38 one for each entry in reset-names.
39 - reset-names: "phy" for reset of phy block,
40 "common" for phy common block reset,
41 "cfg" for phy's ahb cfg block reset (Optional).
42 For "qcom,msm8996-qmp-pcie-phy" must contain:
43 "phy", "common", "cfg".
44 For "qcom,msm8996-qmp-usb3-phy" must contain
45 "phy", "common".
46 For "qcom,ipq8074-qmp-pcie-phy" must contain:
47 "phy", "common".
48
49 - vdda-phy-supply: Phandle to a regulator supply to PHY core block.
50 - vdda-pll-supply: Phandle to 1.8V regulator supply to PHY refclk pll block.
51
52Optional properties:
53 - vddp-ref-clk-supply: Phandle to a regulator supply to any specific refclk
54 pll block.
55
56Required nodes:
57 - Each device node of QMP phy is required to have as many child nodes as
58 the number of lanes the PHY has.
59
60Required properties for child node:
61 - reg: list of offset and length pairs of register sets for PHY blocks -
62 tx, rx and pcs.
63
64 - #phy-cells: must be 0
65
66 - clocks: a list of phandles and clock-specifier pairs,
67 one for each entry in clock-names.
68 - clock-names: Must contain following for pcie and usb qmp phys:
69 "pipe<lane-number>" for pipe clock specific to each lane.
70 - clock-output-names: Name of the PHY clock that will be the parent for
71 the above pipe clock.
72
73 For "qcom,ipq8074-qmp-pcie-phy":
74 - "pcie20_phy0_pipe_clk" Pipe Clock parent
75 (or)
76 "pcie20_phy1_pipe_clk"
77
78 - resets: a list of phandles and reset controller specifier pairs,
79 one for each entry in reset-names.
80 - reset-names: Must contain following for pcie qmp phys:
81 "lane<lane-number>" for reset specific to each lane.
82
83Example:
84 phy@34000 {
85 compatible = "qcom,msm8996-qmp-pcie-phy";
86 reg = <0x34000 0x488>;
87 #clock-cells = <1>;
88 #address-cells = <1>;
89 #size-cells = <1>;
90 ranges;
91
92 clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>,
93 <&gcc GCC_PCIE_PHY_CFG_AHB_CLK>,
94 <&gcc GCC_PCIE_CLKREF_CLK>;
95 clock-names = "aux", "cfg_ahb", "ref";
96
97 vdda-phy-supply = <&pm8994_l28>;
98 vdda-pll-supply = <&pm8994_l12>;
99
100 resets = <&gcc GCC_PCIE_PHY_BCR>,
101 <&gcc GCC_PCIE_PHY_COM_BCR>,
102 <&gcc GCC_PCIE_PHY_COM_NOCSR_BCR>;
103 reset-names = "phy", "common", "cfg";
104
105 pciephy_0: lane@35000 {
106 reg = <0x35000 0x130>,
107 <0x35200 0x200>,
108 <0x35400 0x1dc>;
109 #phy-cells = <0>;
110
111 clocks = <&gcc GCC_PCIE_0_PIPE_CLK>;
112 clock-names = "pipe0";
113 clock-output-names = "pcie_0_pipe_clk_src";
114 resets = <&gcc GCC_PCIE_0_PHY_BCR>;
115 reset-names = "lane0";
116 };
117
118 pciephy_1: lane@36000 {
119 ...
120 ...
121 };