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at v4.17-rc2 32 lines 1.1 kB view raw
1Allwinner Display Engine 2.0 Clock Control Binding 2-------------------------------------------------- 3 4Required properties : 5- compatible: must contain one of the following compatibles: 6 - "allwinner,sun8i-a83t-de2-clk" 7 - "allwinner,sun8i-h3-de2-clk" 8 - "allwinner,sun8i-v3s-de2-clk" 9 - "allwinner,sun50i-h5-de2-clk" 10 11- reg: Must contain the registers base address and length 12- clocks: phandle to the clocks feeding the display engine subsystem. 13 Three are needed: 14 - "mod": the display engine module clock (on A83T it's the DE PLL) 15 - "bus": the bus clock for the whole display engine subsystem 16- clock-names: Must contain the clock names described just above 17- resets: phandle to the reset control for the display engine subsystem. 18- #clock-cells : must contain 1 19- #reset-cells : must contain 1 20 21Example: 22de2_clocks: clock@1000000 { 23 compatible = "allwinner,sun8i-h3-de2-clk"; 24 reg = <0x01000000 0x100000>; 25 clocks = <&ccu CLK_BUS_DE>, 26 <&ccu CLK_DE>; 27 clock-names = "bus", 28 "mod"; 29 resets = <&ccu RST_BUS_DE>; 30 #clock-cells = <1>; 31 #reset-cells = <1>; 32};