tjh.dev
Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
fork
Configure Feed
Select the types of activity you want to include in your feed.
1 PCI TEST
2 Kishon Vijay Abraham I <kishon@ti.com>
3
4Traditionally PCI RC has always been validated by using standard
5PCI cards like ethernet PCI cards or USB PCI cards or SATA PCI cards.
6However with the addition of EP-core in linux kernel, it is possible
7to configure a PCI controller that can operate in EP mode to work as
8a test device.
9
10The PCI endpoint test device is a virtual device (defined in software)
11used to test the endpoint functionality and serve as a sample driver
12for other PCI endpoint devices (to use the EP framework).
13
14The PCI endpoint test device has the following registers:
15
16 1) PCI_ENDPOINT_TEST_MAGIC
17 2) PCI_ENDPOINT_TEST_COMMAND
18 3) PCI_ENDPOINT_TEST_STATUS
19 4) PCI_ENDPOINT_TEST_SRC_ADDR
20 5) PCI_ENDPOINT_TEST_DST_ADDR
21 6) PCI_ENDPOINT_TEST_SIZE
22 7) PCI_ENDPOINT_TEST_CHECKSUM
23
24*) PCI_ENDPOINT_TEST_MAGIC
25
26This register will be used to test BAR0. A known pattern will be written
27and read back from MAGIC register to verify BAR0.
28
29*) PCI_ENDPOINT_TEST_COMMAND:
30
31This register will be used by the host driver to indicate the function
32that the endpoint device must perform.
33
34Bitfield Description:
35 Bit 0 : raise legacy IRQ
36 Bit 1 : raise MSI IRQ
37 Bit 2 - 7 : MSI interrupt number
38 Bit 8 : read command (read data from RC buffer)
39 Bit 9 : write command (write data to RC buffer)
40 Bit 10 : copy command (copy data from one RC buffer to another
41 RC buffer)
42
43*) PCI_ENDPOINT_TEST_STATUS
44
45This register reflects the status of the PCI endpoint device.
46
47Bitfield Description:
48 Bit 0 : read success
49 Bit 1 : read fail
50 Bit 2 : write success
51 Bit 3 : write fail
52 Bit 4 : copy success
53 Bit 5 : copy fail
54 Bit 6 : IRQ raised
55 Bit 7 : source address is invalid
56 Bit 8 : destination address is invalid
57
58*) PCI_ENDPOINT_TEST_SRC_ADDR
59
60This register contains the source address (RC buffer address) for the
61COPY/READ command.
62
63*) PCI_ENDPOINT_TEST_DST_ADDR
64
65This register contains the destination address (RC buffer address) for
66the COPY/WRITE command.