tjh.dev
Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
1/*
2 * DMA support for Internal DMAC with SDHI SD/SDIO controller
3 *
4 * Copyright (C) 2016-17 Renesas Electronics Corporation
5 * Copyright (C) 2016-17 Horms Solutions, Simon Horman
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10 */
11
12#include <linux/device.h>
13#include <linux/dma-mapping.h>
14#include <linux/io-64-nonatomic-hi-lo.h>
15#include <linux/mfd/tmio.h>
16#include <linux/mmc/host.h>
17#include <linux/mod_devicetable.h>
18#include <linux/module.h>
19#include <linux/pagemap.h>
20#include <linux/scatterlist.h>
21#include <linux/sys_soc.h>
22
23#include "renesas_sdhi.h"
24#include "tmio_mmc.h"
25
26#define DM_CM_DTRAN_MODE 0x820
27#define DM_CM_DTRAN_CTRL 0x828
28#define DM_CM_RST 0x830
29#define DM_CM_INFO1 0x840
30#define DM_CM_INFO1_MASK 0x848
31#define DM_CM_INFO2 0x850
32#define DM_CM_INFO2_MASK 0x858
33#define DM_DTRAN_ADDR 0x880
34
35/* DM_CM_DTRAN_MODE */
36#define DTRAN_MODE_CH_NUM_CH0 0 /* "downstream" = for write commands */
37#define DTRAN_MODE_CH_NUM_CH1 BIT(16) /* "uptream" = for read commands */
38#define DTRAN_MODE_BUS_WID_TH (BIT(5) | BIT(4))
39#define DTRAN_MODE_ADDR_MODE BIT(0) /* 1 = Increment address */
40
41/* DM_CM_DTRAN_CTRL */
42#define DTRAN_CTRL_DM_START BIT(0)
43
44/* DM_CM_RST */
45#define RST_DTRANRST1 BIT(9)
46#define RST_DTRANRST0 BIT(8)
47#define RST_RESERVED_BITS GENMASK_ULL(32, 0)
48
49/* DM_CM_INFO1 and DM_CM_INFO1_MASK */
50#define INFO1_CLEAR 0
51#define INFO1_DTRANEND1 BIT(17)
52#define INFO1_DTRANEND0 BIT(16)
53
54/* DM_CM_INFO2 and DM_CM_INFO2_MASK */
55#define INFO2_DTRANERR1 BIT(17)
56#define INFO2_DTRANERR0 BIT(16)
57
58/*
59 * Specification of this driver:
60 * - host->chan_{rx,tx} will be used as a flag of enabling/disabling the dma
61 * - Since this SDHI DMAC register set has 16 but 32-bit width, we
62 * need a custom accessor.
63 */
64
65/* Definitions for sampling clocks */
66static struct renesas_sdhi_scc rcar_gen3_scc_taps[] = {
67 {
68 .clk_rate = 0,
69 .tap = 0x00000300,
70 },
71};
72
73static const struct renesas_sdhi_of_data of_rcar_gen3_compatible = {
74 .tmio_flags = TMIO_MMC_HAS_IDLE_WAIT | TMIO_MMC_WRPROTECT_DISABLE |
75 TMIO_MMC_CLK_ACTUAL | TMIO_MMC_HAVE_CBSY |
76 TMIO_MMC_MIN_RCAR2,
77 .capabilities = MMC_CAP_SD_HIGHSPEED | MMC_CAP_SDIO_IRQ |
78 MMC_CAP_CMD23,
79 .bus_shift = 2,
80 .scc_offset = 0x1000,
81 .taps = rcar_gen3_scc_taps,
82 .taps_num = ARRAY_SIZE(rcar_gen3_scc_taps),
83 /* Gen3 SDHI DMAC can handle 0xffffffff blk count, but seg = 1 */
84 .max_blk_count = 0xffffffff,
85 .max_segs = 1,
86};
87
88static const struct of_device_id renesas_sdhi_internal_dmac_of_match[] = {
89 { .compatible = "renesas,sdhi-r8a7795", .data = &of_rcar_gen3_compatible, },
90 { .compatible = "renesas,sdhi-r8a7796", .data = &of_rcar_gen3_compatible, },
91 { .compatible = "renesas,rcar-gen3-sdhi", .data = &of_rcar_gen3_compatible, },
92 {},
93};
94MODULE_DEVICE_TABLE(of, renesas_sdhi_internal_dmac_of_match);
95
96static void
97renesas_sdhi_internal_dmac_dm_write(struct tmio_mmc_host *host,
98 int addr, u64 val)
99{
100 writeq(val, host->ctl + addr);
101}
102
103static void
104renesas_sdhi_internal_dmac_enable_dma(struct tmio_mmc_host *host, bool enable)
105{
106 struct renesas_sdhi *priv = host_to_priv(host);
107
108 if (!host->chan_tx || !host->chan_rx)
109 return;
110
111 if (!enable)
112 renesas_sdhi_internal_dmac_dm_write(host, DM_CM_INFO1,
113 INFO1_CLEAR);
114
115 if (priv->dma_priv.enable)
116 priv->dma_priv.enable(host, enable);
117}
118
119static void
120renesas_sdhi_internal_dmac_abort_dma(struct tmio_mmc_host *host) {
121 u64 val = RST_DTRANRST1 | RST_DTRANRST0;
122
123 renesas_sdhi_internal_dmac_enable_dma(host, false);
124
125 renesas_sdhi_internal_dmac_dm_write(host, DM_CM_RST,
126 RST_RESERVED_BITS & ~val);
127 renesas_sdhi_internal_dmac_dm_write(host, DM_CM_RST,
128 RST_RESERVED_BITS | val);
129
130 renesas_sdhi_internal_dmac_enable_dma(host, true);
131}
132
133static void
134renesas_sdhi_internal_dmac_dataend_dma(struct tmio_mmc_host *host) {
135 struct renesas_sdhi *priv = host_to_priv(host);
136
137 tasklet_schedule(&priv->dma_priv.dma_complete);
138}
139
140static void
141renesas_sdhi_internal_dmac_start_dma(struct tmio_mmc_host *host,
142 struct mmc_data *data)
143{
144 struct scatterlist *sg = host->sg_ptr;
145 u32 dtran_mode = DTRAN_MODE_BUS_WID_TH | DTRAN_MODE_ADDR_MODE;
146 enum dma_data_direction dir;
147 int ret;
148 u32 irq_mask;
149
150 /* This DMAC cannot handle if sg_len is not 1 */
151 WARN_ON(host->sg_len > 1);
152
153 /* This DMAC cannot handle if buffer is not 8-bytes alignment */
154 if (!IS_ALIGNED(sg->offset, 8))
155 goto force_pio;
156
157 if (data->flags & MMC_DATA_READ) {
158 dtran_mode |= DTRAN_MODE_CH_NUM_CH1;
159 dir = DMA_FROM_DEVICE;
160 irq_mask = TMIO_STAT_RXRDY;
161 } else {
162 dtran_mode |= DTRAN_MODE_CH_NUM_CH0;
163 dir = DMA_TO_DEVICE;
164 irq_mask = TMIO_STAT_TXRQ;
165 }
166
167 ret = dma_map_sg(&host->pdev->dev, sg, host->sg_len, dir);
168 if (ret == 0)
169 goto force_pio;
170
171 renesas_sdhi_internal_dmac_enable_dma(host, true);
172
173 /* disable PIO irqs to avoid "PIO IRQ in DMA mode!" */
174 tmio_mmc_disable_mmc_irqs(host, irq_mask);
175
176 /* set dma parameters */
177 renesas_sdhi_internal_dmac_dm_write(host, DM_CM_DTRAN_MODE,
178 dtran_mode);
179 renesas_sdhi_internal_dmac_dm_write(host, DM_DTRAN_ADDR,
180 sg->dma_address);
181
182 return;
183
184force_pio:
185 host->force_pio = true;
186 renesas_sdhi_internal_dmac_enable_dma(host, false);
187}
188
189static void renesas_sdhi_internal_dmac_issue_tasklet_fn(unsigned long arg)
190{
191 struct tmio_mmc_host *host = (struct tmio_mmc_host *)arg;
192
193 tmio_mmc_enable_mmc_irqs(host, TMIO_STAT_DATAEND);
194
195 /* start the DMAC */
196 renesas_sdhi_internal_dmac_dm_write(host, DM_CM_DTRAN_CTRL,
197 DTRAN_CTRL_DM_START);
198}
199
200static void renesas_sdhi_internal_dmac_complete_tasklet_fn(unsigned long arg)
201{
202 struct tmio_mmc_host *host = (struct tmio_mmc_host *)arg;
203 enum dma_data_direction dir;
204
205 spin_lock_irq(&host->lock);
206
207 if (!host->data)
208 goto out;
209
210 if (host->data->flags & MMC_DATA_READ)
211 dir = DMA_FROM_DEVICE;
212 else
213 dir = DMA_TO_DEVICE;
214
215 renesas_sdhi_internal_dmac_enable_dma(host, false);
216 dma_unmap_sg(&host->pdev->dev, host->sg_ptr, host->sg_len, dir);
217
218 tmio_mmc_do_data_irq(host);
219out:
220 spin_unlock_irq(&host->lock);
221}
222
223static void
224renesas_sdhi_internal_dmac_request_dma(struct tmio_mmc_host *host,
225 struct tmio_mmc_data *pdata)
226{
227 struct renesas_sdhi *priv = host_to_priv(host);
228
229 /* Each value is set to non-zero to assume "enabling" each DMA */
230 host->chan_rx = host->chan_tx = (void *)0xdeadbeaf;
231
232 tasklet_init(&priv->dma_priv.dma_complete,
233 renesas_sdhi_internal_dmac_complete_tasklet_fn,
234 (unsigned long)host);
235 tasklet_init(&host->dma_issue,
236 renesas_sdhi_internal_dmac_issue_tasklet_fn,
237 (unsigned long)host);
238}
239
240static void
241renesas_sdhi_internal_dmac_release_dma(struct tmio_mmc_host *host)
242{
243 /* Each value is set to zero to assume "disabling" each DMA */
244 host->chan_rx = host->chan_tx = NULL;
245}
246
247static const struct tmio_mmc_dma_ops renesas_sdhi_internal_dmac_dma_ops = {
248 .start = renesas_sdhi_internal_dmac_start_dma,
249 .enable = renesas_sdhi_internal_dmac_enable_dma,
250 .request = renesas_sdhi_internal_dmac_request_dma,
251 .release = renesas_sdhi_internal_dmac_release_dma,
252 .abort = renesas_sdhi_internal_dmac_abort_dma,
253 .dataend = renesas_sdhi_internal_dmac_dataend_dma,
254};
255
256/*
257 * Whitelist of specific R-Car Gen3 SoC ES versions to use this DMAC
258 * implementation as others may use a different implementation.
259 */
260static const struct soc_device_attribute gen3_soc_whitelist[] = {
261 { .soc_id = "r8a7795", .revision = "ES1.*" },
262 { .soc_id = "r8a7795", .revision = "ES2.0" },
263 { .soc_id = "r8a7796", .revision = "ES1.0" },
264 { .soc_id = "r8a77995", .revision = "ES1.0" },
265 { /* sentinel */ }
266};
267
268static int renesas_sdhi_internal_dmac_probe(struct platform_device *pdev)
269{
270 if (!soc_device_match(gen3_soc_whitelist))
271 return -ENODEV;
272
273 return renesas_sdhi_probe(pdev, &renesas_sdhi_internal_dmac_dma_ops);
274}
275
276static const struct dev_pm_ops renesas_sdhi_internal_dmac_dev_pm_ops = {
277 SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
278 pm_runtime_force_resume)
279 SET_RUNTIME_PM_OPS(tmio_mmc_host_runtime_suspend,
280 tmio_mmc_host_runtime_resume,
281 NULL)
282};
283
284static struct platform_driver renesas_internal_dmac_sdhi_driver = {
285 .driver = {
286 .name = "renesas_sdhi_internal_dmac",
287 .pm = &renesas_sdhi_internal_dmac_dev_pm_ops,
288 .of_match_table = renesas_sdhi_internal_dmac_of_match,
289 },
290 .probe = renesas_sdhi_internal_dmac_probe,
291 .remove = renesas_sdhi_remove,
292};
293
294module_platform_driver(renesas_internal_dmac_sdhi_driver);
295
296MODULE_DESCRIPTION("Renesas SDHI driver for internal DMAC");
297MODULE_AUTHOR("Yoshihiro Shimoda");
298MODULE_LICENSE("GPL v2");