tjh.dev
Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
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linux
1/*
2 * Copyright (c) 2015, The Linux Foundation. All rights reserved.
3 *
4 * This software is licensed under the terms of the GNU General Public
5 * License version 2, as published by the Free Software Foundation, and
6 * may be copied, distributed, and modified under those terms.
7 *
8 * This program is distributed in the hope that it will be useful,
9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
12 */
13
14#ifndef __QCOM_CLK_ALPHA_PLL_H__
15#define __QCOM_CLK_ALPHA_PLL_H__
16
17#include <linux/clk-provider.h>
18#include "clk-regmap.h"
19
20/* Alpha PLL types */
21enum {
22 CLK_ALPHA_PLL_TYPE_DEFAULT,
23 CLK_ALPHA_PLL_TYPE_HUAYRA,
24 CLK_ALPHA_PLL_TYPE_BRAMMO,
25 CLK_ALPHA_PLL_TYPE_MAX,
26};
27
28enum {
29 PLL_OFF_L_VAL,
30 PLL_OFF_ALPHA_VAL,
31 PLL_OFF_ALPHA_VAL_U,
32 PLL_OFF_USER_CTL,
33 PLL_OFF_USER_CTL_U,
34 PLL_OFF_CONFIG_CTL,
35 PLL_OFF_CONFIG_CTL_U,
36 PLL_OFF_TEST_CTL,
37 PLL_OFF_TEST_CTL_U,
38 PLL_OFF_STATUS,
39 PLL_OFF_MAX_REGS
40};
41
42extern const u8 clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_MAX][PLL_OFF_MAX_REGS];
43
44struct pll_vco {
45 unsigned long min_freq;
46 unsigned long max_freq;
47 u32 val;
48};
49
50/**
51 * struct clk_alpha_pll - phase locked loop (PLL)
52 * @offset: base address of registers
53 * @vco_table: array of VCO settings
54 * @regs: alpha pll register map (see @clk_alpha_pll_regs)
55 * @clkr: regmap clock handle
56 */
57struct clk_alpha_pll {
58 u32 offset;
59 const u8 *regs;
60
61 const struct pll_vco *vco_table;
62 size_t num_vco;
63#define SUPPORTS_OFFLINE_REQ BIT(0)
64#define SUPPORTS_FSM_MODE BIT(2)
65#define SUPPORTS_DYNAMIC_UPDATE BIT(3)
66 u8 flags;
67
68 struct clk_regmap clkr;
69};
70
71/**
72 * struct clk_alpha_pll_postdiv - phase locked loop (PLL) post-divider
73 * @offset: base address of registers
74 * @regs: alpha pll register map (see @clk_alpha_pll_regs)
75 * @width: width of post-divider
76 * @clkr: regmap clock handle
77 */
78struct clk_alpha_pll_postdiv {
79 u32 offset;
80 u8 width;
81 const u8 *regs;
82
83 struct clk_regmap clkr;
84};
85
86struct alpha_pll_config {
87 u32 l;
88 u32 alpha;
89 u32 alpha_hi;
90 u32 config_ctl_val;
91 u32 config_ctl_hi_val;
92 u32 main_output_mask;
93 u32 aux_output_mask;
94 u32 aux2_output_mask;
95 u32 early_output_mask;
96 u32 alpha_en_mask;
97 u32 alpha_mode_mask;
98 u32 pre_div_val;
99 u32 pre_div_mask;
100 u32 post_div_val;
101 u32 post_div_mask;
102 u32 vco_val;
103 u32 vco_mask;
104};
105
106extern const struct clk_ops clk_alpha_pll_ops;
107extern const struct clk_ops clk_alpha_pll_hwfsm_ops;
108extern const struct clk_ops clk_alpha_pll_postdiv_ops;
109extern const struct clk_ops clk_alpha_pll_huayra_ops;
110extern const struct clk_ops clk_alpha_pll_postdiv_ro_ops;
111
112void clk_alpha_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap,
113 const struct alpha_pll_config *config);
114
115#endif