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linux
1/*
2 * TI TPS68470 PMIC operation region driver
3 *
4 * Copyright (C) 2017 Intel Corporation. All rights reserved.
5 *
6 * Author: Rajmohan Mani <rajmohan.mani@intel.com>
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License version
10 * 2 as published by the Free Software Foundation.
11 *
12 * This program is distributed "as is" WITHOUT ANY WARRANTY of any
13 * kind, whether express or implied; without even the implied warranty
14 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * Based on drivers/acpi/pmic/intel_pmic* drivers
18 */
19
20#include <linux/acpi.h>
21#include <linux/mfd/tps68470.h>
22#include <linux/init.h>
23#include <linux/platform_device.h>
24#include <linux/regmap.h>
25
26struct tps68470_pmic_table {
27 u32 address; /* operation region address */
28 u32 reg; /* corresponding register */
29 u32 bitmask; /* bit mask for power, clock */
30};
31
32#define TI_PMIC_POWER_OPREGION_ID 0xB0
33#define TI_PMIC_VR_VAL_OPREGION_ID 0xB1
34#define TI_PMIC_CLOCK_OPREGION_ID 0xB2
35#define TI_PMIC_CLKFREQ_OPREGION_ID 0xB3
36
37struct tps68470_pmic_opregion {
38 struct mutex lock;
39 struct regmap *regmap;
40};
41
42#define S_IO_I2C_EN (BIT(0) | BIT(1))
43
44static const struct tps68470_pmic_table power_table[] = {
45 {
46 .address = 0x00,
47 .reg = TPS68470_REG_S_I2C_CTL,
48 .bitmask = S_IO_I2C_EN,
49 /* S_I2C_CTL */
50 },
51 {
52 .address = 0x04,
53 .reg = TPS68470_REG_VCMCTL,
54 .bitmask = BIT(0),
55 /* VCMCTL */
56 },
57 {
58 .address = 0x08,
59 .reg = TPS68470_REG_VAUX1CTL,
60 .bitmask = BIT(0),
61 /* VAUX1_CTL */
62 },
63 {
64 .address = 0x0C,
65 .reg = TPS68470_REG_VAUX2CTL,
66 .bitmask = BIT(0),
67 /* VAUX2CTL */
68 },
69 {
70 .address = 0x10,
71 .reg = TPS68470_REG_VACTL,
72 .bitmask = BIT(0),
73 /* VACTL */
74 },
75 {
76 .address = 0x14,
77 .reg = TPS68470_REG_VDCTL,
78 .bitmask = BIT(0),
79 /* VDCTL */
80 },
81};
82
83/* Table to set voltage regulator value */
84static const struct tps68470_pmic_table vr_val_table[] = {
85 {
86 .address = 0x00,
87 .reg = TPS68470_REG_VSIOVAL,
88 .bitmask = TPS68470_VSIOVAL_IOVOLT_MASK,
89 /* TPS68470_REG_VSIOVAL */
90 },
91 {
92 .address = 0x04,
93 .reg = TPS68470_REG_VIOVAL,
94 .bitmask = TPS68470_VIOVAL_IOVOLT_MASK,
95 /* TPS68470_REG_VIOVAL */
96 },
97 {
98 .address = 0x08,
99 .reg = TPS68470_REG_VCMVAL,
100 .bitmask = TPS68470_VCMVAL_VCVOLT_MASK,
101 /* TPS68470_REG_VCMVAL */
102 },
103 {
104 .address = 0x0C,
105 .reg = TPS68470_REG_VAUX1VAL,
106 .bitmask = TPS68470_VAUX1VAL_AUX1VOLT_MASK,
107 /* TPS68470_REG_VAUX1VAL */
108 },
109 {
110 .address = 0x10,
111 .reg = TPS68470_REG_VAUX2VAL,
112 .bitmask = TPS68470_VAUX2VAL_AUX2VOLT_MASK,
113 /* TPS68470_REG_VAUX2VAL */
114 },
115 {
116 .address = 0x14,
117 .reg = TPS68470_REG_VAVAL,
118 .bitmask = TPS68470_VAVAL_AVOLT_MASK,
119 /* TPS68470_REG_VAVAL */
120 },
121 {
122 .address = 0x18,
123 .reg = TPS68470_REG_VDVAL,
124 .bitmask = TPS68470_VDVAL_DVOLT_MASK,
125 /* TPS68470_REG_VDVAL */
126 },
127};
128
129/* Table to configure clock frequency */
130static const struct tps68470_pmic_table clk_freq_table[] = {
131 {
132 .address = 0x00,
133 .reg = TPS68470_REG_POSTDIV2,
134 .bitmask = BIT(0) | BIT(1),
135 /* TPS68470_REG_POSTDIV2 */
136 },
137 {
138 .address = 0x04,
139 .reg = TPS68470_REG_BOOSTDIV,
140 .bitmask = 0x1F,
141 /* TPS68470_REG_BOOSTDIV */
142 },
143 {
144 .address = 0x08,
145 .reg = TPS68470_REG_BUCKDIV,
146 .bitmask = 0x0F,
147 /* TPS68470_REG_BUCKDIV */
148 },
149 {
150 .address = 0x0C,
151 .reg = TPS68470_REG_PLLSWR,
152 .bitmask = 0x13,
153 /* TPS68470_REG_PLLSWR */
154 },
155 {
156 .address = 0x10,
157 .reg = TPS68470_REG_XTALDIV,
158 .bitmask = 0xFF,
159 /* TPS68470_REG_XTALDIV */
160 },
161 {
162 .address = 0x14,
163 .reg = TPS68470_REG_PLLDIV,
164 .bitmask = 0xFF,
165 /* TPS68470_REG_PLLDIV */
166 },
167 {
168 .address = 0x18,
169 .reg = TPS68470_REG_POSTDIV,
170 .bitmask = 0x83,
171 /* TPS68470_REG_POSTDIV */
172 },
173};
174
175/* Table to configure and enable clocks */
176static const struct tps68470_pmic_table clk_table[] = {
177 {
178 .address = 0x00,
179 .reg = TPS68470_REG_PLLCTL,
180 .bitmask = 0xF5,
181 /* TPS68470_REG_PLLCTL */
182 },
183 {
184 .address = 0x04,
185 .reg = TPS68470_REG_PLLCTL2,
186 .bitmask = BIT(0),
187 /* TPS68470_REG_PLLCTL2 */
188 },
189 {
190 .address = 0x08,
191 .reg = TPS68470_REG_CLKCFG1,
192 .bitmask = TPS68470_CLKCFG1_MODE_A_MASK |
193 TPS68470_CLKCFG1_MODE_B_MASK,
194 /* TPS68470_REG_CLKCFG1 */
195 },
196 {
197 .address = 0x0C,
198 .reg = TPS68470_REG_CLKCFG2,
199 .bitmask = TPS68470_CLKCFG1_MODE_A_MASK |
200 TPS68470_CLKCFG1_MODE_B_MASK,
201 /* TPS68470_REG_CLKCFG2 */
202 },
203};
204
205static int pmic_get_reg_bit(u64 address,
206 const struct tps68470_pmic_table *table,
207 const unsigned int table_size, int *reg,
208 int *bitmask)
209{
210 u64 i;
211
212 i = address / 4;
213 if (i >= table_size)
214 return -ENOENT;
215
216 if (!reg || !bitmask)
217 return -EINVAL;
218
219 *reg = table[i].reg;
220 *bitmask = table[i].bitmask;
221
222 return 0;
223}
224
225static int tps68470_pmic_get_power(struct regmap *regmap, int reg,
226 int bitmask, u64 *value)
227{
228 unsigned int data;
229
230 if (regmap_read(regmap, reg, &data))
231 return -EIO;
232
233 *value = (data & bitmask) ? 1 : 0;
234 return 0;
235}
236
237static int tps68470_pmic_get_vr_val(struct regmap *regmap, int reg,
238 int bitmask, u64 *value)
239{
240 unsigned int data;
241
242 if (regmap_read(regmap, reg, &data))
243 return -EIO;
244
245 *value = data & bitmask;
246 return 0;
247}
248
249static int tps68470_pmic_get_clk(struct regmap *regmap, int reg,
250 int bitmask, u64 *value)
251{
252 unsigned int data;
253
254 if (regmap_read(regmap, reg, &data))
255 return -EIO;
256
257 *value = (data & bitmask) ? 1 : 0;
258 return 0;
259}
260
261static int tps68470_pmic_get_clk_freq(struct regmap *regmap, int reg,
262 int bitmask, u64 *value)
263{
264 unsigned int data;
265
266 if (regmap_read(regmap, reg, &data))
267 return -EIO;
268
269 *value = data & bitmask;
270 return 0;
271}
272
273static int ti_tps68470_regmap_update_bits(struct regmap *regmap, int reg,
274 int bitmask, u64 value)
275{
276 return regmap_update_bits(regmap, reg, bitmask, value);
277}
278
279static acpi_status tps68470_pmic_common_handler(u32 function,
280 acpi_physical_address address,
281 u32 bits, u64 *value,
282 void *region_context,
283 int (*get)(struct regmap *,
284 int, int, u64 *),
285 int (*update)(struct regmap *,
286 int, int, u64),
287 const struct tps68470_pmic_table *tbl,
288 unsigned int tbl_size)
289{
290 struct tps68470_pmic_opregion *opregion = region_context;
291 struct regmap *regmap = opregion->regmap;
292 int reg, ret, bitmask;
293
294 if (bits != 32)
295 return AE_BAD_PARAMETER;
296
297 ret = pmic_get_reg_bit(address, tbl, tbl_size, ®, &bitmask);
298 if (ret < 0)
299 return AE_BAD_PARAMETER;
300
301 if (function == ACPI_WRITE && *value > bitmask)
302 return AE_BAD_PARAMETER;
303
304 mutex_lock(&opregion->lock);
305
306 ret = (function == ACPI_READ) ?
307 get(regmap, reg, bitmask, value) :
308 update(regmap, reg, bitmask, *value);
309
310 mutex_unlock(&opregion->lock);
311
312 return ret ? AE_ERROR : AE_OK;
313}
314
315static acpi_status tps68470_pmic_cfreq_handler(u32 function,
316 acpi_physical_address address,
317 u32 bits, u64 *value,
318 void *handler_context,
319 void *region_context)
320{
321 return tps68470_pmic_common_handler(function, address, bits, value,
322 region_context,
323 tps68470_pmic_get_clk_freq,
324 ti_tps68470_regmap_update_bits,
325 clk_freq_table,
326 ARRAY_SIZE(clk_freq_table));
327}
328
329static acpi_status tps68470_pmic_clk_handler(u32 function,
330 acpi_physical_address address, u32 bits,
331 u64 *value, void *handler_context,
332 void *region_context)
333{
334 return tps68470_pmic_common_handler(function, address, bits, value,
335 region_context,
336 tps68470_pmic_get_clk,
337 ti_tps68470_regmap_update_bits,
338 clk_table,
339 ARRAY_SIZE(clk_table));
340}
341
342static acpi_status tps68470_pmic_vrval_handler(u32 function,
343 acpi_physical_address address,
344 u32 bits, u64 *value,
345 void *handler_context,
346 void *region_context)
347{
348 return tps68470_pmic_common_handler(function, address, bits, value,
349 region_context,
350 tps68470_pmic_get_vr_val,
351 ti_tps68470_regmap_update_bits,
352 vr_val_table,
353 ARRAY_SIZE(vr_val_table));
354}
355
356static acpi_status tps68470_pmic_pwr_handler(u32 function,
357 acpi_physical_address address,
358 u32 bits, u64 *value,
359 void *handler_context,
360 void *region_context)
361{
362 if (bits != 32)
363 return AE_BAD_PARAMETER;
364
365 /* set/clear for bit 0, bits 0 and 1 together */
366 if (function == ACPI_WRITE &&
367 !(*value == 0 || *value == 1 || *value == 3)) {
368 return AE_BAD_PARAMETER;
369 }
370
371 return tps68470_pmic_common_handler(function, address, bits, value,
372 region_context,
373 tps68470_pmic_get_power,
374 ti_tps68470_regmap_update_bits,
375 power_table,
376 ARRAY_SIZE(power_table));
377}
378
379static int tps68470_pmic_opregion_probe(struct platform_device *pdev)
380{
381 struct regmap *tps68470_regmap = dev_get_drvdata(pdev->dev.parent);
382 acpi_handle handle = ACPI_HANDLE(pdev->dev.parent);
383 struct device *dev = &pdev->dev;
384 struct tps68470_pmic_opregion *opregion;
385 acpi_status status;
386
387 if (!dev || !tps68470_regmap) {
388 dev_warn(dev, "dev or regmap is NULL\n");
389 return -EINVAL;
390 }
391
392 if (!handle) {
393 dev_warn(dev, "acpi handle is NULL\n");
394 return -ENODEV;
395 }
396
397 opregion = devm_kzalloc(dev, sizeof(*opregion), GFP_KERNEL);
398 if (!opregion)
399 return -ENOMEM;
400
401 mutex_init(&opregion->lock);
402 opregion->regmap = tps68470_regmap;
403
404 status = acpi_install_address_space_handler(handle,
405 TI_PMIC_POWER_OPREGION_ID,
406 tps68470_pmic_pwr_handler,
407 NULL, opregion);
408 if (ACPI_FAILURE(status))
409 goto out_mutex_destroy;
410
411 status = acpi_install_address_space_handler(handle,
412 TI_PMIC_VR_VAL_OPREGION_ID,
413 tps68470_pmic_vrval_handler,
414 NULL, opregion);
415 if (ACPI_FAILURE(status))
416 goto out_remove_power_handler;
417
418 status = acpi_install_address_space_handler(handle,
419 TI_PMIC_CLOCK_OPREGION_ID,
420 tps68470_pmic_clk_handler,
421 NULL, opregion);
422 if (ACPI_FAILURE(status))
423 goto out_remove_vr_val_handler;
424
425 status = acpi_install_address_space_handler(handle,
426 TI_PMIC_CLKFREQ_OPREGION_ID,
427 tps68470_pmic_cfreq_handler,
428 NULL, opregion);
429 if (ACPI_FAILURE(status))
430 goto out_remove_clk_handler;
431
432 return 0;
433
434out_remove_clk_handler:
435 acpi_remove_address_space_handler(handle, TI_PMIC_CLOCK_OPREGION_ID,
436 tps68470_pmic_clk_handler);
437out_remove_vr_val_handler:
438 acpi_remove_address_space_handler(handle, TI_PMIC_VR_VAL_OPREGION_ID,
439 tps68470_pmic_vrval_handler);
440out_remove_power_handler:
441 acpi_remove_address_space_handler(handle, TI_PMIC_POWER_OPREGION_ID,
442 tps68470_pmic_pwr_handler);
443out_mutex_destroy:
444 mutex_destroy(&opregion->lock);
445 return -ENODEV;
446}
447
448static struct platform_driver tps68470_pmic_opregion_driver = {
449 .probe = tps68470_pmic_opregion_probe,
450 .driver = {
451 .name = "tps68470_pmic_opregion",
452 },
453};
454
455builtin_platform_driver(tps68470_pmic_opregion_driver)