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1/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
2/*
3 * Copyright 2011 Tilera Corporation. All Rights Reserved.
4 *
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License
7 * as published by the Free Software Foundation, version 2.
8 *
9 * This program is distributed in the hope that it will be useful, but
10 * WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
12 * NON INFRINGEMENT. See the GNU General Public License for
13 * more details.
14 */
15
16#ifndef _ASM_TILE_CACHECTL_H
17#define _ASM_TILE_CACHECTL_H
18
19/*
20 * Options for cacheflush system call.
21 *
22 * The ICACHE flush is performed on all cores currently running the
23 * current process's address space. The intent is for user
24 * applications to be able to modify code, invoke the system call,
25 * then allow arbitrary other threads in the same address space to see
26 * the newly-modified code. Passing a length of CHIP_L1I_CACHE_SIZE()
27 * or more invalidates the entire icache on all cores in the address
28 * spaces. (Note: currently this option invalidates the entire icache
29 * regardless of the requested address and length, but we may choose
30 * to honor the arguments at some point.)
31 *
32 * Flush and invalidation of memory can normally be performed with the
33 * __insn_flush() and __insn_finv() instructions from userspace.
34 * The DCACHE option to the system call allows userspace
35 * to flush the entire L1+L2 data cache from the core. In this case,
36 * the address and length arguments are not used. The DCACHE flush is
37 * restricted to the current core, not all cores in the address space.
38 */
39#define ICACHE (1<<0) /* invalidate L1 instruction cache */
40#define DCACHE (1<<1) /* flush and invalidate data cache */
41#define BCACHE (ICACHE|DCACHE) /* flush both caches */
42
43#endif /* _ASM_TILE_CACHECTL_H */