tjh.dev
Linux kernel mirror (for testing)
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kernel
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linux
1/* SPDX-License-Identifier: GPL-2.0 */
2#ifdef __KERNEL__
3#ifndef _ASM_M32R_IRQ_H
4#define _ASM_M32R_IRQ_H
5
6
7#if defined(CONFIG_PLAT_USRV)
8/*
9 * IRQ definitions for M32700UT
10 * M32700 Chip: 64 interrupts
11 * ICU of M32700UT-on-board PLD: 32 interrupts cascaded to INT1# chip pin
12 */
13#define M32700UT_NUM_CPU_IRQ (64)
14#define M32700UT_NUM_PLD_IRQ (32)
15#define M32700UT_IRQ_BASE 0
16#define M32700UT_CPU_IRQ_BASE M32700UT_IRQ_BASE
17#define M32700UT_PLD_IRQ_BASE (M32700UT_CPU_IRQ_BASE + M32700UT_NUM_CPU_IRQ)
18
19#define NR_IRQS (M32700UT_NUM_CPU_IRQ + M32700UT_NUM_PLD_IRQ)
20#elif defined(CONFIG_PLAT_M32700UT)
21/*
22 * IRQ definitions for M32700UT(Rev.C) + M32R-LAN
23 * M32700 Chip: 64 interrupts
24 * ICU of M32700UT-on-board PLD: 32 interrupts cascaded to INT1# chip pin
25 * ICU of M32R-LCD-on-board PLD: 32 interrupts cascaded to INT2# chip pin
26 * ICU of M32R-LAN-on-board PLD: 32 interrupts cascaded to INT0# chip pin
27 */
28#define M32700UT_NUM_CPU_IRQ (64)
29#define M32700UT_NUM_PLD_IRQ (32)
30#define M32700UT_NUM_LCD_PLD_IRQ (32)
31#define M32700UT_NUM_LAN_PLD_IRQ (32)
32#define M32700UT_IRQ_BASE 0
33#define M32700UT_CPU_IRQ_BASE (M32700UT_IRQ_BASE)
34#define M32700UT_PLD_IRQ_BASE \
35 (M32700UT_CPU_IRQ_BASE + M32700UT_NUM_CPU_IRQ)
36#define M32700UT_LCD_PLD_IRQ_BASE \
37 (M32700UT_PLD_IRQ_BASE + M32700UT_NUM_PLD_IRQ)
38#define M32700UT_LAN_PLD_IRQ_BASE \
39 (M32700UT_LCD_PLD_IRQ_BASE + M32700UT_NUM_LCD_PLD_IRQ)
40
41#define NR_IRQS \
42 (M32700UT_NUM_CPU_IRQ + M32700UT_NUM_PLD_IRQ \
43 + M32700UT_NUM_LCD_PLD_IRQ + M32700UT_NUM_LAN_PLD_IRQ)
44#elif defined(CONFIG_PLAT_OPSPUT)
45/*
46 * IRQ definitions for OPSPUT + M32R-LAN
47 * OPSP Chip: 64 interrupts
48 * ICU of OPSPUT-on-board PLD: 32 interrupts cascaded to INT1# chip pin
49 * ICU of M32R-LCD-on-board PLD: 32 interrupts cascaded to INT2# chip pin
50 * ICU of M32R-LAN-on-board PLD: 32 interrupts cascaded to INT0# chip pin
51 */
52#define OPSPUT_NUM_CPU_IRQ (64)
53#define OPSPUT_NUM_PLD_IRQ (32)
54#define OPSPUT_NUM_LCD_PLD_IRQ (32)
55#define OPSPUT_NUM_LAN_PLD_IRQ (32)
56#define OPSPUT_IRQ_BASE 0
57#define OPSPUT_CPU_IRQ_BASE (OPSPUT_IRQ_BASE)
58#define OPSPUT_PLD_IRQ_BASE \
59 (OPSPUT_CPU_IRQ_BASE + OPSPUT_NUM_CPU_IRQ)
60#define OPSPUT_LCD_PLD_IRQ_BASE \
61 (OPSPUT_PLD_IRQ_BASE + OPSPUT_NUM_PLD_IRQ)
62#define OPSPUT_LAN_PLD_IRQ_BASE \
63 (OPSPUT_LCD_PLD_IRQ_BASE + OPSPUT_NUM_LCD_PLD_IRQ)
64
65#define NR_IRQS \
66 (OPSPUT_NUM_CPU_IRQ + OPSPUT_NUM_PLD_IRQ \
67 + OPSPUT_NUM_LCD_PLD_IRQ + OPSPUT_NUM_LAN_PLD_IRQ)
68
69#elif defined(CONFIG_PLAT_M32104UT)
70/*
71 * IRQ definitions for M32104UT
72 * M32104 Chip: 64 interrupts
73 * ICU of M32104UT-on-board PLD: 32 interrupts cascaded to INT1# chip pin
74 */
75#define M32104UT_NUM_CPU_IRQ (64)
76#define M32104UT_NUM_PLD_IRQ (32)
77#define M32104UT_IRQ_BASE 0
78#define M32104UT_CPU_IRQ_BASE M32104UT_IRQ_BASE
79#define M32104UT_PLD_IRQ_BASE (M32104UT_CPU_IRQ_BASE + M32104UT_NUM_CPU_IRQ)
80
81#define NR_IRQS \
82 (M32104UT_NUM_CPU_IRQ + M32104UT_NUM_PLD_IRQ)
83
84#else
85#define NR_IRQS 64
86#endif
87
88#define irq_canonicalize(irq) (irq)
89
90#endif /* _ASM_M32R_IRQ_H */
91#endif /* __KERNEL__ */