Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
tjh.dev
kernel
os
linux
1/*
2 * Based on arch/arm/include/asm/assembler.h, arch/arm/mm/proc-macros.S
3 *
4 * Copyright (C) 1996-2000 Russell King
5 * Copyright (C) 2012 ARM Ltd.
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program. If not, see <http://www.gnu.org/licenses/>.
18 */
19#ifndef __ASSEMBLY__
20#error "Only include this from assembly code"
21#endif
22
23#ifndef __ASM_ASSEMBLER_H
24#define __ASM_ASSEMBLER_H
25
26#include <asm/asm-offsets.h>
27#include <asm/cpufeature.h>
28#include <asm/debug-monitors.h>
29#include <asm/page.h>
30#include <asm/pgtable-hwdef.h>
31#include <asm/ptrace.h>
32#include <asm/thread_info.h>
33
34 .macro save_and_disable_daif, flags
35 mrs \flags, daif
36 msr daifset, #0xf
37 .endm
38
39 .macro disable_daif
40 msr daifset, #0xf
41 .endm
42
43 .macro enable_daif
44 msr daifclr, #0xf
45 .endm
46
47 .macro restore_daif, flags:req
48 msr daif, \flags
49 .endm
50
51 /* Only on aarch64 pstate, PSR_D_BIT is different for aarch32 */
52 .macro inherit_daif, pstate:req, tmp:req
53 and \tmp, \pstate, #(PSR_D_BIT | PSR_A_BIT | PSR_I_BIT | PSR_F_BIT)
54 msr daif, \tmp
55 .endm
56
57 /* IRQ is the lowest priority flag, unconditionally unmask the rest. */
58 .macro enable_da_f
59 msr daifclr, #(8 | 4 | 1)
60 .endm
61
62/*
63 * Enable and disable interrupts.
64 */
65 .macro disable_irq
66 msr daifset, #2
67 .endm
68
69 .macro enable_irq
70 msr daifclr, #2
71 .endm
72
73 .macro save_and_disable_irq, flags
74 mrs \flags, daif
75 msr daifset, #2
76 .endm
77
78 .macro restore_irq, flags
79 msr daif, \flags
80 .endm
81
82 .macro enable_dbg
83 msr daifclr, #8
84 .endm
85
86 .macro disable_step_tsk, flgs, tmp
87 tbz \flgs, #TIF_SINGLESTEP, 9990f
88 mrs \tmp, mdscr_el1
89 bic \tmp, \tmp, #DBG_MDSCR_SS
90 msr mdscr_el1, \tmp
91 isb // Synchronise with enable_dbg
929990:
93 .endm
94
95 /* call with daif masked */
96 .macro enable_step_tsk, flgs, tmp
97 tbz \flgs, #TIF_SINGLESTEP, 9990f
98 mrs \tmp, mdscr_el1
99 orr \tmp, \tmp, #DBG_MDSCR_SS
100 msr mdscr_el1, \tmp
1019990:
102 .endm
103
104/*
105 * SMP data memory barrier
106 */
107 .macro smp_dmb, opt
108 dmb \opt
109 .endm
110
111/*
112 * RAS Error Synchronization barrier
113 */
114 .macro esb
115 hint #16
116 .endm
117
118/*
119 * Value prediction barrier
120 */
121 .macro csdb
122 hint #20
123 .endm
124
125/*
126 * Sanitise a 64-bit bounded index wrt speculation, returning zero if out
127 * of bounds.
128 */
129 .macro mask_nospec64, idx, limit, tmp
130 sub \tmp, \idx, \limit
131 bic \tmp, \tmp, \idx
132 and \idx, \idx, \tmp, asr #63
133 csdb
134 .endm
135
136/*
137 * NOP sequence
138 */
139 .macro nops, num
140 .rept \num
141 nop
142 .endr
143 .endm
144
145/*
146 * Emit an entry into the exception table
147 */
148 .macro _asm_extable, from, to
149 .pushsection __ex_table, "a"
150 .align 3
151 .long (\from - .), (\to - .)
152 .popsection
153 .endm
154
155#define USER(l, x...) \
1569999: x; \
157 _asm_extable 9999b, l
158
159/*
160 * Register aliases.
161 */
162lr .req x30 // link register
163
164/*
165 * Vector entry
166 */
167 .macro ventry label
168 .align 7
169 b \label
170 .endm
171
172/*
173 * Select code when configured for BE.
174 */
175#ifdef CONFIG_CPU_BIG_ENDIAN
176#define CPU_BE(code...) code
177#else
178#define CPU_BE(code...)
179#endif
180
181/*
182 * Select code when configured for LE.
183 */
184#ifdef CONFIG_CPU_BIG_ENDIAN
185#define CPU_LE(code...)
186#else
187#define CPU_LE(code...) code
188#endif
189
190/*
191 * Define a macro that constructs a 64-bit value by concatenating two
192 * 32-bit registers. Note that on big endian systems the order of the
193 * registers is swapped.
194 */
195#ifndef CONFIG_CPU_BIG_ENDIAN
196 .macro regs_to_64, rd, lbits, hbits
197#else
198 .macro regs_to_64, rd, hbits, lbits
199#endif
200 orr \rd, \lbits, \hbits, lsl #32
201 .endm
202
203/*
204 * Pseudo-ops for PC-relative adr/ldr/str <reg>, <symbol> where
205 * <symbol> is within the range +/- 4 GB of the PC when running
206 * in core kernel context. In module context, a movz/movk sequence
207 * is used, since modules may be loaded far away from the kernel
208 * when KASLR is in effect.
209 */
210 /*
211 * @dst: destination register (64 bit wide)
212 * @sym: name of the symbol
213 */
214 .macro adr_l, dst, sym
215#ifndef MODULE
216 adrp \dst, \sym
217 add \dst, \dst, :lo12:\sym
218#else
219 movz \dst, #:abs_g3:\sym
220 movk \dst, #:abs_g2_nc:\sym
221 movk \dst, #:abs_g1_nc:\sym
222 movk \dst, #:abs_g0_nc:\sym
223#endif
224 .endm
225
226 /*
227 * @dst: destination register (32 or 64 bit wide)
228 * @sym: name of the symbol
229 * @tmp: optional 64-bit scratch register to be used if <dst> is a
230 * 32-bit wide register, in which case it cannot be used to hold
231 * the address
232 */
233 .macro ldr_l, dst, sym, tmp=
234#ifndef MODULE
235 .ifb \tmp
236 adrp \dst, \sym
237 ldr \dst, [\dst, :lo12:\sym]
238 .else
239 adrp \tmp, \sym
240 ldr \dst, [\tmp, :lo12:\sym]
241 .endif
242#else
243 .ifb \tmp
244 adr_l \dst, \sym
245 ldr \dst, [\dst]
246 .else
247 adr_l \tmp, \sym
248 ldr \dst, [\tmp]
249 .endif
250#endif
251 .endm
252
253 /*
254 * @src: source register (32 or 64 bit wide)
255 * @sym: name of the symbol
256 * @tmp: mandatory 64-bit scratch register to calculate the address
257 * while <src> needs to be preserved.
258 */
259 .macro str_l, src, sym, tmp
260#ifndef MODULE
261 adrp \tmp, \sym
262 str \src, [\tmp, :lo12:\sym]
263#else
264 adr_l \tmp, \sym
265 str \src, [\tmp]
266#endif
267 .endm
268
269 /*
270 * @dst: Result of per_cpu(sym, smp_processor_id()), can be SP for
271 * non-module code
272 * @sym: The name of the per-cpu variable
273 * @tmp: scratch register
274 */
275 .macro adr_this_cpu, dst, sym, tmp
276#ifndef MODULE
277 adrp \tmp, \sym
278 add \dst, \tmp, #:lo12:\sym
279#else
280 adr_l \dst, \sym
281#endif
282alternative_if_not ARM64_HAS_VIRT_HOST_EXTN
283 mrs \tmp, tpidr_el1
284alternative_else
285 mrs \tmp, tpidr_el2
286alternative_endif
287 add \dst, \dst, \tmp
288 .endm
289
290 /*
291 * @dst: Result of READ_ONCE(per_cpu(sym, smp_processor_id()))
292 * @sym: The name of the per-cpu variable
293 * @tmp: scratch register
294 */
295 .macro ldr_this_cpu dst, sym, tmp
296 adr_l \dst, \sym
297alternative_if_not ARM64_HAS_VIRT_HOST_EXTN
298 mrs \tmp, tpidr_el1
299alternative_else
300 mrs \tmp, tpidr_el2
301alternative_endif
302 ldr \dst, [\dst, \tmp]
303 .endm
304
305/*
306 * vma_vm_mm - get mm pointer from vma pointer (vma->vm_mm)
307 */
308 .macro vma_vm_mm, rd, rn
309 ldr \rd, [\rn, #VMA_VM_MM]
310 .endm
311
312/*
313 * mmid - get context id from mm pointer (mm->context.id)
314 */
315 .macro mmid, rd, rn
316 ldr \rd, [\rn, #MM_CONTEXT_ID]
317 .endm
318/*
319 * read_ctr - read CTR_EL0. If the system has mismatched
320 * cache line sizes, provide the system wide safe value
321 * from arm64_ftr_reg_ctrel0.sys_val
322 */
323 .macro read_ctr, reg
324alternative_if_not ARM64_MISMATCHED_CACHE_LINE_SIZE
325 mrs \reg, ctr_el0 // read CTR
326 nop
327alternative_else
328 ldr_l \reg, arm64_ftr_reg_ctrel0 + ARM64_FTR_SYSVAL
329alternative_endif
330 .endm
331
332
333/*
334 * raw_dcache_line_size - get the minimum D-cache line size on this CPU
335 * from the CTR register.
336 */
337 .macro raw_dcache_line_size, reg, tmp
338 mrs \tmp, ctr_el0 // read CTR
339 ubfm \tmp, \tmp, #16, #19 // cache line size encoding
340 mov \reg, #4 // bytes per word
341 lsl \reg, \reg, \tmp // actual cache line size
342 .endm
343
344/*
345 * dcache_line_size - get the safe D-cache line size across all CPUs
346 */
347 .macro dcache_line_size, reg, tmp
348 read_ctr \tmp
349 ubfm \tmp, \tmp, #16, #19 // cache line size encoding
350 mov \reg, #4 // bytes per word
351 lsl \reg, \reg, \tmp // actual cache line size
352 .endm
353
354/*
355 * raw_icache_line_size - get the minimum I-cache line size on this CPU
356 * from the CTR register.
357 */
358 .macro raw_icache_line_size, reg, tmp
359 mrs \tmp, ctr_el0 // read CTR
360 and \tmp, \tmp, #0xf // cache line size encoding
361 mov \reg, #4 // bytes per word
362 lsl \reg, \reg, \tmp // actual cache line size
363 .endm
364
365/*
366 * icache_line_size - get the safe I-cache line size across all CPUs
367 */
368 .macro icache_line_size, reg, tmp
369 read_ctr \tmp
370 and \tmp, \tmp, #0xf // cache line size encoding
371 mov \reg, #4 // bytes per word
372 lsl \reg, \reg, \tmp // actual cache line size
373 .endm
374
375/*
376 * tcr_set_idmap_t0sz - update TCR.T0SZ so that we can load the ID map
377 */
378 .macro tcr_set_idmap_t0sz, valreg, tmpreg
379 ldr_l \tmpreg, idmap_t0sz
380 bfi \valreg, \tmpreg, #TCR_T0SZ_OFFSET, #TCR_TxSZ_WIDTH
381 .endm
382
383/*
384 * tcr_compute_pa_size - set TCR.(I)PS to the highest supported
385 * ID_AA64MMFR0_EL1.PARange value
386 *
387 * tcr: register with the TCR_ELx value to be updated
388 * pos: IPS or PS bitfield position
389 * tmp{0,1}: temporary registers
390 */
391 .macro tcr_compute_pa_size, tcr, pos, tmp0, tmp1
392 mrs \tmp0, ID_AA64MMFR0_EL1
393 // Narrow PARange to fit the PS field in TCR_ELx
394 ubfx \tmp0, \tmp0, #ID_AA64MMFR0_PARANGE_SHIFT, #3
395 mov \tmp1, #ID_AA64MMFR0_PARANGE_MAX
396 cmp \tmp0, \tmp1
397 csel \tmp0, \tmp1, \tmp0, hi
398 bfi \tcr, \tmp0, \pos, #3
399 .endm
400
401/*
402 * Macro to perform a data cache maintenance for the interval
403 * [kaddr, kaddr + size)
404 *
405 * op: operation passed to dc instruction
406 * domain: domain used in dsb instruciton
407 * kaddr: starting virtual address of the region
408 * size: size of the region
409 * Corrupts: kaddr, size, tmp1, tmp2
410 */
411 .macro dcache_by_line_op op, domain, kaddr, size, tmp1, tmp2
412 dcache_line_size \tmp1, \tmp2
413 add \size, \kaddr, \size
414 sub \tmp2, \tmp1, #1
415 bic \kaddr, \kaddr, \tmp2
4169998:
417 .if (\op == cvau || \op == cvac)
418alternative_if_not ARM64_WORKAROUND_CLEAN_CACHE
419 dc \op, \kaddr
420alternative_else
421 dc civac, \kaddr
422alternative_endif
423 .elseif (\op == cvap)
424alternative_if ARM64_HAS_DCPOP
425 sys 3, c7, c12, 1, \kaddr // dc cvap
426alternative_else
427 dc cvac, \kaddr
428alternative_endif
429 .else
430 dc \op, \kaddr
431 .endif
432 add \kaddr, \kaddr, \tmp1
433 cmp \kaddr, \size
434 b.lo 9998b
435 dsb \domain
436 .endm
437
438/*
439 * Macro to perform an instruction cache maintenance for the interval
440 * [start, end)
441 *
442 * start, end: virtual addresses describing the region
443 * label: A label to branch to on user fault.
444 * Corrupts: tmp1, tmp2
445 */
446 .macro invalidate_icache_by_line start, end, tmp1, tmp2, label
447 icache_line_size \tmp1, \tmp2
448 sub \tmp2, \tmp1, #1
449 bic \tmp2, \start, \tmp2
4509997:
451USER(\label, ic ivau, \tmp2) // invalidate I line PoU
452 add \tmp2, \tmp2, \tmp1
453 cmp \tmp2, \end
454 b.lo 9997b
455 dsb ish
456 isb
457 .endm
458
459/*
460 * reset_pmuserenr_el0 - reset PMUSERENR_EL0 if PMUv3 present
461 */
462 .macro reset_pmuserenr_el0, tmpreg
463 mrs \tmpreg, id_aa64dfr0_el1 // Check ID_AA64DFR0_EL1 PMUVer
464 sbfx \tmpreg, \tmpreg, #8, #4
465 cmp \tmpreg, #1 // Skip if no PMU present
466 b.lt 9000f
467 msr pmuserenr_el0, xzr // Disable PMU access from EL0
4689000:
469 .endm
470
471/*
472 * copy_page - copy src to dest using temp registers t1-t8
473 */
474 .macro copy_page dest:req src:req t1:req t2:req t3:req t4:req t5:req t6:req t7:req t8:req
4759998: ldp \t1, \t2, [\src]
476 ldp \t3, \t4, [\src, #16]
477 ldp \t5, \t6, [\src, #32]
478 ldp \t7, \t8, [\src, #48]
479 add \src, \src, #64
480 stnp \t1, \t2, [\dest]
481 stnp \t3, \t4, [\dest, #16]
482 stnp \t5, \t6, [\dest, #32]
483 stnp \t7, \t8, [\dest, #48]
484 add \dest, \dest, #64
485 tst \src, #(PAGE_SIZE - 1)
486 b.ne 9998b
487 .endm
488
489/*
490 * Annotate a function as position independent, i.e., safe to be called before
491 * the kernel virtual mapping is activated.
492 */
493#define ENDPIPROC(x) \
494 .globl __pi_##x; \
495 .type __pi_##x, %function; \
496 .set __pi_##x, x; \
497 .size __pi_##x, . - x; \
498 ENDPROC(x)
499
500/*
501 * Annotate a function as being unsuitable for kprobes.
502 */
503#ifdef CONFIG_KPROBES
504#define NOKPROBE(x) \
505 .pushsection "_kprobe_blacklist", "aw"; \
506 .quad x; \
507 .popsection;
508#else
509#define NOKPROBE(x)
510#endif
511 /*
512 * Emit a 64-bit absolute little endian symbol reference in a way that
513 * ensures that it will be resolved at build time, even when building a
514 * PIE binary. This requires cooperation from the linker script, which
515 * must emit the lo32/hi32 halves individually.
516 */
517 .macro le64sym, sym
518 .long \sym\()_lo32
519 .long \sym\()_hi32
520 .endm
521
522 /*
523 * mov_q - move an immediate constant into a 64-bit register using
524 * between 2 and 4 movz/movk instructions (depending on the
525 * magnitude and sign of the operand)
526 */
527 .macro mov_q, reg, val
528 .if (((\val) >> 31) == 0 || ((\val) >> 31) == 0x1ffffffff)
529 movz \reg, :abs_g1_s:\val
530 .else
531 .if (((\val) >> 47) == 0 || ((\val) >> 47) == 0x1ffff)
532 movz \reg, :abs_g2_s:\val
533 .else
534 movz \reg, :abs_g3:\val
535 movk \reg, :abs_g2_nc:\val
536 .endif
537 movk \reg, :abs_g1_nc:\val
538 .endif
539 movk \reg, :abs_g0_nc:\val
540 .endm
541
542/*
543 * Return the current thread_info.
544 */
545 .macro get_thread_info, rd
546 mrs \rd, sp_el0
547 .endm
548
549/*
550 * Arrange a physical address in a TTBR register, taking care of 52-bit
551 * addresses.
552 *
553 * phys: physical address, preserved
554 * ttbr: returns the TTBR value
555 */
556 .macro phys_to_ttbr, ttbr, phys
557#ifdef CONFIG_ARM64_PA_BITS_52
558 orr \ttbr, \phys, \phys, lsr #46
559 and \ttbr, \ttbr, #TTBR_BADDR_MASK_52
560#else
561 mov \ttbr, \phys
562#endif
563 .endm
564
565 .macro phys_to_pte, pte, phys
566#ifdef CONFIG_ARM64_PA_BITS_52
567 /*
568 * We assume \phys is 64K aligned and this is guaranteed by only
569 * supporting this configuration with 64K pages.
570 */
571 orr \pte, \phys, \phys, lsr #36
572 and \pte, \pte, #PTE_ADDR_MASK
573#else
574 mov \pte, \phys
575#endif
576 .endm
577
578 .macro pte_to_phys, phys, pte
579#ifdef CONFIG_ARM64_PA_BITS_52
580 ubfiz \phys, \pte, #(48 - 16 - 12), #16
581 bfxil \phys, \pte, #16, #32
582 lsl \phys, \phys, #16
583#else
584 and \phys, \pte, #PTE_ADDR_MASK
585#endif
586 .endm
587
588/**
589 * Errata workaround prior to disable MMU. Insert an ISB immediately prior
590 * to executing the MSR that will change SCTLR_ELn[M] from a value of 1 to 0.
591 */
592 .macro pre_disable_mmu_workaround
593#ifdef CONFIG_QCOM_FALKOR_ERRATUM_E1041
594 isb
595#endif
596 .endm
597
598#endif /* __ASM_ASSEMBLER_H */