tjh.dev
Linux kernel mirror (for testing)
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linux
1/*
2 * Device Tree Source for UniPhier Pro4 SoC
3 *
4 * Copyright (C) 2015-2016 Socionext Inc.
5 * Author: Masahiro Yamada <yamada.masahiro@socionext.com>
6 *
7 * SPDX-License-Identifier: (GPL-2.0+ OR MIT)
8 */
9
10#include <dt-bindings/gpio/uniphier-gpio.h>
11
12/ {
13 compatible = "socionext,uniphier-pro4";
14 #address-cells = <1>;
15 #size-cells = <1>;
16
17 cpus {
18 #address-cells = <1>;
19 #size-cells = <0>;
20
21 cpu@0 {
22 device_type = "cpu";
23 compatible = "arm,cortex-a9";
24 reg = <0>;
25 enable-method = "psci";
26 next-level-cache = <&l2>;
27 };
28
29 cpu@1 {
30 device_type = "cpu";
31 compatible = "arm,cortex-a9";
32 reg = <1>;
33 enable-method = "psci";
34 next-level-cache = <&l2>;
35 };
36 };
37
38 psci {
39 compatible = "arm,psci-0.2";
40 method = "smc";
41 };
42
43 clocks {
44 refclk: ref {
45 compatible = "fixed-clock";
46 #clock-cells = <0>;
47 clock-frequency = <25000000>;
48 };
49
50 arm_timer_clk: arm-timer {
51 #clock-cells = <0>;
52 compatible = "fixed-clock";
53 clock-frequency = <50000000>;
54 };
55 };
56
57 soc {
58 compatible = "simple-bus";
59 #address-cells = <1>;
60 #size-cells = <1>;
61 ranges;
62 interrupt-parent = <&intc>;
63
64 l2: l2-cache@500c0000 {
65 compatible = "socionext,uniphier-system-cache";
66 reg = <0x500c0000 0x2000>, <0x503c0100 0x4>,
67 <0x506c0000 0x400>;
68 interrupts = <0 174 4>, <0 175 4>;
69 cache-unified;
70 cache-size = <(768 * 1024)>;
71 cache-sets = <256>;
72 cache-line-size = <128>;
73 cache-level = <2>;
74 };
75
76 serial0: serial@54006800 {
77 compatible = "socionext,uniphier-uart";
78 status = "disabled";
79 reg = <0x54006800 0x40>;
80 interrupts = <0 33 4>;
81 pinctrl-names = "default";
82 pinctrl-0 = <&pinctrl_uart0>;
83 clocks = <&peri_clk 0>;
84 resets = <&peri_rst 0>;
85 };
86
87 serial1: serial@54006900 {
88 compatible = "socionext,uniphier-uart";
89 status = "disabled";
90 reg = <0x54006900 0x40>;
91 interrupts = <0 35 4>;
92 pinctrl-names = "default";
93 pinctrl-0 = <&pinctrl_uart1>;
94 clocks = <&peri_clk 1>;
95 resets = <&peri_rst 1>;
96 };
97
98 serial2: serial@54006a00 {
99 compatible = "socionext,uniphier-uart";
100 status = "disabled";
101 reg = <0x54006a00 0x40>;
102 interrupts = <0 37 4>;
103 pinctrl-names = "default";
104 pinctrl-0 = <&pinctrl_uart2>;
105 clocks = <&peri_clk 2>;
106 resets = <&peri_rst 2>;
107 };
108
109 serial3: serial@54006b00 {
110 compatible = "socionext,uniphier-uart";
111 status = "disabled";
112 reg = <0x54006b00 0x40>;
113 interrupts = <0 177 4>;
114 pinctrl-names = "default";
115 pinctrl-0 = <&pinctrl_uart3>;
116 clocks = <&peri_clk 3>;
117 resets = <&peri_rst 3>;
118 };
119
120 gpio: gpio@55000000 {
121 compatible = "socionext,uniphier-gpio";
122 reg = <0x55000000 0x200>;
123 interrupt-parent = <&aidet>;
124 interrupt-controller;
125 #interrupt-cells = <2>;
126 gpio-controller;
127 #gpio-cells = <2>;
128 gpio-ranges = <&pinctrl 0 0 0>;
129 gpio-ranges-group-names = "gpio_range";
130 ngpios = <248>;
131 socionext,interrupt-ranges = <0 48 16>, <16 154 5>;
132 };
133
134 i2c0: i2c@58780000 {
135 compatible = "socionext,uniphier-fi2c";
136 status = "disabled";
137 reg = <0x58780000 0x80>;
138 #address-cells = <1>;
139 #size-cells = <0>;
140 interrupts = <0 41 4>;
141 pinctrl-names = "default";
142 pinctrl-0 = <&pinctrl_i2c0>;
143 clocks = <&peri_clk 4>;
144 resets = <&peri_rst 4>;
145 clock-frequency = <100000>;
146 };
147
148 i2c1: i2c@58781000 {
149 compatible = "socionext,uniphier-fi2c";
150 status = "disabled";
151 reg = <0x58781000 0x80>;
152 #address-cells = <1>;
153 #size-cells = <0>;
154 interrupts = <0 42 4>;
155 pinctrl-names = "default";
156 pinctrl-0 = <&pinctrl_i2c1>;
157 clocks = <&peri_clk 5>;
158 resets = <&peri_rst 5>;
159 clock-frequency = <100000>;
160 };
161
162 i2c2: i2c@58782000 {
163 compatible = "socionext,uniphier-fi2c";
164 status = "disabled";
165 reg = <0x58782000 0x80>;
166 #address-cells = <1>;
167 #size-cells = <0>;
168 interrupts = <0 43 4>;
169 pinctrl-names = "default";
170 pinctrl-0 = <&pinctrl_i2c2>;
171 clocks = <&peri_clk 6>;
172 resets = <&peri_rst 6>;
173 clock-frequency = <100000>;
174 };
175
176 i2c3: i2c@58783000 {
177 compatible = "socionext,uniphier-fi2c";
178 status = "disabled";
179 reg = <0x58783000 0x80>;
180 #address-cells = <1>;
181 #size-cells = <0>;
182 interrupts = <0 44 4>;
183 pinctrl-names = "default";
184 pinctrl-0 = <&pinctrl_i2c3>;
185 clocks = <&peri_clk 7>;
186 resets = <&peri_rst 7>;
187 clock-frequency = <100000>;
188 };
189
190 /* i2c4 does not exist */
191
192 /* chip-internal connection for DMD */
193 i2c5: i2c@58785000 {
194 compatible = "socionext,uniphier-fi2c";
195 reg = <0x58785000 0x80>;
196 #address-cells = <1>;
197 #size-cells = <0>;
198 interrupts = <0 25 4>;
199 clocks = <&peri_clk 9>;
200 resets = <&peri_rst 9>;
201 clock-frequency = <400000>;
202 };
203
204 /* chip-internal connection for HDMI */
205 i2c6: i2c@58786000 {
206 compatible = "socionext,uniphier-fi2c";
207 reg = <0x58786000 0x80>;
208 #address-cells = <1>;
209 #size-cells = <0>;
210 interrupts = <0 26 4>;
211 clocks = <&peri_clk 10>;
212 resets = <&peri_rst 10>;
213 clock-frequency = <400000>;
214 };
215
216 system_bus: system-bus@58c00000 {
217 compatible = "socionext,uniphier-system-bus";
218 status = "disabled";
219 reg = <0x58c00000 0x400>;
220 #address-cells = <2>;
221 #size-cells = <1>;
222 pinctrl-names = "default";
223 pinctrl-0 = <&pinctrl_system_bus>;
224 };
225
226 smpctrl@59801000 {
227 compatible = "socionext,uniphier-smpctrl";
228 reg = <0x59801000 0x400>;
229 };
230
231 mioctrl@59810000 {
232 compatible = "socionext,uniphier-pro4-mioctrl",
233 "simple-mfd", "syscon";
234 reg = <0x59810000 0x800>;
235
236 mio_clk: clock {
237 compatible = "socionext,uniphier-pro4-mio-clock";
238 #clock-cells = <1>;
239 };
240
241 mio_rst: reset {
242 compatible = "socionext,uniphier-pro4-mio-reset";
243 #reset-cells = <1>;
244 };
245 };
246
247 perictrl@59820000 {
248 compatible = "socionext,uniphier-pro4-perictrl",
249 "simple-mfd", "syscon";
250 reg = <0x59820000 0x200>;
251
252 peri_clk: clock {
253 compatible = "socionext,uniphier-pro4-peri-clock";
254 #clock-cells = <1>;
255 };
256
257 peri_rst: reset {
258 compatible = "socionext,uniphier-pro4-peri-reset";
259 #reset-cells = <1>;
260 };
261 };
262
263 usb2: usb@5a800100 {
264 compatible = "socionext,uniphier-ehci", "generic-ehci";
265 status = "disabled";
266 reg = <0x5a800100 0x100>;
267 interrupts = <0 80 4>;
268 pinctrl-names = "default";
269 pinctrl-0 = <&pinctrl_usb2>;
270 clocks = <&sys_clk 8>, <&mio_clk 7>, <&mio_clk 8>,
271 <&mio_clk 12>;
272 resets = <&sys_rst 8>, <&mio_rst 7>, <&mio_rst 8>,
273 <&mio_rst 12>;
274 has-transaction-translator;
275 };
276
277 usb3: usb@5a810100 {
278 compatible = "socionext,uniphier-ehci", "generic-ehci";
279 status = "disabled";
280 reg = <0x5a810100 0x100>;
281 interrupts = <0 81 4>;
282 pinctrl-names = "default";
283 pinctrl-0 = <&pinctrl_usb3>;
284 clocks = <&sys_clk 8>, <&mio_clk 7>, <&mio_clk 9>,
285 <&mio_clk 13>;
286 resets = <&sys_rst 8>, <&mio_rst 7>, <&mio_rst 9>,
287 <&mio_rst 13>;
288 has-transaction-translator;
289 };
290
291 soc-glue@5f800000 {
292 compatible = "socionext,uniphier-pro4-soc-glue",
293 "simple-mfd", "syscon";
294 reg = <0x5f800000 0x2000>;
295
296 pinctrl: pinctrl {
297 compatible = "socionext,uniphier-pro4-pinctrl";
298 };
299 };
300
301 soc-glue@5f900000 {
302 compatible = "socionext,uniphier-pro4-soc-glue-debug",
303 "simple-mfd";
304 #address-cells = <1>;
305 #size-cells = <1>;
306 ranges = <0 0x5f900000 0x2000>;
307
308 efuse@100 {
309 compatible = "socionext,uniphier-efuse";
310 reg = <0x100 0x28>;
311 };
312
313 efuse@130 {
314 compatible = "socionext,uniphier-efuse";
315 reg = <0x130 0x8>;
316 };
317
318 efuse@200 {
319 compatible = "socionext,uniphier-efuse";
320 reg = <0x200 0x14>;
321 };
322 };
323
324 aidet: aidet@5fc20000 {
325 compatible = "socionext,uniphier-pro4-aidet";
326 reg = <0x5fc20000 0x200>;
327 interrupt-controller;
328 #interrupt-cells = <2>;
329 };
330
331 timer@60000200 {
332 compatible = "arm,cortex-a9-global-timer";
333 reg = <0x60000200 0x20>;
334 interrupts = <1 11 0x304>;
335 clocks = <&arm_timer_clk>;
336 };
337
338 timer@60000600 {
339 compatible = "arm,cortex-a9-twd-timer";
340 reg = <0x60000600 0x20>;
341 interrupts = <1 13 0x304>;
342 clocks = <&arm_timer_clk>;
343 };
344
345 intc: interrupt-controller@60001000 {
346 compatible = "arm,cortex-a9-gic";
347 reg = <0x60001000 0x1000>,
348 <0x60000100 0x100>;
349 #interrupt-cells = <3>;
350 interrupt-controller;
351 };
352
353 sysctrl@61840000 {
354 compatible = "socionext,uniphier-pro4-sysctrl",
355 "simple-mfd", "syscon";
356 reg = <0x61840000 0x10000>;
357
358 sys_clk: clock {
359 compatible = "socionext,uniphier-pro4-clock";
360 #clock-cells = <1>;
361 };
362
363 sys_rst: reset {
364 compatible = "socionext,uniphier-pro4-reset";
365 #reset-cells = <1>;
366 };
367 };
368
369 nand: nand@68000000 {
370 compatible = "socionext,uniphier-denali-nand-v5a";
371 status = "disabled";
372 reg-names = "nand_data", "denali_reg";
373 reg = <0x68000000 0x20>, <0x68100000 0x1000>;
374 interrupts = <0 65 4>;
375 pinctrl-names = "default";
376 pinctrl-0 = <&pinctrl_nand>;
377 clocks = <&sys_clk 2>;
378 resets = <&sys_rst 2>;
379 };
380 };
381};
382
383#include "uniphier-pinctrl.dtsi"