tjh.dev
Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
1/*
2 * Copyright (C) 2017 Zodiac Inflight Innovations
3 *
4 * This file is dual-licensed: you can use it either under the terms
5 * of the GPL or the X11 license, at your option. Note that this dual
6 * licensing only applies to this file, and not this project as a
7 * whole.
8 *
9 * a) This file is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License
11 * version 2 as published by the Free Software Foundation.
12 *
13 * This file is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * Or, alternatively,
19 *
20 * b) Permission is hereby granted, free of charge, to any person
21 * obtaining a copy of this software and associated documentation
22 * files (the "Software"), to deal in the Software without
23 * restriction, including without limitation the rights to use,
24 * copy, modify, merge, publish, distribute, sublicense, and/or
25 * sell copies of the Software, and to permit persons to whom the
26 * Software is furnished to do so, subject to the following
27 * conditions:
28 *
29 * The above copyright notice and this permission notice shall be
30 * included in all copies or substantial portions of the Software.
31 *
32 * THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND,
33 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
34 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
35 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
36 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
37 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
38 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
39 * OTHER DEALINGS IN THE SOFTWARE.
40 */
41
42/dts-v1/;
43#include "imx51.dtsi"
44#include <dt-bindings/sound/fsl-imx-audmux.h>
45
46/ {
47 model = "ZII RDU1 Board";
48 compatible = "zii,imx51-rdu1", "fsl,imx51";
49
50 chosen {
51 stdout-path = &uart1;
52 };
53
54 aliases {
55 mdio-gpio0 = &mdio_gpio;
56 rtc0 = &ds1341;
57 };
58
59 clk_26M_osc: 26M_osc {
60 compatible = "fixed-clock";
61 #clock-cells = <0>;
62 clock-frequency = <26000000>;
63 };
64
65 clk_26M_osc_gate: 26M_gate {
66 compatible = "gpio-gate-clock";
67 pinctrl-names = "default";
68 pinctrl-0 = <&pinctrl_clk26mhz>;
69 clocks = <&clk_26M_osc>;
70 #clock-cells = <0>;
71 enable-gpios = <&gpio3 1 GPIO_ACTIVE_HIGH>;
72 };
73
74 clk_26M_usb: usbhost_gate {
75 compatible = "gpio-gate-clock";
76 pinctrl-names = "default";
77 pinctrl-0 = <&pinctrl_usbgate26mhz>;
78 clocks = <&clk_26M_osc_gate>;
79 #clock-cells = <0>;
80 enable-gpios = <&gpio1 19 GPIO_ACTIVE_LOW>;
81 };
82
83 clk_26M_snd: snd_gate {
84 compatible = "gpio-gate-clock";
85 pinctrl-names = "default";
86 pinctrl-0 = <&pinctrl_sndgate26mhz>;
87 clocks = <&clk_26M_osc_gate>;
88 #clock-cells = <0>;
89 enable-gpios = <&gpio4 26 GPIO_ACTIVE_LOW>;
90 };
91
92 reg_5p0v_main: regulator-5p0v-main {
93 compatible = "regulator-fixed";
94 regulator-name = "5V_MAIN";
95 regulator-min-microvolt = <5000000>;
96 regulator-max-microvolt = <5000000>;
97 regulator-always-on;
98 };
99
100 reg_3p3v: regulator-3p3v {
101 compatible = "regulator-fixed";
102 regulator-name = "3.3V";
103 regulator-min-microvolt = <3300000>;
104 regulator-max-microvolt = <3300000>;
105 regulator-always-on;
106 };
107
108 disp0 {
109 compatible = "fsl,imx-parallel-display";
110 pinctrl-names = "default";
111 pinctrl-0 = <&pinctrl_ipu_disp1>;
112
113 #address-cells = <1>;
114 #size-cells = <0>;
115
116 port@0 {
117 reg = <0>;
118
119 display_in: endpoint {
120 remote-endpoint = <&ipu_di0_disp1>;
121 };
122 };
123
124 port@1 {
125 reg = <1>;
126
127 display_out: endpoint {
128 remote-endpoint = <&panel_in>;
129 };
130 };
131 };
132
133 panel {
134 /* no compatible here, bootloader will patch in correct one */
135 pinctrl-names = "default";
136 pinctrl-0 = <&pinctrl_panel>;
137 power-supply = <®_3p3v>;
138 enable-gpios = <&gpio3 3 GPIO_ACTIVE_HIGH>;
139 status = "disabled";
140
141 port {
142 panel_in: endpoint {
143 remote-endpoint = <&display_out>;
144 };
145 };
146 };
147
148 i2c_gpio: i2c-gpio {
149 compatible = "i2c-gpio";
150 pinctrl-names = "default";
151 pinctrl-0 = <&pinctrl_swi2c>;
152 gpios = <&gpio1 2 GPIO_ACTIVE_HIGH>, /* sda */
153 <&gpio3 4 GPIO_ACTIVE_HIGH>; /* scl */
154 i2c-gpio,delay-us = <50>;
155 status = "okay";
156
157 #address-cells = <1>;
158 #size-cells = <0>;
159
160 sgtl5000: codec@a {
161 compatible = "fsl,sgtl5000";
162 reg = <0x0a>;
163 clocks = <&clk_26M_snd>;
164 VDDA-supply = <&vdig_reg>;
165 VDDIO-supply = <&vvideo_reg>;
166 #sound-dai-cells = <0>;
167 };
168 };
169
170 spi_gpio: spi-gpio {
171 compatible = "spi-gpio";
172 #address-cells = <1>;
173 #size-cells = <0>;
174 pinctrl-names = "default";
175 pinctrl-0 = <&pinctrl_gpiospi0>;
176 status = "okay";
177
178 gpio-sck = <&gpio4 15 GPIO_ACTIVE_HIGH>;
179 gpio-mosi = <&gpio4 12 GPIO_ACTIVE_HIGH>;
180 gpio-miso = <&gpio4 11 GPIO_ACTIVE_HIGH>;
181 num-chipselects = <1>;
182 cs-gpios = <&gpio4 14 GPIO_ACTIVE_HIGH>;
183
184 eeprom@0 {
185 compatible = "eeprom-93xx46";
186 reg = <0>;
187 spi-max-frequency = <1000000>;
188 spi-cs-high;
189 data-size = <8>;
190 };
191 };
192
193 mdio_gpio: mdio-gpio {
194 compatible = "virtual,mdio-gpio";
195 pinctrl-names = "default";
196 pinctrl-0 = <&pinctrl_swmdio>;
197 gpios = <&gpio3 26 GPIO_ACTIVE_HIGH>, /* mdc */
198 <&gpio3 25 GPIO_ACTIVE_HIGH>; /* mdio */
199
200 #address-cells = <1>;
201 #size-cells = <0>;
202
203 switch@0 {
204 compatible = "marvell,mv88e6085";
205 #address-cells = <1>;
206 #size-cells = <0>;
207 reg = <0>;
208 dsa,member = <0 0>;
209
210 ports {
211 #address-cells = <1>;
212 #size-cells = <0>;
213
214 port@0 {
215 reg = <0>;
216 label = "cpu";
217 ethernet = <&fec>;
218
219 fixed-link {
220 speed = <100>;
221 full-duplex;
222 };
223 };
224
225 port@1 {
226 reg = <1>;
227 label = "netaux";
228 };
229
230 port@3 {
231 reg = <3>;
232 label = "netright";
233 };
234
235 port@4 {
236 reg = <4>;
237 label = "netleft";
238 };
239 };
240 };
241 };
242
243 sound {
244 compatible = "simple-audio-card";
245 simple-audio-card,name = "Front";
246 simple-audio-card,format = "i2s";
247 simple-audio-card,bitclock-master = <&sound_codec>;
248 simple-audio-card,frame-master = <&sound_codec>;
249 simple-audio-card,widgets =
250 "Headphone", "Headphone Jack";
251 simple-audio-card,routing =
252 "Headphone Jack", "HPLEFT",
253 "Headphone Jack", "HPRIGHT";
254 simple-audio-card,aux-devs = <&hpa1>;
255
256 sound_cpu: simple-audio-card,cpu {
257 sound-dai = <&ssi2>;
258 };
259
260 sound_codec: simple-audio-card,codec {
261 sound-dai = <&sgtl5000>;
262 clocks = <&clk_26M_snd>;
263 };
264 };
265
266 usbh1phy: usbphy1 {
267 compatible = "usb-nop-xceiv";
268 pinctrl-names = "default";
269 pinctrl-0 = <&pinctrl_usbh1phy>;
270 clocks = <&clk_26M_usb>;
271 clock-names = "main_clk";
272 reset-gpios = <&gpio4 8 GPIO_ACTIVE_LOW>;
273 vcc-supply = <&vusb_reg>;
274 #phy-cells = <0>;
275 };
276
277 usbh2phy: usbphy2 {
278 compatible = "usb-nop-xceiv";
279 pinctrl-names = "default";
280 pinctrl-0 = <&pinctrl_usbh2phy>;
281 clocks = <&clk_26M_usb>;
282 clock-names = "main_clk";
283 reset-gpios = <&gpio4 7 GPIO_ACTIVE_LOW>;
284 vcc-supply = <&vusb_reg>;
285 #phy-cells = <0>;
286 };
287};
288
289&audmux {
290 pinctrl-names = "default";
291 pinctrl-0 = <&pinctrl_audmux>;
292 status = "okay";
293
294 ssi2 {
295 fsl,audmux-port = <1>;
296 fsl,port-config = <
297 (IMX_AUDMUX_V2_PTCR_SYN |
298 IMX_AUDMUX_V2_PTCR_TFSEL(2) |
299 IMX_AUDMUX_V2_PTCR_TCSEL(2) |
300 IMX_AUDMUX_V2_PTCR_TFSDIR |
301 IMX_AUDMUX_V2_PTCR_TCLKDIR)
302 IMX_AUDMUX_V2_PDCR_RXDSEL(2)
303 >;
304 };
305
306 aud3 {
307 fsl,audmux-port = <2>;
308 fsl,port-config = <
309 IMX_AUDMUX_V2_PTCR_SYN
310 IMX_AUDMUX_V2_PDCR_RXDSEL(1)
311 >;
312 };
313};
314
315&cpu {
316 cpu-supply = <&sw1_reg>;
317};
318
319&ecspi1 {
320 pinctrl-names = "default";
321 pinctrl-0 = <&pinctrl_ecspi1>;
322 cs-gpios = <&gpio4 24 GPIO_ACTIVE_HIGH>,
323 <&gpio4 25 GPIO_ACTIVE_LOW>;
324 status = "okay";
325
326 pmic@0 {
327 compatible = "fsl,mc13892";
328 pinctrl-names = "default";
329 pinctrl-0 = <&pinctrl_pmic>;
330 spi-max-frequency = <6000000>;
331 spi-cs-high;
332 reg = <0>;
333 interrupt-parent = <&gpio1>;
334 interrupts = <8 IRQ_TYPE_LEVEL_HIGH>;
335 fsl,mc13xxx-uses-adc;
336
337 regulators {
338 sw1_reg: sw1 {
339 regulator-min-microvolt = <600000>;
340 regulator-max-microvolt = <1375000>;
341 regulator-boot-on;
342 regulator-always-on;
343 };
344
345 sw2_reg: sw2 {
346 regulator-min-microvolt = <900000>;
347 regulator-max-microvolt = <1850000>;
348 regulator-boot-on;
349 regulator-always-on;
350 };
351
352 sw3_reg: sw3 {
353 regulator-min-microvolt = <1100000>;
354 regulator-max-microvolt = <1850000>;
355 regulator-boot-on;
356 regulator-always-on;
357 };
358
359 sw4_reg: sw4 {
360 regulator-min-microvolt = <1100000>;
361 regulator-max-microvolt = <1850000>;
362 regulator-boot-on;
363 regulator-always-on;
364 };
365
366 vpll_reg: vpll {
367 regulator-min-microvolt = <1050000>;
368 regulator-max-microvolt = <1800000>;
369 regulator-boot-on;
370 regulator-always-on;
371 };
372
373 vdig_reg: vdig {
374 regulator-min-microvolt = <1650000>;
375 regulator-max-microvolt = <1650000>;
376 regulator-boot-on;
377 };
378
379 vsd_reg: vsd {
380 regulator-min-microvolt = <1800000>;
381 regulator-max-microvolt = <3150000>;
382 };
383
384 vusb_reg: vusb {
385 regulator-always-on;
386 };
387
388 vusb2_reg: vusb2 {
389 regulator-min-microvolt = <2400000>;
390 regulator-max-microvolt = <2775000>;
391 regulator-boot-on;
392 regulator-always-on;
393 };
394
395 vvideo_reg: vvideo {
396 regulator-min-microvolt = <2775000>;
397 regulator-max-microvolt = <2775000>;
398 };
399
400 vaudio_reg: vaudio {
401 regulator-min-microvolt = <2300000>;
402 regulator-max-microvolt = <3000000>;
403 };
404
405 vcam_reg: vcam {
406 regulator-min-microvolt = <2500000>;
407 regulator-max-microvolt = <3000000>;
408 };
409
410 vgen1_reg: vgen1 {
411 regulator-min-microvolt = <1200000>;
412 regulator-max-microvolt = <1200000>;
413 };
414
415 vgen2_reg: vgen2 {
416 regulator-min-microvolt = <1200000>;
417 regulator-max-microvolt = <3150000>;
418 regulator-always-on;
419 };
420
421 vgen3_reg: vgen3 {
422 regulator-min-microvolt = <1800000>;
423 regulator-max-microvolt = <2900000>;
424 regulator-always-on;
425 };
426 };
427
428 leds {
429 #address-cells = <1>;
430 #size-cells = <0>;
431 led-control = <0x0 0x0 0x3f83f8 0x0>;
432
433 sysled0@3 {
434 reg = <3>;
435 label = "system:green:status";
436 linux,default-trigger = "default-on";
437 };
438
439 sysled1@4 {
440 reg = <4>;
441 label = "system:green:act";
442 linux,default-trigger = "heartbeat";
443 };
444 };
445 };
446
447 flash@1 {
448 #address-cells = <1>;
449 #size-cells = <1>;
450 compatible = "atmel,at45db642d", "atmel,at45", "atmel,dataflash";
451 spi-max-frequency = <25000000>;
452 reg = <1>;
453 };
454};
455
456&esdhc1 {
457 pinctrl-names = "default";
458 pinctrl-0 = <&pinctrl_esdhc1>;
459 bus-width = <4>;
460 non-removable;
461 status = "okay";
462};
463
464&fec {
465 pinctrl-names = "default";
466 pinctrl-0 = <&pinctrl_fec>;
467 phy-mode = "mii";
468 phy-reset-gpios = <&gpio2 14 GPIO_ACTIVE_LOW>;
469 phy-supply = <&vgen3_reg>;
470 status = "okay";
471};
472
473&i2c2 {
474 pinctrl-names = "default";
475 pinctrl-0 = <&pinctrl_i2c2>;
476 status = "okay";
477
478 eeprom@50 {
479 compatible = "atmel,24c04";
480 pagesize = <16>;
481 reg = <0x50>;
482 };
483
484 hpa1: amp@60 {
485 compatible = "ti,tpa6130a2";
486 reg = <0x60>;
487 pinctrl-names = "default";
488 pinctrl-0 = <&pinctrl_ampgpio>;
489 power-gpio = <&gpio1 9 GPIO_ACTIVE_HIGH>;
490 Vdd-supply = <®_3p3v>;
491 };
492
493 ds1341: rtc@68 {
494 compatible = "maxim,ds1341";
495 reg = <0x68>;
496 };
497
498 /* touch nodes default disabled, bootloader will enable the right one */
499
500 touchscreen@4b {
501 compatible = "atmel,maxtouch";
502 reg = <0x4b>;
503 pinctrl-names = "default";
504 pinctrl-0 = <&pinctrl_ts>;
505 interrupt-parent = <&gpio3>;
506 interrupts = <12 IRQ_TYPE_LEVEL_LOW>;
507 status = "disabled";
508 };
509
510 touchscreen@4c {
511 compatible = "atmel,maxtouch";
512 reg = <0x4c>;
513 pinctrl-names = "default";
514 pinctrl-0 = <&pinctrl_ts>;
515 interrupt-parent = <&gpio3>;
516 interrupts = <12 IRQ_TYPE_LEVEL_LOW>;
517 status = "disabled";
518 };
519
520 touchscreen@20 {
521 compatible = "syna,rmi4_i2c";
522 reg = <0x20>;
523 pinctrl-names = "default";
524 pinctrl-0 = <&pinctrl_ts>;
525 interrupt-parent = <&gpio3>;
526 interrupts = <12 IRQ_TYPE_LEVEL_LOW>;
527 status = "disabled";
528
529 #address-cells = <1>;
530 #size-cells = <0>;
531
532 rmi4-f01@1 {
533 reg = <0x1>;
534 syna,nosleep-mode = <2>;
535 };
536
537 rmi4-f11@11 {
538 reg = <0x11>;
539 touch-inverted-y;
540 touch-swapped-x-y;
541 syna,sensor-type = <1>;
542 };
543 };
544
545};
546
547&ipu_di0_disp1 {
548 remote-endpoint = <&display_in>;
549};
550
551&ssi2 {
552 status = "okay";
553};
554
555&uart1 {
556 pinctrl-names = "default";
557 pinctrl-0 = <&pinctrl_uart1>;
558 status = "okay";
559};
560
561&uart2 {
562 pinctrl-names = "default";
563 pinctrl-0 = <&pinctrl_uart2>;
564 status = "okay";
565};
566
567&uart3 {
568 pinctrl-names = "default";
569 pinctrl-0 = <&pinctrl_uart3>;
570 status = "okay";
571};
572
573&usbh1 {
574 pinctrl-names = "default";
575 pinctrl-0 = <&pinctrl_usbh1>;
576 dr_mode = "host";
577 phy_type = "ulpi";
578 fsl,usbphy = <&usbh1phy>;
579 disable-over-current;
580 vbus-supply = <®_5p0v_main>;
581 status = "okay";
582};
583
584&usbh2 {
585 pinctrl-names = "default";
586 pinctrl-0 = <&pinctrl_usbh2>;
587 dr_mode = "host";
588 phy_type = "ulpi";
589 fsl,usbphy = <&usbh2phy>;
590 disable-over-current;
591 vbus-supply = <®_5p0v_main>;
592 status = "okay";
593};
594
595&usbphy0 {
596 vcc-supply = <&vusb_reg>;
597};
598
599&usbotg {
600 dr_mode = "host";
601 disable-over-current;
602 phy_type = "utmi_wide";
603 vbus-supply = <®_5p0v_main>;
604 status = "okay";
605};
606
607&iomuxc {
608 pinctrl_ampgpio: ampgpiogrp {
609 fsl,pins = <
610 MX51_PAD_GPIO1_9__GPIO1_9 0x5e
611 >;
612 };
613
614 pinctrl_audmux: audmuxgrp {
615 fsl,pins = <
616 MX51_PAD_AUD3_BB_TXD__AUD3_TXD 0xa5
617 MX51_PAD_AUD3_BB_RXD__AUD3_RXD 0x85
618 MX51_PAD_AUD3_BB_CK__AUD3_TXC 0xa5
619 MX51_PAD_AUD3_BB_FS__AUD3_TXFS 0x85
620 >;
621 };
622
623 pinctrl_clk26mhz: clk26mhzgrp {
624 fsl,pins = <
625 MX51_PAD_DI1_PIN12__GPIO3_1 0x85
626 >;
627 };
628
629 pinctrl_ecspi1: ecspi1grp {
630 fsl,pins = <
631 MX51_PAD_CSPI1_MISO__ECSPI1_MISO 0x185
632 MX51_PAD_CSPI1_MOSI__ECSPI1_MOSI 0x185
633 MX51_PAD_CSPI1_SCLK__ECSPI1_SCLK 0x185
634 MX51_PAD_CSPI1_SS0__GPIO4_24 0x85
635 MX51_PAD_CSPI1_SS1__GPIO4_25 0x85
636 >;
637 };
638
639 pinctrl_esdhc1: esdhc1grp {
640 fsl,pins = <
641 MX51_PAD_SD1_CMD__SD1_CMD 0x400020d5
642 MX51_PAD_SD1_CLK__SD1_CLK 0x20d5
643 MX51_PAD_SD1_DATA0__SD1_DATA0 0x20d5
644 MX51_PAD_SD1_DATA1__SD1_DATA1 0x20d5
645 MX51_PAD_SD1_DATA2__SD1_DATA2 0x20d5
646 MX51_PAD_SD1_DATA3__SD1_DATA3 0x20d5
647 >;
648 };
649
650 pinctrl_fec: fecgrp {
651 fsl,pins = <
652 MX51_PAD_EIM_EB2__FEC_MDIO 0x1f5
653 MX51_PAD_NANDF_D9__FEC_RDATA0 0x2180
654 MX51_PAD_EIM_EB3__FEC_RDATA1 0x180
655 MX51_PAD_EIM_CS2__FEC_RDATA2 0x180
656 MX51_PAD_EIM_CS3__FEC_RDATA3 0x180
657 MX51_PAD_EIM_CS4__FEC_RX_ER 0x180
658 MX51_PAD_NANDF_D11__FEC_RX_DV 0x2084
659 MX51_PAD_EIM_CS5__FEC_CRS 0x180
660 MX51_PAD_NANDF_RB2__FEC_COL 0x2180
661 MX51_PAD_NANDF_RB3__FEC_RX_CLK 0x2180
662 MX51_PAD_NANDF_CS2__FEC_TX_ER 0x2004
663 MX51_PAD_NANDF_CS3__FEC_MDC 0x2004
664 MX51_PAD_NANDF_D8__FEC_TDATA0 0x2180
665 MX51_PAD_NANDF_CS4__FEC_TDATA1 0x2004
666 MX51_PAD_NANDF_CS5__FEC_TDATA2 0x2004
667 MX51_PAD_NANDF_CS6__FEC_TDATA3 0x2004
668 MX51_PAD_DISP2_DAT9__FEC_TX_EN 0x2004
669 MX51_PAD_DISP2_DAT13__FEC_TX_CLK 0x2180
670 MX51_PAD_EIM_A20__GPIO2_14 0x85
671 >;
672 };
673
674 pinctrl_gpiospi0: gpiospi0grp {
675 fsl,pins = <
676 MX51_PAD_CSI2_D18__GPIO4_11 0x85
677 MX51_PAD_CSI2_D19__GPIO4_12 0x85
678 MX51_PAD_CSI2_HSYNC__GPIO4_14 0x85
679 MX51_PAD_CSI2_PIXCLK__GPIO4_15 0x85
680 >;
681 };
682
683 pinctrl_i2c2: i2c2grp {
684 fsl,pins = <
685 MX51_PAD_KEY_COL4__I2C2_SCL 0x400001ed
686 MX51_PAD_KEY_COL5__I2C2_SDA 0x400001ed
687 >;
688 };
689
690 pinctrl_ipu_disp1: ipudisp1grp {
691 fsl,pins = <
692 MX51_PAD_DISP1_DAT0__DISP1_DAT0 0x5
693 MX51_PAD_DISP1_DAT1__DISP1_DAT1 0x5
694 MX51_PAD_DISP1_DAT2__DISP1_DAT2 0x5
695 MX51_PAD_DISP1_DAT3__DISP1_DAT3 0x5
696 MX51_PAD_DISP1_DAT4__DISP1_DAT4 0x5
697 MX51_PAD_DISP1_DAT5__DISP1_DAT5 0x5
698 MX51_PAD_DISP1_DAT6__DISP1_DAT6 0x5
699 MX51_PAD_DISP1_DAT7__DISP1_DAT7 0x5
700 MX51_PAD_DISP1_DAT8__DISP1_DAT8 0x5
701 MX51_PAD_DISP1_DAT9__DISP1_DAT9 0x5
702 MX51_PAD_DISP1_DAT10__DISP1_DAT10 0x5
703 MX51_PAD_DISP1_DAT11__DISP1_DAT11 0x5
704 MX51_PAD_DISP1_DAT12__DISP1_DAT12 0x5
705 MX51_PAD_DISP1_DAT13__DISP1_DAT13 0x5
706 MX51_PAD_DISP1_DAT14__DISP1_DAT14 0x5
707 MX51_PAD_DISP1_DAT15__DISP1_DAT15 0x5
708 MX51_PAD_DISP1_DAT16__DISP1_DAT16 0x5
709 MX51_PAD_DISP1_DAT17__DISP1_DAT17 0x5
710 MX51_PAD_DISP1_DAT18__DISP1_DAT18 0x5
711 MX51_PAD_DISP1_DAT19__DISP1_DAT19 0x5
712 MX51_PAD_DISP1_DAT20__DISP1_DAT20 0x5
713 MX51_PAD_DISP1_DAT21__DISP1_DAT21 0x5
714 MX51_PAD_DISP1_DAT22__DISP1_DAT22 0x5
715 MX51_PAD_DISP1_DAT23__DISP1_DAT23 0x5
716 MX51_PAD_DI1_PIN2__DI1_PIN2 0x5
717 MX51_PAD_DI1_PIN3__DI1_PIN3 0x5
718 MX51_PAD_DI2_DISP_CLK__DI2_DISP_CLK 0x5
719 >;
720 };
721
722 pinctrl_panel: panelgrp {
723 fsl,pins = <
724 MX51_PAD_DI1_D0_CS__GPIO3_3 0x85
725 >;
726 };
727
728 pinctrl_pmic: pmicgrp {
729 fsl,pins = <
730 MX51_PAD_GPIO1_4__GPIO1_4 0x1e0
731 MX51_PAD_GPIO1_8__GPIO1_8 0x21e2
732 >;
733 };
734
735 pinctrl_sndgate26mhz: sndgate26mhzgrp {
736 fsl,pins = <
737 MX51_PAD_CSPI1_RDY__GPIO4_26 0x85
738 >;
739 };
740
741 pinctrl_swi2c: swi2cgrp {
742 fsl,pins = <
743 MX51_PAD_GPIO1_2__GPIO1_2 0xc5
744 MX51_PAD_DI1_D1_CS__GPIO3_4 0x400001f5
745 >;
746 };
747
748 pinctrl_swmdio: swmdiogrp {
749 fsl,pins = <
750 MX51_PAD_NANDF_D14__GPIO3_26 0x21e6
751 MX51_PAD_NANDF_D15__GPIO3_25 0x21e6
752 >;
753 };
754
755 pinctrl_ts: tsgrp {
756 fsl,pins = <
757 MX51_PAD_CSI1_D8__GPIO3_12 0x85
758 MX51_PAD_CSI1_D9__GPIO3_13 0x85
759 >;
760 };
761
762 pinctrl_uart1: uart1grp {
763 fsl,pins = <
764 MX51_PAD_UART1_RXD__UART1_RXD 0x1c5
765 MX51_PAD_UART1_TXD__UART1_TXD 0x1c5
766 MX51_PAD_UART1_RTS__UART1_RTS 0x1c4
767 MX51_PAD_UART1_CTS__UART1_CTS 0x1c4
768 >;
769 };
770
771 pinctrl_uart2: uart2grp {
772 fsl,pins = <
773 MX51_PAD_UART2_RXD__UART2_RXD 0xc5
774 MX51_PAD_UART2_TXD__UART2_TXD 0xc5
775 >;
776 };
777
778 pinctrl_uart3: uart3grp {
779 fsl,pins = <
780 MX51_PAD_EIM_D25__UART3_RXD 0x1c5
781 MX51_PAD_EIM_D26__UART3_TXD 0x1c5
782 >;
783 };
784
785 pinctrl_usbgate26mhz: usbgate26mhzgrp {
786 fsl,pins = <
787 MX51_PAD_DISP2_DAT6__GPIO1_19 0x85
788 >;
789 };
790
791 pinctrl_usbh1: usbh1grp {
792 fsl,pins = <
793 MX51_PAD_USBH1_STP__USBH1_STP 0x0
794 MX51_PAD_USBH1_CLK__USBH1_CLK 0x0
795 MX51_PAD_USBH1_DIR__USBH1_DIR 0x0
796 MX51_PAD_USBH1_NXT__USBH1_NXT 0x0
797 MX51_PAD_USBH1_DATA0__USBH1_DATA0 0x0
798 MX51_PAD_USBH1_DATA1__USBH1_DATA1 0x0
799 MX51_PAD_USBH1_DATA2__USBH1_DATA2 0x0
800 MX51_PAD_USBH1_DATA3__USBH1_DATA3 0x0
801 MX51_PAD_USBH1_DATA4__USBH1_DATA4 0x0
802 MX51_PAD_USBH1_DATA5__USBH1_DATA5 0x0
803 MX51_PAD_USBH1_DATA6__USBH1_DATA6 0x0
804 MX51_PAD_USBH1_DATA7__USBH1_DATA7 0x0
805 >;
806 };
807
808 pinctrl_usbh1phy: usbh1phygrp {
809 fsl,pins = <
810 MX51_PAD_NANDF_D0__GPIO4_8 0x85
811 >;
812 };
813
814 pinctrl_usbh2: usbh2grp {
815 fsl,pins = <
816 MX51_PAD_EIM_A26__USBH2_STP 0x0
817 MX51_PAD_EIM_A24__USBH2_CLK 0x0
818 MX51_PAD_EIM_A25__USBH2_DIR 0x0
819 MX51_PAD_EIM_A27__USBH2_NXT 0x0
820 MX51_PAD_EIM_D16__USBH2_DATA0 0x0
821 MX51_PAD_EIM_D17__USBH2_DATA1 0x0
822 MX51_PAD_EIM_D18__USBH2_DATA2 0x0
823 MX51_PAD_EIM_D19__USBH2_DATA3 0x0
824 MX51_PAD_EIM_D20__USBH2_DATA4 0x0
825 MX51_PAD_EIM_D21__USBH2_DATA5 0x0
826 MX51_PAD_EIM_D22__USBH2_DATA6 0x0
827 MX51_PAD_EIM_D23__USBH2_DATA7 0x0
828 >;
829 };
830
831 pinctrl_usbh2phy: usbh2phygrp {
832 fsl,pins = <
833 MX51_PAD_NANDF_D1__GPIO4_7 0x85
834 >;
835 };
836};