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1* Xilinx NWL PCIe Root Port Bridge DT description
2
3Required properties:
4- compatible: Should contain "xlnx,nwl-pcie-2.11"
5- #address-cells: Address representation for root ports, set to <3>
6- #size-cells: Size representation for root ports, set to <2>
7- #interrupt-cells: specifies the number of cells needed to encode an
8 interrupt source. The value must be 1.
9- reg: Should contain Bridge, PCIe Controller registers location,
10 configuration space, and length
11- reg-names: Must include the following entries:
12 "breg": bridge registers
13 "pcireg": PCIe controller registers
14 "cfg": configuration space region
15- device_type: must be "pci"
16- interrupts: Should contain NWL PCIe interrupt
17- interrupt-names: Must include the following entries:
18 "msi1, msi0": interrupt asserted when an MSI is received
19 "intx": interrupt asserted when a legacy interrupt is received
20 "misc": interrupt asserted when miscellaneous interrupt is received
21- interrupt-map-mask and interrupt-map: standard PCI properties to define the
22 mapping of the PCI interface to interrupt numbers.
23- ranges: ranges for the PCI memory regions (I/O space region is not
24 supported by hardware)
25 Please refer to the standard PCI bus binding document for a more
26 detailed explanation
27- msi-controller: indicates that this is MSI controller node
28- msi-parent: MSI parent of the root complex itself
29- legacy-interrupt-controller: Interrupt controller device node for Legacy
30 interrupts
31 - interrupt-controller: identifies the node as an interrupt controller
32 - #interrupt-cells: should be set to 1
33 - #address-cells: specifies the number of cells needed to encode an
34 address. The value must be 0.
35
36
37Example:
38++++++++
39
40nwl_pcie: pcie@fd0e0000 {
41 #address-cells = <3>;
42 #size-cells = <2>;
43 compatible = "xlnx,nwl-pcie-2.11";
44 #interrupt-cells = <1>;
45 msi-controller;
46 device_type = "pci";
47 interrupt-parent = <&gic>;
48 interrupts = <0 114 4>, <0 115 4>, <0 116 4>, <0 117 4>, <0 118 4>;
49 interrupt-names = "msi0", "msi1", "intx", "dummy", "misc";
50 interrupt-map-mask = <0x0 0x0 0x0 0x7>;
51 interrupt-map = <0x0 0x0 0x0 0x1 &pcie_intc 0x1>,
52 <0x0 0x0 0x0 0x2 &pcie_intc 0x2>,
53 <0x0 0x0 0x0 0x3 &pcie_intc 0x3>,
54 <0x0 0x0 0x0 0x4 &pcie_intc 0x4>;
55
56 msi-parent = <&nwl_pcie>;
57 reg = <0x0 0xfd0e0000 0x0 0x1000>,
58 <0x0 0xfd480000 0x0 0x1000>,
59 <0x80 0x00000000 0x0 0x1000000>;
60 reg-names = "breg", "pcireg", "cfg";
61 ranges = <0x02000000 0x00000000 0xe0000000 0x00000000 0xe0000000 0x00000000 0x10000000 /* non-prefetchable memory */
62 0x43000000 0x00000006 0x00000000 0x00000006 0x00000000 0x00000002 0x00000000>;/* prefetchable memory */
63
64 pcie_intc: legacy-interrupt-controller {
65 interrupt-controller;
66 #address-cells = <0>;
67 #interrupt-cells = <1>;
68 };
69
70};