tjh.dev
Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
1/*
2 * Driver for the Axis ARTPEC-6 pin controller
3 *
4 * Author: Chris Paterson <chris.paterson@linux.pieboy.co.uk>
5 *
6 * This file is licensed under the terms of the GNU General Public
7 * License version 2. This program is licensed "as is" without any
8 * warranty of any kind, whether express or implied.
9 */
10
11#include <linux/device.h>
12#include <linux/err.h>
13#include <linux/init.h>
14#include <linux/io.h>
15#include <linux/of.h>
16#include <linux/platform_device.h>
17#include <linux/pinctrl/pinctrl.h>
18#include <linux/pinctrl/pinconf-generic.h>
19#include <linux/pinctrl/pinconf.h>
20#include <linux/pinctrl/pinmux.h>
21#include <linux/slab.h>
22#include "core.h"
23#include "pinconf.h"
24#include "pinctrl-utils.h"
25
26#define ARTPEC6_LAST_PIN 97 /* 97 pins in pinmux */
27#define ARTPEC6_MAX_MUXABLE 35 /* Last pin with muxable function */
28
29/* Pinmux control register bit definitions */
30#define ARTPEC6_PINMUX_UDC0_MASK 0x00000001
31#define ARTPEC6_PINMUX_UDC0_SHIFT 0
32#define ARTPEC6_PINMUX_UDC1_MASK 0x00000002
33#define ARTPEC6_PINMUX_UDC1_SHIFT 1
34#define ARTPEC6_PINMUX_DRV_MASK 0x00000060
35#define ARTPEC6_PINMUX_DRV_SHIFT 5
36#define ARTPEC6_PINMUX_SEL_MASK 0x00003000
37#define ARTPEC6_PINMUX_SEL_SHIFT 12
38
39/* Pinmux configurations */
40#define ARTPEC6_CONFIG_0 0
41#define ARTPEC6_CONFIG_1 1
42#define ARTPEC6_CONFIG_2 2
43#define ARTPEC6_CONFIG_3 3
44
45/* Pin drive strength options */
46#define ARTPEC6_DRIVE_4mA 4
47#define ARTPEC6_DRIVE_4mA_SET 0
48#define ARTPEC6_DRIVE_6mA 6
49#define ARTPEC6_DRIVE_6mA_SET 1
50#define ARTPEC6_DRIVE_8mA 8
51#define ARTPEC6_DRIVE_8mA_SET 2
52#define ARTPEC6_DRIVE_9mA 9
53#define ARTPEC6_DRIVE_9mA_SET 3
54
55struct artpec6_pmx {
56 struct device *dev;
57 struct pinctrl_dev *pctl;
58 void __iomem *base;
59 struct pinctrl_pin_desc *pins;
60 unsigned int num_pins;
61 const struct artpec6_pin_group *pin_groups;
62 unsigned int num_pin_groups;
63 const struct artpec6_pmx_func *functions;
64 unsigned int num_functions;
65};
66
67struct artpec6_pin_group {
68 const char *name;
69 const unsigned int *pins;
70 const unsigned int num_pins;
71 unsigned char config;
72};
73
74struct artpec6_pmx_func {
75 const char *name;
76 const char * const *groups;
77 const unsigned int num_groups;
78};
79
80/* pins */
81static struct pinctrl_pin_desc artpec6_pins[] = {
82 PINCTRL_PIN(0, "GPIO0"),
83 PINCTRL_PIN(1, "GPIO1"),
84 PINCTRL_PIN(2, "GPIO2"),
85 PINCTRL_PIN(3, "GPIO3"),
86 PINCTRL_PIN(4, "GPIO4"),
87 PINCTRL_PIN(5, "GPIO5"),
88 PINCTRL_PIN(6, "GPIO6"),
89 PINCTRL_PIN(7, "GPIO7"),
90 PINCTRL_PIN(8, "GPIO8"),
91 PINCTRL_PIN(9, "GPIO9"),
92 PINCTRL_PIN(10, "GPIO10"),
93 PINCTRL_PIN(11, "GPIO11"),
94 PINCTRL_PIN(12, "GPIO12"),
95 PINCTRL_PIN(13, "GPIO13"),
96 PINCTRL_PIN(14, "GPIO14"),
97 PINCTRL_PIN(15, "GPIO15"),
98 PINCTRL_PIN(16, "GPIO16"),
99 PINCTRL_PIN(17, "GPIO17"),
100 PINCTRL_PIN(18, "GPIO18"),
101 PINCTRL_PIN(19, "GPIO19"),
102 PINCTRL_PIN(20, "GPIO20"),
103 PINCTRL_PIN(21, "GPIO21"),
104 PINCTRL_PIN(22, "GPIO22"),
105 PINCTRL_PIN(23, "GPIO23"),
106 PINCTRL_PIN(24, "GPIO24"),
107 PINCTRL_PIN(25, "GPIO25"),
108 PINCTRL_PIN(26, "GPIO26"),
109 PINCTRL_PIN(27, "GPIO27"),
110 PINCTRL_PIN(28, "GPIO28"),
111 PINCTRL_PIN(29, "GPIO29"),
112 PINCTRL_PIN(30, "GPIO30"),
113 PINCTRL_PIN(31, "GPIO31"),
114 PINCTRL_PIN(32, "UART3_TXD"),
115 PINCTRL_PIN(33, "UART3_RXD"),
116 PINCTRL_PIN(34, "UART3_RTS"),
117 PINCTRL_PIN(35, "UART3_CTS"),
118 PINCTRL_PIN(36, "NF_ALE"),
119 PINCTRL_PIN(37, "NF_CE0_N"),
120 PINCTRL_PIN(38, "NF_CE1_N"),
121 PINCTRL_PIN(39, "NF_CLE"),
122 PINCTRL_PIN(40, "NF_RE_N"),
123 PINCTRL_PIN(41, "NF_WE_N"),
124 PINCTRL_PIN(42, "NF_WP0_N"),
125 PINCTRL_PIN(43, "NF_WP1_N"),
126 PINCTRL_PIN(44, "NF_IO0"),
127 PINCTRL_PIN(45, "NF_IO1"),
128 PINCTRL_PIN(46, "NF_IO2"),
129 PINCTRL_PIN(47, "NF_IO3"),
130 PINCTRL_PIN(48, "NF_IO4"),
131 PINCTRL_PIN(49, "NF_IO5"),
132 PINCTRL_PIN(50, "NF_IO6"),
133 PINCTRL_PIN(51, "NF_IO7"),
134 PINCTRL_PIN(52, "NF_RB0_N"),
135 PINCTRL_PIN(53, "SDIO0_CLK"),
136 PINCTRL_PIN(54, "SDIO0_CMD"),
137 PINCTRL_PIN(55, "SDIO0_DAT0"),
138 PINCTRL_PIN(56, "SDIO0_DAT1"),
139 PINCTRL_PIN(57, "SDIO0_DAT2"),
140 PINCTRL_PIN(58, "SDIO0_DAT3"),
141 PINCTRL_PIN(59, "SDI0_CD"),
142 PINCTRL_PIN(60, "SDI0_WP"),
143 PINCTRL_PIN(61, "SDIO1_CLK"),
144 PINCTRL_PIN(62, "SDIO1_CMD"),
145 PINCTRL_PIN(63, "SDIO1_DAT0"),
146 PINCTRL_PIN(64, "SDIO1_DAT1"),
147 PINCTRL_PIN(65, "SDIO1_DAT2"),
148 PINCTRL_PIN(66, "SDIO1_DAT3"),
149 PINCTRL_PIN(67, "SDIO1_CD"),
150 PINCTRL_PIN(68, "SDIO1_WP"),
151 PINCTRL_PIN(69, "GBE_REFCLk"),
152 PINCTRL_PIN(70, "GBE_GTX_CLK"),
153 PINCTRL_PIN(71, "GBE_TX_CLK"),
154 PINCTRL_PIN(72, "GBE_TX_EN"),
155 PINCTRL_PIN(73, "GBE_TX_ER"),
156 PINCTRL_PIN(74, "GBE_TXD0"),
157 PINCTRL_PIN(75, "GBE_TXD1"),
158 PINCTRL_PIN(76, "GBE_TXD2"),
159 PINCTRL_PIN(77, "GBE_TXD3"),
160 PINCTRL_PIN(78, "GBE_TXD4"),
161 PINCTRL_PIN(79, "GBE_TXD5"),
162 PINCTRL_PIN(80, "GBE_TXD6"),
163 PINCTRL_PIN(81, "GBE_TXD7"),
164 PINCTRL_PIN(82, "GBE_RX_CLK"),
165 PINCTRL_PIN(83, "GBE_RX_DV"),
166 PINCTRL_PIN(84, "GBE_RX_ER"),
167 PINCTRL_PIN(85, "GBE_RXD0"),
168 PINCTRL_PIN(86, "GBE_RXD1"),
169 PINCTRL_PIN(87, "GBE_RXD2"),
170 PINCTRL_PIN(88, "GBE_RXD3"),
171 PINCTRL_PIN(89, "GBE_RXD4"),
172 PINCTRL_PIN(90, "GBE_RXD5"),
173 PINCTRL_PIN(91, "GBE_RXD6"),
174 PINCTRL_PIN(92, "GBE_RXD7"),
175 PINCTRL_PIN(93, "GBE_CRS"),
176 PINCTRL_PIN(94, "GBE_COL"),
177 PINCTRL_PIN(95, "GBE_MDC"),
178 PINCTRL_PIN(96, "GBE_MDIO"),
179};
180
181static const unsigned int cpuclkout_pins0[] = { 0 };
182static const unsigned int udlclkout_pins0[] = { 1 };
183static const unsigned int i2c1_pins0[] = { 2, 3 };
184static const unsigned int i2c2_pins0[] = { 4, 5 };
185static const unsigned int i2c3_pins0[] = { 6, 7 };
186static const unsigned int i2s0_pins0[] = { 8, 9, 10, 11 };
187static const unsigned int i2s1_pins0[] = { 12, 13, 14, 15 };
188static const unsigned int i2srefclk_pins0[] = { 19 };
189static const unsigned int spi0_pins0[] = { 12, 13, 14, 15 };
190static const unsigned int spi1_pins0[] = { 16, 17, 18, 19 };
191static const unsigned int pciedebug_pins0[] = { 12, 13, 14, 15 };
192static const unsigned int uart0_pins0[] = { 16, 17, 18, 19, 20,
193 21, 22, 23, 24, 25 };
194static const unsigned int uart0_pins1[] = { 20, 21, 22, 23 };
195static const unsigned int uart1_pins0[] = { 24, 25, 26, 27 };
196static const unsigned int uart2_pins0[] = { 26, 27, 28, 29, 30,
197 31, 32, 33, 34, 35 };
198static const unsigned int uart2_pins1[] = { 28, 29, 30, 31 };
199static const unsigned int uart3_pins0[] = { 32, 33, 34, 35 };
200static const unsigned int uart4_pins0[] = { 20, 21, 22, 23 };
201static const unsigned int uart5_pins0[] = { 28, 29, 30, 31 };
202static const unsigned int nand_pins0[] = { 36, 37, 38, 39, 40, 41,
203 42, 43, 44, 45, 46, 47,
204 48, 49, 50, 51, 52 };
205static const unsigned int sdio0_pins0[] = { 53, 54, 55, 56, 57, 58, 59, 60 };
206static const unsigned int sdio1_pins0[] = { 61, 62, 63, 64, 65, 66, 67, 68 };
207static const unsigned int ethernet_pins0[] = { 69, 70, 71, 72, 73, 74, 75,
208 76, 77, 78, 79, 80, 81, 82,
209 83, 84, 85, 86, 87, 88, 89,
210 90, 91, 92, 93, 94, 95, 96 };
211
212static const struct artpec6_pin_group artpec6_pin_groups[] = {
213 {
214 .name = "cpuclkoutgrp0",
215 .pins = cpuclkout_pins0,
216 .num_pins = ARRAY_SIZE(cpuclkout_pins0),
217 .config = ARTPEC6_CONFIG_1,
218 },
219 {
220 .name = "udlclkoutgrp0",
221 .pins = udlclkout_pins0,
222 .num_pins = ARRAY_SIZE(udlclkout_pins0),
223 .config = ARTPEC6_CONFIG_1,
224 },
225 {
226 .name = "i2c1grp0",
227 .pins = i2c1_pins0,
228 .num_pins = ARRAY_SIZE(i2c1_pins0),
229 .config = ARTPEC6_CONFIG_1,
230 },
231 {
232 .name = "i2c2grp0",
233 .pins = i2c2_pins0,
234 .num_pins = ARRAY_SIZE(i2c2_pins0),
235 .config = ARTPEC6_CONFIG_1,
236 },
237 {
238 .name = "i2c3grp0",
239 .pins = i2c3_pins0,
240 .num_pins = ARRAY_SIZE(i2c3_pins0),
241 .config = ARTPEC6_CONFIG_1,
242 },
243 {
244 .name = "i2s0grp0",
245 .pins = i2s0_pins0,
246 .num_pins = ARRAY_SIZE(i2s0_pins0),
247 .config = ARTPEC6_CONFIG_1,
248 },
249 {
250 .name = "i2s1grp0",
251 .pins = i2s1_pins0,
252 .num_pins = ARRAY_SIZE(i2s1_pins0),
253 .config = ARTPEC6_CONFIG_1,
254 },
255 {
256 .name = "i2srefclkgrp0",
257 .pins = i2srefclk_pins0,
258 .num_pins = ARRAY_SIZE(i2srefclk_pins0),
259 .config = ARTPEC6_CONFIG_3,
260 },
261 {
262 .name = "spi0grp0",
263 .pins = spi0_pins0,
264 .num_pins = ARRAY_SIZE(spi0_pins0),
265 .config = ARTPEC6_CONFIG_2,
266 },
267 {
268 .name = "spi1grp0",
269 .pins = spi1_pins0,
270 .num_pins = ARRAY_SIZE(spi1_pins0),
271 .config = ARTPEC6_CONFIG_2,
272 },
273 {
274 .name = "pciedebuggrp0",
275 .pins = pciedebug_pins0,
276 .num_pins = ARRAY_SIZE(pciedebug_pins0),
277 .config = ARTPEC6_CONFIG_3,
278 },
279 {
280 .name = "uart0grp0",
281 .pins = uart0_pins0,
282 .num_pins = ARRAY_SIZE(uart0_pins0),
283 .config = ARTPEC6_CONFIG_1,
284 },
285 {
286 .name = "uart0grp1",
287 .pins = uart0_pins1,
288 .num_pins = ARRAY_SIZE(uart0_pins1),
289 .config = ARTPEC6_CONFIG_1,
290 },
291 {
292 .name = "uart1grp0",
293 .pins = uart1_pins0,
294 .num_pins = ARRAY_SIZE(uart1_pins0),
295 .config = ARTPEC6_CONFIG_2,
296 },
297 {
298 .name = "uart2grp0",
299 .pins = uart2_pins0,
300 .num_pins = ARRAY_SIZE(uart2_pins0),
301 .config = ARTPEC6_CONFIG_1,
302 },
303 {
304 .name = "uart2grp1",
305 .pins = uart2_pins1,
306 .num_pins = ARRAY_SIZE(uart2_pins1),
307 .config = ARTPEC6_CONFIG_1,
308 },
309 {
310 .name = "uart3grp0",
311 .pins = uart3_pins0,
312 .num_pins = ARRAY_SIZE(uart3_pins0),
313 .config = ARTPEC6_CONFIG_0,
314 },
315 {
316 .name = "uart4grp0",
317 .pins = uart4_pins0,
318 .num_pins = ARRAY_SIZE(uart4_pins0),
319 .config = ARTPEC6_CONFIG_2,
320 },
321 {
322 .name = "uart5grp0",
323 .pins = uart5_pins0,
324 .num_pins = ARRAY_SIZE(uart5_pins0),
325 .config = ARTPEC6_CONFIG_2,
326 },
327 {
328 .name = "uart5nocts",
329 .pins = uart5_pins0,
330 .num_pins = ARRAY_SIZE(uart5_pins0) - 1,
331 .config = ARTPEC6_CONFIG_2,
332 },
333 {
334 .name = "nandgrp0",
335 .pins = nand_pins0,
336 .num_pins = ARRAY_SIZE(nand_pins0),
337 .config = ARTPEC6_CONFIG_0,
338 },
339 {
340 .name = "sdio0grp0",
341 .pins = sdio0_pins0,
342 .num_pins = ARRAY_SIZE(sdio0_pins0),
343 .config = ARTPEC6_CONFIG_0,
344 },
345 {
346 .name = "sdio1grp0",
347 .pins = sdio1_pins0,
348 .num_pins = ARRAY_SIZE(sdio1_pins0),
349 .config = ARTPEC6_CONFIG_0,
350 },
351 {
352 .name = "ethernetgrp0",
353 .pins = ethernet_pins0,
354 .num_pins = ARRAY_SIZE(ethernet_pins0),
355 .config = ARTPEC6_CONFIG_0,
356 },
357};
358
359struct pin_register {
360 unsigned int start;
361 unsigned int end;
362 unsigned int reg_base;
363};
364
365/*
366 * The register map has two holes where the pin number
367 * no longer fits directly with the register offset.
368 * This table allows us to map this easily.
369 */
370static const struct pin_register pin_register[] = {
371 { 0, 35, 0x0 }, /* 0x0 - 0x8c */
372 { 36, 52, 0x100 }, /* 0x100 - 0x140 */
373 { 53, 96, 0x180 }, /* 0x180 - 0x22c */
374};
375
376static unsigned int artpec6_pmx_reg_offset(unsigned int pin)
377{
378 int i;
379
380 for (i = 0; i < ARRAY_SIZE(pin_register); i++) {
381 if (pin <= pin_register[i].end) {
382 return (pin - pin_register[i].start) * 4 +
383 pin_register[i].reg_base;
384 }
385 }
386 /*
387 * Anything we return here is wrong, but we can only
388 * get here if pin is outside registered range.
389 */
390 pr_err("%s: Impossible pin %d\n", __func__, pin);
391 return 0;
392}
393
394static int artpec6_get_groups_count(struct pinctrl_dev *pctldev)
395{
396 return ARRAY_SIZE(artpec6_pin_groups);
397}
398
399static const char *artpec6_get_group_name(struct pinctrl_dev *pctldev,
400 unsigned int group)
401{
402 return artpec6_pin_groups[group].name;
403}
404
405static int artpec6_get_group_pins(struct pinctrl_dev *pctldev,
406 unsigned int group,
407 const unsigned int **pins,
408 unsigned int *num_pins)
409{
410 *pins = (unsigned int *)artpec6_pin_groups[group].pins;
411 *num_pins = artpec6_pin_groups[group].num_pins;
412 return 0;
413}
414
415static int artpec6_pconf_drive_mA_to_field(unsigned int mA)
416{
417 switch (mA) {
418 case ARTPEC6_DRIVE_4mA:
419 return ARTPEC6_DRIVE_4mA_SET;
420 case ARTPEC6_DRIVE_6mA:
421 return ARTPEC6_DRIVE_6mA_SET;
422 case ARTPEC6_DRIVE_8mA:
423 return ARTPEC6_DRIVE_8mA_SET;
424 case ARTPEC6_DRIVE_9mA:
425 return ARTPEC6_DRIVE_9mA_SET;
426 default:
427 return -EINVAL;
428 }
429}
430
431static unsigned int artpec6_pconf_drive_field_to_mA(int field)
432{
433 switch (field) {
434 case ARTPEC6_DRIVE_4mA_SET:
435 return ARTPEC6_DRIVE_4mA;
436 case ARTPEC6_DRIVE_6mA_SET:
437 return ARTPEC6_DRIVE_6mA;
438 case ARTPEC6_DRIVE_8mA_SET:
439 return ARTPEC6_DRIVE_8mA;
440 case ARTPEC6_DRIVE_9mA_SET:
441 return ARTPEC6_DRIVE_9mA;
442 default:
443 /* Shouldn't happen */
444 return 0;
445 }
446}
447
448static const struct pinctrl_ops artpec6_pctrl_ops = {
449 .get_group_pins = artpec6_get_group_pins,
450 .get_groups_count = artpec6_get_groups_count,
451 .get_group_name = artpec6_get_group_name,
452 .dt_node_to_map = pinconf_generic_dt_node_to_map_all,
453 .dt_free_map = pinctrl_utils_free_map,
454};
455
456static const char * const gpiogrps[] = {
457 "cpuclkoutgrp0", "udlclkoutgrp0", "i2c1grp0", "i2c2grp0",
458 "i2c3grp0", "i2s0grp0", "i2s1grp0", "i2srefclkgrp0",
459 "spi0grp0", "spi1grp0", "pciedebuggrp0", "uart0grp0",
460 "uart0grp1", "uart1grp0", "uart2grp0", "uart2grp1",
461 "uart4grp0", "uart5grp0",
462};
463static const char * const cpuclkoutgrps[] = { "cpuclkoutgrp0" };
464static const char * const udlclkoutgrps[] = { "udlclkoutgrp0" };
465static const char * const i2c1grps[] = { "i2c1grp0" };
466static const char * const i2c2grps[] = { "i2c2grp0" };
467static const char * const i2c3grps[] = { "i2c3grp0" };
468static const char * const i2s0grps[] = { "i2s0grp0" };
469static const char * const i2s1grps[] = { "i2s1grp0" };
470static const char * const i2srefclkgrps[] = { "i2srefclkgrp0" };
471static const char * const spi0grps[] = { "spi0grp0" };
472static const char * const spi1grps[] = { "spi1grp0" };
473static const char * const pciedebuggrps[] = { "pciedebuggrp0" };
474static const char * const uart0grps[] = { "uart0grp0", "uart0grp1" };
475static const char * const uart1grps[] = { "uart1grp0" };
476static const char * const uart2grps[] = { "uart2grp0", "uart2grp1" };
477static const char * const uart3grps[] = { "uart3grp0" };
478static const char * const uart4grps[] = { "uart4grp0" };
479static const char * const uart5grps[] = { "uart5grp0", "uart5nocts" };
480static const char * const nandgrps[] = { "nandgrp0" };
481static const char * const sdio0grps[] = { "sdio0grp0" };
482static const char * const sdio1grps[] = { "sdio1grp0" };
483static const char * const ethernetgrps[] = { "ethernetgrp0" };
484
485static const struct artpec6_pmx_func artpec6_pmx_functions[] = {
486 {
487 .name = "gpio",
488 .groups = gpiogrps,
489 .num_groups = ARRAY_SIZE(gpiogrps),
490 },
491 {
492 .name = "cpuclkout",
493 .groups = cpuclkoutgrps,
494 .num_groups = ARRAY_SIZE(cpuclkoutgrps),
495 },
496 {
497 .name = "udlclkout",
498 .groups = udlclkoutgrps,
499 .num_groups = ARRAY_SIZE(udlclkoutgrps),
500 },
501 {
502 .name = "i2c1",
503 .groups = i2c1grps,
504 .num_groups = ARRAY_SIZE(i2c1grps),
505 },
506 {
507 .name = "i2c2",
508 .groups = i2c2grps,
509 .num_groups = ARRAY_SIZE(i2c2grps),
510 },
511 {
512 .name = "i2c3",
513 .groups = i2c3grps,
514 .num_groups = ARRAY_SIZE(i2c3grps),
515 },
516 {
517 .name = "i2s0",
518 .groups = i2s0grps,
519 .num_groups = ARRAY_SIZE(i2s0grps),
520 },
521 {
522 .name = "i2s1",
523 .groups = i2s1grps,
524 .num_groups = ARRAY_SIZE(i2s1grps),
525 },
526 {
527 .name = "i2srefclk",
528 .groups = i2srefclkgrps,
529 .num_groups = ARRAY_SIZE(i2srefclkgrps),
530 },
531 {
532 .name = "spi0",
533 .groups = spi0grps,
534 .num_groups = ARRAY_SIZE(spi0grps),
535 },
536 {
537 .name = "spi1",
538 .groups = spi1grps,
539 .num_groups = ARRAY_SIZE(spi1grps),
540 },
541 {
542 .name = "pciedebug",
543 .groups = pciedebuggrps,
544 .num_groups = ARRAY_SIZE(pciedebuggrps),
545 },
546 {
547 .name = "uart0",
548 .groups = uart0grps,
549 .num_groups = ARRAY_SIZE(uart0grps),
550 },
551 {
552 .name = "uart1",
553 .groups = uart1grps,
554 .num_groups = ARRAY_SIZE(uart1grps),
555 },
556 {
557 .name = "uart2",
558 .groups = uart2grps,
559 .num_groups = ARRAY_SIZE(uart2grps),
560 },
561 {
562 .name = "uart3",
563 .groups = uart3grps,
564 .num_groups = ARRAY_SIZE(uart3grps),
565 },
566 {
567 .name = "uart4",
568 .groups = uart4grps,
569 .num_groups = ARRAY_SIZE(uart4grps),
570 },
571 {
572 .name = "uart5",
573 .groups = uart5grps,
574 .num_groups = ARRAY_SIZE(uart5grps),
575 },
576 {
577 .name = "nand",
578 .groups = nandgrps,
579 .num_groups = ARRAY_SIZE(nandgrps),
580 },
581 {
582 .name = "sdio0",
583 .groups = sdio0grps,
584 .num_groups = ARRAY_SIZE(sdio0grps),
585 },
586 {
587 .name = "sdio1",
588 .groups = sdio1grps,
589 .num_groups = ARRAY_SIZE(sdio1grps),
590 },
591 {
592 .name = "ethernet",
593 .groups = ethernetgrps,
594 .num_groups = ARRAY_SIZE(ethernetgrps),
595 },
596};
597
598static int artpec6_pmx_get_functions_count(struct pinctrl_dev *pctldev)
599{
600 return ARRAY_SIZE(artpec6_pmx_functions);
601}
602
603static const char *artpec6_pmx_get_fname(struct pinctrl_dev *pctldev,
604 unsigned int function)
605{
606 return artpec6_pmx_functions[function].name;
607}
608
609static int artpec6_pmx_get_fgroups(struct pinctrl_dev *pctldev,
610 unsigned int function,
611 const char * const **groups,
612 unsigned int * const num_groups)
613{
614 *groups = artpec6_pmx_functions[function].groups;
615 *num_groups = artpec6_pmx_functions[function].num_groups;
616 return 0;
617}
618
619static void artpec6_pmx_select_func(struct pinctrl_dev *pctldev,
620 unsigned int function, unsigned int group,
621 bool enable)
622{
623 unsigned int regval, val;
624 unsigned int reg;
625 int i;
626 struct artpec6_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
627
628 for (i = 0; i < artpec6_pin_groups[group].num_pins; i++) {
629 /*
630 * Registers for pins above a ARTPEC6_MAX_MUXABLE
631 * do not have a SEL field and are always selected.
632 */
633 if (artpec6_pin_groups[group].pins[i] > ARTPEC6_MAX_MUXABLE)
634 continue;
635
636 if (!strcmp(artpec6_pmx_get_fname(pctldev, function), "gpio")) {
637 /* GPIO is always config 0 */
638 val = ARTPEC6_CONFIG_0 << ARTPEC6_PINMUX_SEL_SHIFT;
639 } else {
640 if (enable)
641 val = artpec6_pin_groups[group].config
642 << ARTPEC6_PINMUX_SEL_SHIFT;
643 else
644 val = ARTPEC6_CONFIG_0
645 << ARTPEC6_PINMUX_SEL_SHIFT;
646 }
647
648 reg = artpec6_pmx_reg_offset(artpec6_pin_groups[group].pins[i]);
649
650 regval = readl(pmx->base + reg);
651 regval &= ~ARTPEC6_PINMUX_SEL_MASK;
652 regval |= val;
653 writel(regval, pmx->base + reg);
654 }
655}
656
657int artpec6_pmx_enable(struct pinctrl_dev *pctldev, unsigned int function,
658 unsigned int group)
659{
660 struct artpec6_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
661
662 dev_dbg(pmx->dev, "enabling %s function for pin group %s\n",
663 artpec6_pmx_get_fname(pctldev, function),
664 artpec6_get_group_name(pctldev, group));
665
666 artpec6_pmx_select_func(pctldev, function, group, true);
667
668 return 0;
669}
670
671void artpec6_pmx_disable(struct pinctrl_dev *pctldev, unsigned int function,
672 unsigned int group)
673{
674 struct artpec6_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
675
676 dev_dbg(pmx->dev, "disabling %s function for pin group %s\n",
677 artpec6_pmx_get_fname(pctldev, function),
678 artpec6_get_group_name(pctldev, group));
679
680 artpec6_pmx_select_func(pctldev, function, group, false);
681}
682
683static int artpec6_pmx_request_gpio(struct pinctrl_dev *pctldev,
684 struct pinctrl_gpio_range *range,
685 unsigned int pin)
686{
687 struct artpec6_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
688 unsigned int reg = artpec6_pmx_reg_offset(pin);
689 u32 val;
690
691 if (pin >= 32)
692 return -EINVAL;
693
694 val = readl_relaxed(pmx->base + reg);
695 val &= ~ARTPEC6_PINMUX_SEL_MASK;
696 val |= ARTPEC6_CONFIG_0 << ARTPEC6_PINMUX_SEL_SHIFT;
697 writel_relaxed(val, pmx->base + reg);
698
699 return 0;
700}
701
702static const struct pinmux_ops artpec6_pmx_ops = {
703 .get_functions_count = artpec6_pmx_get_functions_count,
704 .get_function_name = artpec6_pmx_get_fname,
705 .get_function_groups = artpec6_pmx_get_fgroups,
706 .set_mux = artpec6_pmx_enable,
707 .gpio_request_enable = artpec6_pmx_request_gpio,
708};
709
710static int artpec6_pconf_get(struct pinctrl_dev *pctldev, unsigned int pin,
711 unsigned long *config)
712{
713 struct artpec6_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
714 enum pin_config_param param = pinconf_to_config_param(*config);
715 unsigned int regval;
716
717 /* Check for valid pin */
718 if (pin >= pmx->num_pins) {
719 dev_dbg(pmx->dev, "pinconf is not supported for pin %s\n",
720 pmx->pins[pin].name);
721 return -ENOTSUPP;
722 }
723
724 dev_dbg(pmx->dev, "getting configuration for pin %s\n",
725 pmx->pins[pin].name);
726
727 /* Read pin register values */
728 regval = readl(pmx->base + artpec6_pmx_reg_offset(pin));
729
730 /* If valid, get configuration for parameter */
731 switch (param) {
732 case PIN_CONFIG_BIAS_DISABLE:
733 if (!(regval & ARTPEC6_PINMUX_UDC1_MASK))
734 return -EINVAL;
735 break;
736
737 case PIN_CONFIG_BIAS_PULL_UP:
738 case PIN_CONFIG_BIAS_PULL_DOWN:
739 if (regval & ARTPEC6_PINMUX_UDC1_MASK)
740 return -EINVAL;
741
742 regval = regval & ARTPEC6_PINMUX_UDC0_MASK;
743 if ((param == PIN_CONFIG_BIAS_PULL_UP && !regval) ||
744 (param == PIN_CONFIG_BIAS_PULL_DOWN && regval))
745 return -EINVAL;
746 break;
747 case PIN_CONFIG_DRIVE_STRENGTH:
748 regval = (regval & ARTPEC6_PINMUX_DRV_MASK)
749 >> ARTPEC6_PINMUX_DRV_SHIFT;
750 regval = artpec6_pconf_drive_field_to_mA(regval);
751 *config = pinconf_to_config_packed(param, regval);
752 break;
753 default:
754 return -ENOTSUPP;
755 }
756
757 return 0;
758}
759
760/*
761 * Valid combinations of param and arg:
762 *
763 * param arg
764 * PIN_CONFIG_BIAS_DISABLE: x (disable bias)
765 * PIN_CONFIG_BIAS_PULL_UP: 1 (pull up bias + enable)
766 * PIN_CONFIG_BIAS_PULL_DOWN: 1 (pull down bias + enable)
767 * PIN_CONFIG_DRIVE_STRENGTH: x (4mA, 6mA, 8mA, 9mA)
768 *
769 * All other args are invalid. All other params are not supported.
770 */
771static int artpec6_pconf_set(struct pinctrl_dev *pctldev, unsigned int pin,
772 unsigned long *configs, unsigned int num_configs)
773{
774 struct artpec6_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
775 enum pin_config_param param;
776 unsigned int arg;
777 unsigned int regval;
778 unsigned int *reg;
779 int i;
780
781 /* Check for valid pin */
782 if (pin >= pmx->num_pins) {
783 dev_dbg(pmx->dev, "pinconf is not supported for pin %s\n",
784 pmx->pins[pin].name);
785 return -ENOTSUPP;
786 }
787
788 dev_dbg(pmx->dev, "setting configuration for pin %s\n",
789 pmx->pins[pin].name);
790
791 reg = pmx->base + artpec6_pmx_reg_offset(pin);
792
793 /* For each config */
794 for (i = 0; i < num_configs; i++) {
795 int drive;
796
797 param = pinconf_to_config_param(configs[i]);
798 arg = pinconf_to_config_argument(configs[i]);
799
800 switch (param) {
801 case PIN_CONFIG_BIAS_DISABLE:
802 regval = readl(reg);
803 regval |= (1 << ARTPEC6_PINMUX_UDC1_SHIFT);
804 writel(regval, reg);
805 break;
806
807 case PIN_CONFIG_BIAS_PULL_UP:
808 if (arg != 1) {
809 dev_dbg(pctldev->dev, "%s: arg %u out of range\n",
810 __func__, arg);
811 return -EINVAL;
812 }
813
814 regval = readl(reg);
815 regval |= (arg << ARTPEC6_PINMUX_UDC0_SHIFT);
816 regval &= ~ARTPEC6_PINMUX_UDC1_MASK; /* Enable */
817 writel(regval, reg);
818 break;
819
820 case PIN_CONFIG_BIAS_PULL_DOWN:
821 if (arg != 1) {
822 dev_dbg(pctldev->dev, "%s: arg %u out of range\n",
823 __func__, arg);
824 return -EINVAL;
825 }
826
827 regval = readl(reg);
828 regval &= ~(arg << ARTPEC6_PINMUX_UDC0_SHIFT);
829 regval &= ~ARTPEC6_PINMUX_UDC1_MASK; /* Enable */
830 writel(regval, reg);
831 break;
832
833 case PIN_CONFIG_DRIVE_STRENGTH:
834 drive = artpec6_pconf_drive_mA_to_field(arg);
835 if (drive < 0) {
836 dev_dbg(pctldev->dev, "%s: arg %u out of range\n",
837 __func__, arg);
838 return -EINVAL;
839 }
840
841 regval = readl(reg);
842 regval &= ~ARTPEC6_PINMUX_DRV_MASK;
843 regval |= (drive << ARTPEC6_PINMUX_DRV_SHIFT);
844 writel(regval, reg);
845 break;
846
847 default:
848 dev_dbg(pmx->dev, "parameter not supported\n");
849 return -ENOTSUPP;
850 }
851 }
852
853 return 0;
854}
855
856static int artpec6_pconf_group_set(struct pinctrl_dev *pctldev,
857 unsigned int group, unsigned long *configs,
858 unsigned int num_configs)
859{
860 unsigned int num_pins, current_pin;
861 int ret;
862
863 dev_dbg(pctldev->dev, "setting group %s configuration\n",
864 artpec6_get_group_name(pctldev, group));
865
866 num_pins = artpec6_pin_groups[group].num_pins;
867
868 for (current_pin = 0; current_pin < num_pins; current_pin++) {
869 ret = artpec6_pconf_set(pctldev,
870 artpec6_pin_groups[group].pins[current_pin],
871 configs, num_configs);
872
873 if (ret < 0)
874 return ret;
875 }
876
877 return 0;
878}
879
880static const struct pinconf_ops artpec6_pconf_ops = {
881 .is_generic = true,
882 .pin_config_get = artpec6_pconf_get,
883 .pin_config_set = artpec6_pconf_set,
884 .pin_config_group_set = artpec6_pconf_group_set,
885};
886
887static struct pinctrl_desc artpec6_desc = {
888 .name = "artpec6-pinctrl",
889 .owner = THIS_MODULE,
890 .pins = artpec6_pins,
891 .npins = ARRAY_SIZE(artpec6_pins),
892 .pctlops = &artpec6_pctrl_ops,
893 .pmxops = &artpec6_pmx_ops,
894 .confops = &artpec6_pconf_ops,
895};
896
897/* The reset values say 4mA, but we want 8mA as default. */
898static void artpec6_pmx_reset(struct artpec6_pmx *pmx)
899{
900 void __iomem *base = pmx->base;
901 int i;
902
903 for (i = 0; i < ARTPEC6_LAST_PIN; i++) {
904 u32 val;
905
906 val = readl_relaxed(base + artpec6_pmx_reg_offset(i));
907 val &= ~ARTPEC6_PINMUX_DRV_MASK;
908 val |= ARTPEC6_DRIVE_8mA_SET << ARTPEC6_PINMUX_DRV_SHIFT;
909 writel_relaxed(val, base + artpec6_pmx_reg_offset(i));
910 }
911}
912
913static int artpec6_pmx_probe(struct platform_device *pdev)
914{
915 struct artpec6_pmx *pmx;
916 struct resource *res;
917
918 pmx = devm_kzalloc(&pdev->dev, sizeof(*pmx), GFP_KERNEL);
919 if (!pmx)
920 return -ENOMEM;
921
922 pmx->dev = &pdev->dev;
923
924 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
925 pmx->base = devm_ioremap_resource(&pdev->dev, res);
926
927 if (IS_ERR(pmx->base))
928 return PTR_ERR(pmx->base);
929
930 artpec6_pmx_reset(pmx);
931
932 pmx->pins = artpec6_pins;
933 pmx->num_pins = ARRAY_SIZE(artpec6_pins);
934 pmx->functions = artpec6_pmx_functions;
935 pmx->num_functions = ARRAY_SIZE(artpec6_pmx_functions);
936 pmx->pin_groups = artpec6_pin_groups;
937 pmx->num_pin_groups = ARRAY_SIZE(artpec6_pin_groups);
938 pmx->pctl = pinctrl_register(&artpec6_desc, &pdev->dev, pmx);
939
940 if (IS_ERR(pmx->pctl)) {
941 dev_err(&pdev->dev, "could not register pinctrl driver\n");
942 return PTR_ERR(pmx->pctl);
943 }
944
945 platform_set_drvdata(pdev, pmx);
946
947 dev_info(&pdev->dev, "initialised Axis ARTPEC-6 pinctrl driver\n");
948
949 return 0;
950}
951
952static int artpec6_pmx_remove(struct platform_device *pdev)
953{
954 struct artpec6_pmx *pmx = platform_get_drvdata(pdev);
955
956 pinctrl_unregister(pmx->pctl);
957
958 return 0;
959}
960
961static const struct of_device_id artpec6_pinctrl_match[] = {
962 { .compatible = "axis,artpec6-pinctrl" },
963 {},
964};
965
966static struct platform_driver artpec6_pmx_driver = {
967 .driver = {
968 .name = "artpec6-pinctrl",
969 .of_match_table = artpec6_pinctrl_match,
970 },
971 .probe = artpec6_pmx_probe,
972 .remove = artpec6_pmx_remove,
973};
974
975static int __init artpec6_pmx_init(void)
976{
977 return platform_driver_register(&artpec6_pmx_driver);
978}
979arch_initcall(artpec6_pmx_init);