tjh.dev
Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
1/*
2 * (C) COPYRIGHT 2016 ARM Limited. All rights reserved.
3 * Author: Liviu Dudau <Liviu.Dudau@arm.com>
4 *
5 * This program is free software and is provided to you under the terms of the
6 * GNU General Public License version 2 as published by the Free Software
7 * Foundation, and any use by you of this program is subject to the terms
8 * of such GNU licence.
9 *
10 * ARM Mali DP plane manipulation routines.
11 */
12
13#include <drm/drmP.h>
14#include <drm/drm_atomic.h>
15#include <drm/drm_atomic_helper.h>
16#include <drm/drm_fb_cma_helper.h>
17#include <drm/drm_gem_cma_helper.h>
18#include <drm/drm_plane_helper.h>
19#include <drm/drm_print.h>
20
21#include "malidp_hw.h"
22#include "malidp_drv.h"
23
24/* Layer specific register offsets */
25#define MALIDP_LAYER_FORMAT 0x000
26#define MALIDP_LAYER_CONTROL 0x004
27#define LAYER_ENABLE (1 << 0)
28#define LAYER_FLOWCFG_MASK 7
29#define LAYER_FLOWCFG(x) (((x) & LAYER_FLOWCFG_MASK) << 1)
30#define LAYER_FLOWCFG_SCALE_SE 3
31#define LAYER_ROT_OFFSET 8
32#define LAYER_H_FLIP (1 << 10)
33#define LAYER_V_FLIP (1 << 11)
34#define LAYER_ROT_MASK (0xf << 8)
35#define LAYER_COMP_MASK (0x3 << 12)
36#define LAYER_COMP_PIXEL (0x3 << 12)
37#define LAYER_COMP_PLANE (0x2 << 12)
38#define MALIDP_LAYER_COMPOSE 0x008
39#define MALIDP_LAYER_SIZE 0x00c
40#define LAYER_H_VAL(x) (((x) & 0x1fff) << 0)
41#define LAYER_V_VAL(x) (((x) & 0x1fff) << 16)
42#define MALIDP_LAYER_COMP_SIZE 0x010
43#define MALIDP_LAYER_OFFSET 0x014
44#define MALIDP550_LS_ENABLE 0x01c
45#define MALIDP550_LS_R1_IN_SIZE 0x020
46
47/*
48 * This 4-entry look-up-table is used to determine the full 8-bit alpha value
49 * for formats with 1- or 2-bit alpha channels.
50 * We set it to give 100%/0% opacity for 1-bit formats and 100%/66%/33%/0%
51 * opacity for 2-bit formats.
52 */
53#define MALIDP_ALPHA_LUT 0xffaa5500
54
55static void malidp_de_plane_destroy(struct drm_plane *plane)
56{
57 struct malidp_plane *mp = to_malidp_plane(plane);
58
59 if (mp->base.fb)
60 drm_framebuffer_put(mp->base.fb);
61
62 drm_plane_helper_disable(plane);
63 drm_plane_cleanup(plane);
64 devm_kfree(plane->dev->dev, mp);
65}
66
67/*
68 * Replicate what the default ->reset hook does: free the state pointer and
69 * allocate a new empty object. We just need enough space to store
70 * a malidp_plane_state instead of a drm_plane_state.
71 */
72static void malidp_plane_reset(struct drm_plane *plane)
73{
74 struct malidp_plane_state *state = to_malidp_plane_state(plane->state);
75
76 if (state)
77 __drm_atomic_helper_plane_destroy_state(&state->base);
78 kfree(state);
79 plane->state = NULL;
80 state = kzalloc(sizeof(*state), GFP_KERNEL);
81 if (state) {
82 state->base.plane = plane;
83 state->base.rotation = DRM_MODE_ROTATE_0;
84 plane->state = &state->base;
85 }
86}
87
88static struct
89drm_plane_state *malidp_duplicate_plane_state(struct drm_plane *plane)
90{
91 struct malidp_plane_state *state, *m_state;
92
93 if (!plane->state)
94 return NULL;
95
96 state = kmalloc(sizeof(*state), GFP_KERNEL);
97 if (!state)
98 return NULL;
99
100 m_state = to_malidp_plane_state(plane->state);
101 __drm_atomic_helper_plane_duplicate_state(plane, &state->base);
102 state->rotmem_size = m_state->rotmem_size;
103 state->format = m_state->format;
104 state->n_planes = m_state->n_planes;
105
106 return &state->base;
107}
108
109static void malidp_destroy_plane_state(struct drm_plane *plane,
110 struct drm_plane_state *state)
111{
112 struct malidp_plane_state *m_state = to_malidp_plane_state(state);
113
114 __drm_atomic_helper_plane_destroy_state(state);
115 kfree(m_state);
116}
117
118static void malidp_plane_atomic_print_state(struct drm_printer *p,
119 const struct drm_plane_state *state)
120{
121 struct malidp_plane_state *ms = to_malidp_plane_state(state);
122
123 drm_printf(p, "\trotmem_size=%u\n", ms->rotmem_size);
124 drm_printf(p, "\tformat_id=%u\n", ms->format);
125 drm_printf(p, "\tn_planes=%u\n", ms->n_planes);
126}
127
128static const struct drm_plane_funcs malidp_de_plane_funcs = {
129 .update_plane = drm_atomic_helper_update_plane,
130 .disable_plane = drm_atomic_helper_disable_plane,
131 .destroy = malidp_de_plane_destroy,
132 .reset = malidp_plane_reset,
133 .atomic_duplicate_state = malidp_duplicate_plane_state,
134 .atomic_destroy_state = malidp_destroy_plane_state,
135 .atomic_print_state = malidp_plane_atomic_print_state,
136};
137
138static int malidp_se_check_scaling(struct malidp_plane *mp,
139 struct drm_plane_state *state)
140{
141 struct drm_crtc_state *crtc_state =
142 drm_atomic_get_existing_crtc_state(state->state, state->crtc);
143 struct malidp_crtc_state *mc;
144 struct drm_rect clip = { 0 };
145 u32 src_w, src_h;
146 int ret;
147
148 if (!crtc_state)
149 return -EINVAL;
150
151 clip.x2 = crtc_state->adjusted_mode.hdisplay;
152 clip.y2 = crtc_state->adjusted_mode.vdisplay;
153 ret = drm_atomic_helper_check_plane_state(state, crtc_state, &clip,
154 0, INT_MAX, true, true);
155 if (ret)
156 return ret;
157
158 src_w = state->src_w >> 16;
159 src_h = state->src_h >> 16;
160 if ((state->crtc_w == src_w) && (state->crtc_h == src_h)) {
161 /* Scaling not necessary for this plane. */
162 mc->scaled_planes_mask &= ~(mp->layer->id);
163 return 0;
164 }
165
166 if (mp->layer->id & (DE_SMART | DE_GRAPHICS2))
167 return -EINVAL;
168
169 mc = to_malidp_crtc_state(crtc_state);
170
171 mc->scaled_planes_mask |= mp->layer->id;
172 /* Defer scaling requirements calculation to the crtc check. */
173 return 0;
174}
175
176static int malidp_de_plane_check(struct drm_plane *plane,
177 struct drm_plane_state *state)
178{
179 struct malidp_plane *mp = to_malidp_plane(plane);
180 struct malidp_plane_state *ms = to_malidp_plane_state(state);
181 struct drm_framebuffer *fb;
182 int i, ret;
183
184 if (!state->crtc || !state->fb)
185 return 0;
186
187 fb = state->fb;
188
189 ms->format = malidp_hw_get_format_id(&mp->hwdev->hw->map,
190 mp->layer->id,
191 fb->format->format);
192 if (ms->format == MALIDP_INVALID_FORMAT_ID)
193 return -EINVAL;
194
195 ms->n_planes = fb->format->num_planes;
196 for (i = 0; i < ms->n_planes; i++) {
197 if (!malidp_hw_pitch_valid(mp->hwdev, fb->pitches[i])) {
198 DRM_DEBUG_KMS("Invalid pitch %u for plane %d\n",
199 fb->pitches[i], i);
200 return -EINVAL;
201 }
202 }
203
204 if ((state->crtc_w > mp->hwdev->max_line_size) ||
205 (state->crtc_h > mp->hwdev->max_line_size) ||
206 (state->crtc_w < mp->hwdev->min_line_size) ||
207 (state->crtc_h < mp->hwdev->min_line_size))
208 return -EINVAL;
209
210 /*
211 * DP550/650 video layers can accept 3 plane formats only if
212 * fb->pitches[1] == fb->pitches[2] since they don't have a
213 * third plane stride register.
214 */
215 if (ms->n_planes == 3 &&
216 !(mp->hwdev->hw->features & MALIDP_DEVICE_LV_HAS_3_STRIDES) &&
217 (state->fb->pitches[1] != state->fb->pitches[2]))
218 return -EINVAL;
219
220 ret = malidp_se_check_scaling(mp, state);
221 if (ret)
222 return ret;
223
224 /* packed RGB888 / BGR888 can't be rotated or flipped */
225 if (state->rotation != DRM_MODE_ROTATE_0 &&
226 (fb->format->format == DRM_FORMAT_RGB888 ||
227 fb->format->format == DRM_FORMAT_BGR888))
228 return -EINVAL;
229
230 ms->rotmem_size = 0;
231 if (state->rotation & MALIDP_ROTATED_MASK) {
232 int val;
233
234 val = mp->hwdev->hw->rotmem_required(mp->hwdev, state->crtc_h,
235 state->crtc_w,
236 fb->format->format);
237 if (val < 0)
238 return val;
239
240 ms->rotmem_size = val;
241 }
242
243 return 0;
244}
245
246static void malidp_de_set_plane_pitches(struct malidp_plane *mp,
247 int num_planes, unsigned int pitches[3])
248{
249 int i;
250 int num_strides = num_planes;
251
252 if (!mp->layer->stride_offset)
253 return;
254
255 if (num_planes == 3)
256 num_strides = (mp->hwdev->hw->features &
257 MALIDP_DEVICE_LV_HAS_3_STRIDES) ? 3 : 2;
258
259 for (i = 0; i < num_strides; ++i)
260 malidp_hw_write(mp->hwdev, pitches[i],
261 mp->layer->base +
262 mp->layer->stride_offset + i * 4);
263}
264
265static void malidp_de_plane_update(struct drm_plane *plane,
266 struct drm_plane_state *old_state)
267{
268 struct malidp_plane *mp;
269 struct malidp_plane_state *ms = to_malidp_plane_state(plane->state);
270 u32 src_w, src_h, dest_w, dest_h, val;
271 int i;
272
273 mp = to_malidp_plane(plane);
274
275 /* convert src values from Q16 fixed point to integer */
276 src_w = plane->state->src_w >> 16;
277 src_h = plane->state->src_h >> 16;
278 dest_w = plane->state->crtc_w;
279 dest_h = plane->state->crtc_h;
280
281 malidp_hw_write(mp->hwdev, ms->format, mp->layer->base);
282
283 for (i = 0; i < ms->n_planes; i++) {
284 /* calculate the offset for the layer's plane registers */
285 u16 ptr = mp->layer->ptr + (i << 4);
286 dma_addr_t fb_addr = drm_fb_cma_get_gem_addr(plane->state->fb,
287 plane->state, i);
288
289 malidp_hw_write(mp->hwdev, lower_32_bits(fb_addr), ptr);
290 malidp_hw_write(mp->hwdev, upper_32_bits(fb_addr), ptr + 4);
291 }
292 malidp_de_set_plane_pitches(mp, ms->n_planes,
293 plane->state->fb->pitches);
294
295 malidp_hw_write(mp->hwdev, LAYER_H_VAL(src_w) | LAYER_V_VAL(src_h),
296 mp->layer->base + MALIDP_LAYER_SIZE);
297
298 malidp_hw_write(mp->hwdev, LAYER_H_VAL(dest_w) | LAYER_V_VAL(dest_h),
299 mp->layer->base + MALIDP_LAYER_COMP_SIZE);
300
301 malidp_hw_write(mp->hwdev, LAYER_H_VAL(plane->state->crtc_x) |
302 LAYER_V_VAL(plane->state->crtc_y),
303 mp->layer->base + MALIDP_LAYER_OFFSET);
304
305 if (mp->layer->id == DE_SMART)
306 malidp_hw_write(mp->hwdev,
307 LAYER_H_VAL(src_w) | LAYER_V_VAL(src_h),
308 mp->layer->base + MALIDP550_LS_R1_IN_SIZE);
309
310 /* first clear the rotation bits */
311 val = malidp_hw_read(mp->hwdev, mp->layer->base + MALIDP_LAYER_CONTROL);
312 val &= ~LAYER_ROT_MASK;
313
314 /* setup the rotation and axis flip bits */
315 if (plane->state->rotation & DRM_MODE_ROTATE_MASK)
316 val |= ilog2(plane->state->rotation & DRM_MODE_ROTATE_MASK) <<
317 LAYER_ROT_OFFSET;
318 if (plane->state->rotation & DRM_MODE_REFLECT_X)
319 val |= LAYER_H_FLIP;
320 if (plane->state->rotation & DRM_MODE_REFLECT_Y)
321 val |= LAYER_V_FLIP;
322
323 /*
324 * always enable pixel alpha blending until we have a way to change
325 * blend modes
326 */
327 val &= ~LAYER_COMP_MASK;
328 val |= LAYER_COMP_PIXEL;
329
330 val &= ~LAYER_FLOWCFG(LAYER_FLOWCFG_MASK);
331 if (plane->state->crtc) {
332 struct malidp_crtc_state *m =
333 to_malidp_crtc_state(plane->state->crtc->state);
334
335 if (m->scaler_config.scale_enable &&
336 m->scaler_config.plane_src_id == mp->layer->id)
337 val |= LAYER_FLOWCFG(LAYER_FLOWCFG_SCALE_SE);
338 }
339
340 /* set the 'enable layer' bit */
341 val |= LAYER_ENABLE;
342
343 malidp_hw_write(mp->hwdev, val,
344 mp->layer->base + MALIDP_LAYER_CONTROL);
345}
346
347static void malidp_de_plane_disable(struct drm_plane *plane,
348 struct drm_plane_state *state)
349{
350 struct malidp_plane *mp = to_malidp_plane(plane);
351
352 malidp_hw_clearbits(mp->hwdev,
353 LAYER_ENABLE | LAYER_FLOWCFG(LAYER_FLOWCFG_MASK),
354 mp->layer->base + MALIDP_LAYER_CONTROL);
355}
356
357static const struct drm_plane_helper_funcs malidp_de_plane_helper_funcs = {
358 .atomic_check = malidp_de_plane_check,
359 .atomic_update = malidp_de_plane_update,
360 .atomic_disable = malidp_de_plane_disable,
361};
362
363int malidp_de_planes_init(struct drm_device *drm)
364{
365 struct malidp_drm *malidp = drm->dev_private;
366 const struct malidp_hw_regmap *map = &malidp->dev->hw->map;
367 struct malidp_plane *plane = NULL;
368 enum drm_plane_type plane_type;
369 unsigned long crtcs = 1 << drm->mode_config.num_crtc;
370 unsigned long flags = DRM_MODE_ROTATE_0 | DRM_MODE_ROTATE_90 | DRM_MODE_ROTATE_180 |
371 DRM_MODE_ROTATE_270 | DRM_MODE_REFLECT_X | DRM_MODE_REFLECT_Y;
372 u32 *formats;
373 int ret, i, j, n;
374
375 formats = kcalloc(map->n_pixel_formats, sizeof(*formats), GFP_KERNEL);
376 if (!formats) {
377 ret = -ENOMEM;
378 goto cleanup;
379 }
380
381 for (i = 0; i < map->n_layers; i++) {
382 u8 id = map->layers[i].id;
383
384 plane = kzalloc(sizeof(*plane), GFP_KERNEL);
385 if (!plane) {
386 ret = -ENOMEM;
387 goto cleanup;
388 }
389
390 /* build the list of DRM supported formats based on the map */
391 for (n = 0, j = 0; j < map->n_pixel_formats; j++) {
392 if ((map->pixel_formats[j].layer & id) == id)
393 formats[n++] = map->pixel_formats[j].format;
394 }
395
396 plane_type = (i == 0) ? DRM_PLANE_TYPE_PRIMARY :
397 DRM_PLANE_TYPE_OVERLAY;
398 ret = drm_universal_plane_init(drm, &plane->base, crtcs,
399 &malidp_de_plane_funcs, formats,
400 n, NULL, plane_type, NULL);
401 if (ret < 0)
402 goto cleanup;
403
404 drm_plane_helper_add(&plane->base,
405 &malidp_de_plane_helper_funcs);
406 plane->hwdev = malidp->dev;
407 plane->layer = &map->layers[i];
408
409 if (id == DE_SMART) {
410 /*
411 * Enable the first rectangle in the SMART layer to be
412 * able to use it as a drm plane.
413 */
414 malidp_hw_write(malidp->dev, 1,
415 plane->layer->base + MALIDP550_LS_ENABLE);
416 /* Skip the features which the SMART layer doesn't have. */
417 continue;
418 }
419
420 drm_plane_create_rotation_property(&plane->base, DRM_MODE_ROTATE_0, flags);
421 malidp_hw_write(malidp->dev, MALIDP_ALPHA_LUT,
422 plane->layer->base + MALIDP_LAYER_COMPOSE);
423 }
424
425 kfree(formats);
426
427 return 0;
428
429cleanup:
430 malidp_de_planes_destroy(drm);
431 kfree(formats);
432
433 return ret;
434}
435
436void malidp_de_planes_destroy(struct drm_device *drm)
437{
438 struct drm_plane *p, *pt;
439
440 list_for_each_entry_safe(p, pt, &drm->mode_config.plane_list, head) {
441 drm_plane_cleanup(p);
442 kfree(p);
443 }
444}