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1* Renesas Clock Pulse Generator / Module Standby and Software Reset
2
3On Renesas ARM SoCs (SH/R-Mobile, R-Car, RZ), the CPG (Clock Pulse Generator)
4and MSSR (Module Standby and Software Reset) blocks are intimately connected,
5and share the same register block.
6
7They provide the following functionalities:
8 - The CPG block generates various core clocks,
9 - The MSSR block provides two functions:
10 1. Module Standby, providing a Clock Domain to control the clock supply
11 to individual SoC devices,
12 2. Reset Control, to perform a software reset of individual SoC devices.
13
14Required Properties:
15 - compatible: Must be one of:
16 - "renesas,r8a7743-cpg-mssr" for the r8a7743 SoC (RZ/G1M)
17 - "renesas,r8a7745-cpg-mssr" for the r8a7745 SoC (RZ/G1E)
18 - "renesas,r8a7790-cpg-mssr" for the r8a7790 SoC (R-Car H2)
19 - "renesas,r8a7791-cpg-mssr" for the r8a7791 SoC (R-Car M2-W)
20 - "renesas,r8a7792-cpg-mssr" for the r8a7792 SoC (R-Car V2H)
21 - "renesas,r8a7793-cpg-mssr" for the r8a7793 SoC (R-Car M2-N)
22 - "renesas,r8a7794-cpg-mssr" for the r8a7794 SoC (R-Car E2)
23 - "renesas,r8a7795-cpg-mssr" for the r8a7795 SoC (R-Car H3)
24 - "renesas,r8a7796-cpg-mssr" for the r8a7796 SoC (R-Car M3-W)
25 - "renesas,r8a77970-cpg-mssr" for the r8a77970 SoC (R-Car V3M)
26 - "renesas,r8a77995-cpg-mssr" for the r8a77995 SoC (R-Car D3)
27
28 - reg: Base address and length of the memory resource used by the CPG/MSSR
29 block
30
31 - clocks: References to external parent clocks, one entry for each entry in
32 clock-names
33 - clock-names: List of external parent clock names. Valid names are:
34 - "extal" (r8a7743, r8a7745, r8a7790, r8a7791, r8a7792, r8a7793, r8a7794,
35 r8a7795, r8a7796, r8a77970, r8a77995)
36 - "extalr" (r8a7795, r8a7796, r8a77970)
37 - "usb_extal" (r8a7743, r8a7745, r8a7790, r8a7791, r8a7793, r8a7794)
38
39 - #clock-cells: Must be 2
40 - For CPG core clocks, the two clock specifier cells must be "CPG_CORE"
41 and a core clock reference, as defined in
42 <dt-bindings/clock/*-cpg-mssr.h>.
43 - For module clocks, the two clock specifier cells must be "CPG_MOD" and
44 a module number, as defined in the datasheet.
45
46 - #power-domain-cells: Must be 0
47 - SoC devices that are part of the CPG/MSSR Clock Domain and can be
48 power-managed through Module Standby should refer to the CPG device
49 node in their "power-domains" property, as documented by the generic PM
50 Domain bindings in
51 Documentation/devicetree/bindings/power/power_domain.txt.
52
53 - #reset-cells: Must be 1
54 - The single reset specifier cell must be the module number, as defined
55 in the datasheet.
56
57
58Examples
59--------
60
61 - CPG device node:
62
63 cpg: clock-controller@e6150000 {
64 compatible = "renesas,r8a7795-cpg-mssr";
65 reg = <0 0xe6150000 0 0x1000>;
66 clocks = <&extal_clk>, <&extalr_clk>;
67 clock-names = "extal", "extalr";
68 #clock-cells = <2>;
69 #power-domain-cells = <0>;
70 #reset-cells = <1>;
71 };
72
73
74 - CPG/MSSR Clock Domain member device node:
75
76 scif2: serial@e6e88000 {
77 compatible = "renesas,scif-r8a7795", "renesas,scif";
78 reg = <0 0xe6e88000 0 64>;
79 interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>;
80 clocks = <&cpg CPG_MOD 310>;
81 clock-names = "fck";
82 dmas = <&dmac1 0x13>, <&dmac1 0x12>;
83 dma-names = "tx", "rx";
84 power-domains = <&cpg>;
85 resets = <&cpg 310>;
86 };