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1Qualcomm QUSB2 phy controller 2============================= 3 4QUSB2 controller supports LS/FS/HS usb connectivity on Qualcomm chipsets. 5 6Required properties: 7 - compatible: compatible list, contains "qcom,msm8996-qusb2-phy". 8 - reg: offset and length of the PHY register set. 9 - #phy-cells: must be 0. 10 11 - clocks: a list of phandles and clock-specifier pairs, 12 one for each entry in clock-names. 13 - clock-names: must be "cfg_ahb" for phy config clock, 14 "ref" for 19.2 MHz ref clk, 15 "iface" for phy interface clock (Optional). 16 17 - vdda-pll-supply: Phandle to 1.8V regulator supply to PHY refclk pll block. 18 - vdda-phy-dpdm-supply: Phandle to 3.1V regulator supply to Dp/Dm port signals. 19 20 - resets: Phandle to reset to phy block. 21 22Optional properties: 23 - nvmem-cells: Phandle to nvmem cell that contains 'HS Tx trim' 24 tuning parameter value for qusb2 phy. 25 26 - qcom,tcsr-syscon: Phandle to TCSR syscon register region. 27 28Example: 29 hsusb_phy: phy@7411000 { 30 compatible = "qcom,msm8996-qusb2-phy"; 31 reg = <0x7411000 0x180>; 32 #phy-cells = <0>; 33 34 clocks = <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>, 35 <&gcc GCC_RX1_USB2_CLKREF_CLK>, 36 clock-names = "cfg_ahb", "ref"; 37 38 vdda-pll-supply = <&pm8994_l12>; 39 vdda-phy-dpdm-supply = <&pm8994_l24>; 40 41 resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>; 42 nvmem-cells = <&qusb2p_hstx_trim>; 43 };