Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
tjh.dev
kernel
os
linux
1/*
2 * Copyright 2014, Michael Ellerman, IBM Corp.
3 * Licensed under GPLv2.
4 */
5
6#ifndef _SELFTESTS_POWERPC_REG_H
7#define _SELFTESTS_POWERPC_REG_H
8
9#define __stringify_1(x) #x
10#define __stringify(x) __stringify_1(x)
11
12#define mfspr(rn) ({unsigned long rval; \
13 asm volatile("mfspr %0," _str(rn) \
14 : "=r" (rval)); rval; })
15#define mtspr(rn, v) asm volatile("mtspr " _str(rn) ",%0" : \
16 : "r" ((unsigned long)(v)) \
17 : "memory")
18
19#define mb() asm volatile("sync" : : : "memory");
20
21#define SPRN_MMCR2 769
22#define SPRN_MMCRA 770
23#define SPRN_MMCR0 779
24#define MMCR0_PMAO 0x00000080
25#define MMCR0_PMAE 0x04000000
26#define MMCR0_FC 0x80000000
27#define SPRN_EBBHR 804
28#define SPRN_EBBRR 805
29#define SPRN_BESCR 806 /* Branch event status & control register */
30#define SPRN_BESCRS 800 /* Branch event status & control set (1 bits set to 1) */
31#define SPRN_BESCRSU 801 /* Branch event status & control set upper */
32#define SPRN_BESCRR 802 /* Branch event status & control REset (1 bits set to 0) */
33#define SPRN_BESCRRU 803 /* Branch event status & control REset upper */
34
35#define BESCR_PMEO 0x1 /* PMU Event-based exception Occurred */
36#define BESCR_PME (0x1ul << 32) /* PMU Event-based exception Enable */
37
38#define SPRN_PMC1 771
39#define SPRN_PMC2 772
40#define SPRN_PMC3 773
41#define SPRN_PMC4 774
42#define SPRN_PMC5 775
43#define SPRN_PMC6 776
44
45#define SPRN_SIAR 780
46#define SPRN_SDAR 781
47#define SPRN_SIER 768
48
49#define SPRN_TEXASR 0x82 /* Transaction Exception and Status Register */
50#define SPRN_TFIAR 0x81 /* Transaction Failure Inst Addr */
51#define SPRN_TFHAR 0x80 /* Transaction Failure Handler Addr */
52#define SPRN_TAR 0x32f /* Target Address Register */
53
54#define SPRN_DSCR_PRIV 0x11 /* Privilege State DSCR */
55#define SPRN_DSCR 0x03 /* Data Stream Control Register */
56#define SPRN_PPR 896 /* Program Priority Register */
57
58/* TEXASR register bits */
59#define TEXASR_FC 0xFE00000000000000
60#define TEXASR_FP 0x0100000000000000
61#define TEXASR_DA 0x0080000000000000
62#define TEXASR_NO 0x0040000000000000
63#define TEXASR_FO 0x0020000000000000
64#define TEXASR_SIC 0x0010000000000000
65#define TEXASR_NTC 0x0008000000000000
66#define TEXASR_TC 0x0004000000000000
67#define TEXASR_TIC 0x0002000000000000
68#define TEXASR_IC 0x0001000000000000
69#define TEXASR_IFC 0x0000800000000000
70#define TEXASR_ABT 0x0000000100000000
71#define TEXASR_SPD 0x0000000080000000
72#define TEXASR_HV 0x0000000020000000
73#define TEXASR_PR 0x0000000010000000
74#define TEXASR_FS 0x0000000008000000
75#define TEXASR_TE 0x0000000004000000
76#define TEXASR_ROT 0x0000000002000000
77
78/* Vector Instructions */
79#define VSX_XX1(xs, ra, rb) (((xs) & 0x1f) << 21 | ((ra) << 16) | \
80 ((rb) << 11) | (((xs) >> 5)))
81#define STXVD2X(xs, ra, rb) .long (0x7c000798 | VSX_XX1((xs), (ra), (rb)))
82#define LXVD2X(xs, ra, rb) .long (0x7c000698 | VSX_XX1((xs), (ra), (rb)))
83
84#define ASM_LOAD_GPR_IMMED(_asm_symbol_name_immed) \
85 "li 14, %[" #_asm_symbol_name_immed "];" \
86 "li 15, %[" #_asm_symbol_name_immed "];" \
87 "li 16, %[" #_asm_symbol_name_immed "];" \
88 "li 17, %[" #_asm_symbol_name_immed "];" \
89 "li 18, %[" #_asm_symbol_name_immed "];" \
90 "li 19, %[" #_asm_symbol_name_immed "];" \
91 "li 20, %[" #_asm_symbol_name_immed "];" \
92 "li 21, %[" #_asm_symbol_name_immed "];" \
93 "li 22, %[" #_asm_symbol_name_immed "];" \
94 "li 23, %[" #_asm_symbol_name_immed "];" \
95 "li 24, %[" #_asm_symbol_name_immed "];" \
96 "li 25, %[" #_asm_symbol_name_immed "];" \
97 "li 26, %[" #_asm_symbol_name_immed "];" \
98 "li 27, %[" #_asm_symbol_name_immed "];" \
99 "li 28, %[" #_asm_symbol_name_immed "];" \
100 "li 29, %[" #_asm_symbol_name_immed "];" \
101 "li 30, %[" #_asm_symbol_name_immed "];" \
102 "li 31, %[" #_asm_symbol_name_immed "];"
103
104#define ASM_LOAD_FPR_SINGLE_PRECISION(_asm_symbol_name_addr) \
105 "lfs 0, 0(%[" #_asm_symbol_name_addr "]);" \
106 "lfs 1, 0(%[" #_asm_symbol_name_addr "]);" \
107 "lfs 2, 0(%[" #_asm_symbol_name_addr "]);" \
108 "lfs 3, 0(%[" #_asm_symbol_name_addr "]);" \
109 "lfs 4, 0(%[" #_asm_symbol_name_addr "]);" \
110 "lfs 5, 0(%[" #_asm_symbol_name_addr "]);" \
111 "lfs 6, 0(%[" #_asm_symbol_name_addr "]);" \
112 "lfs 7, 0(%[" #_asm_symbol_name_addr "]);" \
113 "lfs 8, 0(%[" #_asm_symbol_name_addr "]);" \
114 "lfs 9, 0(%[" #_asm_symbol_name_addr "]);" \
115 "lfs 10, 0(%[" #_asm_symbol_name_addr "]);" \
116 "lfs 11, 0(%[" #_asm_symbol_name_addr "]);" \
117 "lfs 12, 0(%[" #_asm_symbol_name_addr "]);" \
118 "lfs 13, 0(%[" #_asm_symbol_name_addr "]);" \
119 "lfs 14, 0(%[" #_asm_symbol_name_addr "]);" \
120 "lfs 15, 0(%[" #_asm_symbol_name_addr "]);" \
121 "lfs 16, 0(%[" #_asm_symbol_name_addr "]);" \
122 "lfs 17, 0(%[" #_asm_symbol_name_addr "]);" \
123 "lfs 18, 0(%[" #_asm_symbol_name_addr "]);" \
124 "lfs 19, 0(%[" #_asm_symbol_name_addr "]);" \
125 "lfs 20, 0(%[" #_asm_symbol_name_addr "]);" \
126 "lfs 21, 0(%[" #_asm_symbol_name_addr "]);" \
127 "lfs 22, 0(%[" #_asm_symbol_name_addr "]);" \
128 "lfs 23, 0(%[" #_asm_symbol_name_addr "]);" \
129 "lfs 24, 0(%[" #_asm_symbol_name_addr "]);" \
130 "lfs 25, 0(%[" #_asm_symbol_name_addr "]);" \
131 "lfs 26, 0(%[" #_asm_symbol_name_addr "]);" \
132 "lfs 27, 0(%[" #_asm_symbol_name_addr "]);" \
133 "lfs 28, 0(%[" #_asm_symbol_name_addr "]);" \
134 "lfs 29, 0(%[" #_asm_symbol_name_addr "]);" \
135 "lfs 30, 0(%[" #_asm_symbol_name_addr "]);" \
136 "lfs 31, 0(%[" #_asm_symbol_name_addr "]);"
137
138#ifndef __ASSEMBLER__
139void store_gpr(unsigned long *addr);
140void load_gpr(unsigned long *addr);
141void load_fpr_single_precision(float *addr);
142void store_fpr_single_precision(float *addr);
143#endif /* end of __ASSEMBLER__ */
144
145#endif /* _SELFTESTS_POWERPC_REG_H */