Linux kernel mirror (for testing)
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linux
1/*
2 * Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved.
3 *
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
31 */
32
33#ifndef MLX5_DEVICE_H
34#define MLX5_DEVICE_H
35
36#include <linux/types.h>
37#include <rdma/ib_verbs.h>
38#include <linux/mlx5/mlx5_ifc.h>
39
40#if defined(__LITTLE_ENDIAN)
41#define MLX5_SET_HOST_ENDIANNESS 0
42#elif defined(__BIG_ENDIAN)
43#define MLX5_SET_HOST_ENDIANNESS 0x80
44#else
45#error Host endianness not defined
46#endif
47
48/* helper macros */
49#define __mlx5_nullp(typ) ((struct mlx5_ifc_##typ##_bits *)0)
50#define __mlx5_bit_sz(typ, fld) sizeof(__mlx5_nullp(typ)->fld)
51#define __mlx5_bit_off(typ, fld) (offsetof(struct mlx5_ifc_##typ##_bits, fld))
52#define __mlx5_16_off(typ, fld) (__mlx5_bit_off(typ, fld) / 16)
53#define __mlx5_dw_off(typ, fld) (__mlx5_bit_off(typ, fld) / 32)
54#define __mlx5_64_off(typ, fld) (__mlx5_bit_off(typ, fld) / 64)
55#define __mlx5_16_bit_off(typ, fld) (16 - __mlx5_bit_sz(typ, fld) - (__mlx5_bit_off(typ, fld) & 0xf))
56#define __mlx5_dw_bit_off(typ, fld) (32 - __mlx5_bit_sz(typ, fld) - (__mlx5_bit_off(typ, fld) & 0x1f))
57#define __mlx5_mask(typ, fld) ((u32)((1ull << __mlx5_bit_sz(typ, fld)) - 1))
58#define __mlx5_dw_mask(typ, fld) (__mlx5_mask(typ, fld) << __mlx5_dw_bit_off(typ, fld))
59#define __mlx5_mask16(typ, fld) ((u16)((1ull << __mlx5_bit_sz(typ, fld)) - 1))
60#define __mlx5_16_mask(typ, fld) (__mlx5_mask16(typ, fld) << __mlx5_16_bit_off(typ, fld))
61#define __mlx5_st_sz_bits(typ) sizeof(struct mlx5_ifc_##typ##_bits)
62
63#define MLX5_FLD_SZ_BYTES(typ, fld) (__mlx5_bit_sz(typ, fld) / 8)
64#define MLX5_ST_SZ_BYTES(typ) (sizeof(struct mlx5_ifc_##typ##_bits) / 8)
65#define MLX5_ST_SZ_DW(typ) (sizeof(struct mlx5_ifc_##typ##_bits) / 32)
66#define MLX5_ST_SZ_QW(typ) (sizeof(struct mlx5_ifc_##typ##_bits) / 64)
67#define MLX5_UN_SZ_BYTES(typ) (sizeof(union mlx5_ifc_##typ##_bits) / 8)
68#define MLX5_UN_SZ_DW(typ) (sizeof(union mlx5_ifc_##typ##_bits) / 32)
69#define MLX5_BYTE_OFF(typ, fld) (__mlx5_bit_off(typ, fld) / 8)
70#define MLX5_ADDR_OF(typ, p, fld) ((char *)(p) + MLX5_BYTE_OFF(typ, fld))
71
72/* insert a value to a struct */
73#define MLX5_SET(typ, p, fld, v) do { \
74 u32 _v = v; \
75 BUILD_BUG_ON(__mlx5_st_sz_bits(typ) % 32); \
76 *((__be32 *)(p) + __mlx5_dw_off(typ, fld)) = \
77 cpu_to_be32((be32_to_cpu(*((__be32 *)(p) + __mlx5_dw_off(typ, fld))) & \
78 (~__mlx5_dw_mask(typ, fld))) | (((_v) & __mlx5_mask(typ, fld)) \
79 << __mlx5_dw_bit_off(typ, fld))); \
80} while (0)
81
82#define MLX5_SET_TO_ONES(typ, p, fld) do { \
83 BUILD_BUG_ON(__mlx5_st_sz_bits(typ) % 32); \
84 *((__be32 *)(p) + __mlx5_dw_off(typ, fld)) = \
85 cpu_to_be32((be32_to_cpu(*((__be32 *)(p) + __mlx5_dw_off(typ, fld))) & \
86 (~__mlx5_dw_mask(typ, fld))) | ((__mlx5_mask(typ, fld)) \
87 << __mlx5_dw_bit_off(typ, fld))); \
88} while (0)
89
90#define MLX5_GET(typ, p, fld) ((be32_to_cpu(*((__be32 *)(p) +\
91__mlx5_dw_off(typ, fld))) >> __mlx5_dw_bit_off(typ, fld)) & \
92__mlx5_mask(typ, fld))
93
94#define MLX5_GET_PR(typ, p, fld) ({ \
95 u32 ___t = MLX5_GET(typ, p, fld); \
96 pr_debug(#fld " = 0x%x\n", ___t); \
97 ___t; \
98})
99
100#define __MLX5_SET64(typ, p, fld, v) do { \
101 BUILD_BUG_ON(__mlx5_bit_sz(typ, fld) != 64); \
102 *((__be64 *)(p) + __mlx5_64_off(typ, fld)) = cpu_to_be64(v); \
103} while (0)
104
105#define MLX5_SET64(typ, p, fld, v) do { \
106 BUILD_BUG_ON(__mlx5_bit_off(typ, fld) % 64); \
107 __MLX5_SET64(typ, p, fld, v); \
108} while (0)
109
110#define MLX5_ARRAY_SET64(typ, p, fld, idx, v) do { \
111 BUILD_BUG_ON(__mlx5_bit_off(typ, fld) % 64); \
112 __MLX5_SET64(typ, p, fld[idx], v); \
113} while (0)
114
115#define MLX5_GET64(typ, p, fld) be64_to_cpu(*((__be64 *)(p) + __mlx5_64_off(typ, fld)))
116
117#define MLX5_GET64_PR(typ, p, fld) ({ \
118 u64 ___t = MLX5_GET64(typ, p, fld); \
119 pr_debug(#fld " = 0x%llx\n", ___t); \
120 ___t; \
121})
122
123#define MLX5_GET16(typ, p, fld) ((be16_to_cpu(*((__be16 *)(p) +\
124__mlx5_16_off(typ, fld))) >> __mlx5_16_bit_off(typ, fld)) & \
125__mlx5_mask16(typ, fld))
126
127#define MLX5_SET16(typ, p, fld, v) do { \
128 u16 _v = v; \
129 BUILD_BUG_ON(__mlx5_st_sz_bits(typ) % 16); \
130 *((__be16 *)(p) + __mlx5_16_off(typ, fld)) = \
131 cpu_to_be16((be16_to_cpu(*((__be16 *)(p) + __mlx5_16_off(typ, fld))) & \
132 (~__mlx5_16_mask(typ, fld))) | (((_v) & __mlx5_mask16(typ, fld)) \
133 << __mlx5_16_bit_off(typ, fld))); \
134} while (0)
135
136/* Big endian getters */
137#define MLX5_GET64_BE(typ, p, fld) (*((__be64 *)(p) +\
138 __mlx5_64_off(typ, fld)))
139
140#define MLX5_GET_BE(type_t, typ, p, fld) ({ \
141 type_t tmp; \
142 switch (sizeof(tmp)) { \
143 case sizeof(u8): \
144 tmp = (__force type_t)MLX5_GET(typ, p, fld); \
145 break; \
146 case sizeof(u16): \
147 tmp = (__force type_t)cpu_to_be16(MLX5_GET(typ, p, fld)); \
148 break; \
149 case sizeof(u32): \
150 tmp = (__force type_t)cpu_to_be32(MLX5_GET(typ, p, fld)); \
151 break; \
152 case sizeof(u64): \
153 tmp = (__force type_t)MLX5_GET64_BE(typ, p, fld); \
154 break; \
155 } \
156 tmp; \
157 })
158
159enum mlx5_inline_modes {
160 MLX5_INLINE_MODE_NONE,
161 MLX5_INLINE_MODE_L2,
162 MLX5_INLINE_MODE_IP,
163 MLX5_INLINE_MODE_TCP_UDP,
164};
165
166enum {
167 MLX5_MAX_COMMANDS = 32,
168 MLX5_CMD_DATA_BLOCK_SIZE = 512,
169 MLX5_PCI_CMD_XPORT = 7,
170 MLX5_MKEY_BSF_OCTO_SIZE = 4,
171 MLX5_MAX_PSVS = 4,
172};
173
174enum {
175 MLX5_EXTENDED_UD_AV = 0x80000000,
176};
177
178enum {
179 MLX5_CQ_STATE_ARMED = 9,
180 MLX5_CQ_STATE_ALWAYS_ARMED = 0xb,
181 MLX5_CQ_STATE_FIRED = 0xa,
182};
183
184enum {
185 MLX5_STAT_RATE_OFFSET = 5,
186};
187
188enum {
189 MLX5_INLINE_SEG = 0x80000000,
190};
191
192enum {
193 MLX5_HW_START_PADDING = MLX5_INLINE_SEG,
194};
195
196enum {
197 MLX5_MIN_PKEY_TABLE_SIZE = 128,
198 MLX5_MAX_LOG_PKEY_TABLE = 5,
199};
200
201enum {
202 MLX5_MKEY_INBOX_PG_ACCESS = 1 << 31
203};
204
205enum {
206 MLX5_PFAULT_SUBTYPE_WQE = 0,
207 MLX5_PFAULT_SUBTYPE_RDMA = 1,
208};
209
210enum {
211 MLX5_PERM_LOCAL_READ = 1 << 2,
212 MLX5_PERM_LOCAL_WRITE = 1 << 3,
213 MLX5_PERM_REMOTE_READ = 1 << 4,
214 MLX5_PERM_REMOTE_WRITE = 1 << 5,
215 MLX5_PERM_ATOMIC = 1 << 6,
216 MLX5_PERM_UMR_EN = 1 << 7,
217};
218
219enum {
220 MLX5_PCIE_CTRL_SMALL_FENCE = 1 << 0,
221 MLX5_PCIE_CTRL_RELAXED_ORDERING = 1 << 2,
222 MLX5_PCIE_CTRL_NO_SNOOP = 1 << 3,
223 MLX5_PCIE_CTRL_TLP_PROCE_EN = 1 << 6,
224 MLX5_PCIE_CTRL_TPH_MASK = 3 << 4,
225};
226
227enum {
228 MLX5_EN_RD = (u64)1,
229 MLX5_EN_WR = (u64)2
230};
231
232enum {
233 MLX5_ADAPTER_PAGE_SHIFT = 12,
234 MLX5_ADAPTER_PAGE_SIZE = 1 << MLX5_ADAPTER_PAGE_SHIFT,
235};
236
237enum {
238 MLX5_BFREGS_PER_UAR = 4,
239 MLX5_MAX_UARS = 1 << 8,
240 MLX5_NON_FP_BFREGS_PER_UAR = 2,
241 MLX5_FP_BFREGS_PER_UAR = MLX5_BFREGS_PER_UAR -
242 MLX5_NON_FP_BFREGS_PER_UAR,
243 MLX5_MAX_BFREGS = MLX5_MAX_UARS *
244 MLX5_NON_FP_BFREGS_PER_UAR,
245 MLX5_UARS_IN_PAGE = PAGE_SIZE / MLX5_ADAPTER_PAGE_SIZE,
246 MLX5_NON_FP_BFREGS_IN_PAGE = MLX5_NON_FP_BFREGS_PER_UAR * MLX5_UARS_IN_PAGE,
247};
248
249enum {
250 MLX5_MKEY_MASK_LEN = 1ull << 0,
251 MLX5_MKEY_MASK_PAGE_SIZE = 1ull << 1,
252 MLX5_MKEY_MASK_START_ADDR = 1ull << 6,
253 MLX5_MKEY_MASK_PD = 1ull << 7,
254 MLX5_MKEY_MASK_EN_RINVAL = 1ull << 8,
255 MLX5_MKEY_MASK_EN_SIGERR = 1ull << 9,
256 MLX5_MKEY_MASK_BSF_EN = 1ull << 12,
257 MLX5_MKEY_MASK_KEY = 1ull << 13,
258 MLX5_MKEY_MASK_QPN = 1ull << 14,
259 MLX5_MKEY_MASK_LR = 1ull << 17,
260 MLX5_MKEY_MASK_LW = 1ull << 18,
261 MLX5_MKEY_MASK_RR = 1ull << 19,
262 MLX5_MKEY_MASK_RW = 1ull << 20,
263 MLX5_MKEY_MASK_A = 1ull << 21,
264 MLX5_MKEY_MASK_SMALL_FENCE = 1ull << 23,
265 MLX5_MKEY_MASK_FREE = 1ull << 29,
266};
267
268enum {
269 MLX5_UMR_TRANSLATION_OFFSET_EN = (1 << 4),
270
271 MLX5_UMR_CHECK_NOT_FREE = (1 << 5),
272 MLX5_UMR_CHECK_FREE = (2 << 5),
273
274 MLX5_UMR_INLINE = (1 << 7),
275};
276
277#define MLX5_UMR_MTT_ALIGNMENT 0x40
278#define MLX5_UMR_MTT_MASK (MLX5_UMR_MTT_ALIGNMENT - 1)
279#define MLX5_UMR_MTT_MIN_CHUNK_SIZE MLX5_UMR_MTT_ALIGNMENT
280
281#define MLX5_USER_INDEX_LEN (MLX5_FLD_SZ_BYTES(qpc, user_index) * 8)
282
283enum {
284 MLX5_EVENT_QUEUE_TYPE_QP = 0,
285 MLX5_EVENT_QUEUE_TYPE_RQ = 1,
286 MLX5_EVENT_QUEUE_TYPE_SQ = 2,
287};
288
289enum mlx5_event {
290 MLX5_EVENT_TYPE_COMP = 0x0,
291
292 MLX5_EVENT_TYPE_PATH_MIG = 0x01,
293 MLX5_EVENT_TYPE_COMM_EST = 0x02,
294 MLX5_EVENT_TYPE_SQ_DRAINED = 0x03,
295 MLX5_EVENT_TYPE_SRQ_LAST_WQE = 0x13,
296 MLX5_EVENT_TYPE_SRQ_RQ_LIMIT = 0x14,
297
298 MLX5_EVENT_TYPE_CQ_ERROR = 0x04,
299 MLX5_EVENT_TYPE_WQ_CATAS_ERROR = 0x05,
300 MLX5_EVENT_TYPE_PATH_MIG_FAILED = 0x07,
301 MLX5_EVENT_TYPE_WQ_INVAL_REQ_ERROR = 0x10,
302 MLX5_EVENT_TYPE_WQ_ACCESS_ERROR = 0x11,
303 MLX5_EVENT_TYPE_SRQ_CATAS_ERROR = 0x12,
304
305 MLX5_EVENT_TYPE_INTERNAL_ERROR = 0x08,
306 MLX5_EVENT_TYPE_PORT_CHANGE = 0x09,
307 MLX5_EVENT_TYPE_GPIO_EVENT = 0x15,
308 MLX5_EVENT_TYPE_PORT_MODULE_EVENT = 0x16,
309 MLX5_EVENT_TYPE_REMOTE_CONFIG = 0x19,
310 MLX5_EVENT_TYPE_GENERAL_EVENT = 0x22,
311 MLX5_EVENT_TYPE_PPS_EVENT = 0x25,
312
313 MLX5_EVENT_TYPE_DB_BF_CONGESTION = 0x1a,
314 MLX5_EVENT_TYPE_STALL_EVENT = 0x1b,
315
316 MLX5_EVENT_TYPE_CMD = 0x0a,
317 MLX5_EVENT_TYPE_PAGE_REQUEST = 0xb,
318
319 MLX5_EVENT_TYPE_PAGE_FAULT = 0xc,
320 MLX5_EVENT_TYPE_NIC_VPORT_CHANGE = 0xd,
321
322 MLX5_EVENT_TYPE_FPGA_ERROR = 0x20,
323};
324
325enum {
326 MLX5_GENERAL_SUBTYPE_DELAY_DROP_TIMEOUT = 0x1,
327};
328
329enum {
330 MLX5_PORT_CHANGE_SUBTYPE_DOWN = 1,
331 MLX5_PORT_CHANGE_SUBTYPE_ACTIVE = 4,
332 MLX5_PORT_CHANGE_SUBTYPE_INITIALIZED = 5,
333 MLX5_PORT_CHANGE_SUBTYPE_LID = 6,
334 MLX5_PORT_CHANGE_SUBTYPE_PKEY = 7,
335 MLX5_PORT_CHANGE_SUBTYPE_GUID = 8,
336 MLX5_PORT_CHANGE_SUBTYPE_CLIENT_REREG = 9,
337};
338
339enum {
340 MLX5_DEV_CAP_FLAG_XRC = 1LL << 3,
341 MLX5_DEV_CAP_FLAG_BAD_PKEY_CNTR = 1LL << 8,
342 MLX5_DEV_CAP_FLAG_BAD_QKEY_CNTR = 1LL << 9,
343 MLX5_DEV_CAP_FLAG_APM = 1LL << 17,
344 MLX5_DEV_CAP_FLAG_ATOMIC = 1LL << 18,
345 MLX5_DEV_CAP_FLAG_BLOCK_MCAST = 1LL << 23,
346 MLX5_DEV_CAP_FLAG_ON_DMND_PG = 1LL << 24,
347 MLX5_DEV_CAP_FLAG_CQ_MODER = 1LL << 29,
348 MLX5_DEV_CAP_FLAG_RESIZE_CQ = 1LL << 30,
349 MLX5_DEV_CAP_FLAG_DCT = 1LL << 37,
350 MLX5_DEV_CAP_FLAG_SIG_HAND_OVER = 1LL << 40,
351 MLX5_DEV_CAP_FLAG_CMDIF_CSUM = 3LL << 46,
352};
353
354enum {
355 MLX5_ROCE_VERSION_1 = 0,
356 MLX5_ROCE_VERSION_2 = 2,
357};
358
359enum {
360 MLX5_ROCE_VERSION_1_CAP = 1 << MLX5_ROCE_VERSION_1,
361 MLX5_ROCE_VERSION_2_CAP = 1 << MLX5_ROCE_VERSION_2,
362};
363
364enum {
365 MLX5_ROCE_L3_TYPE_IPV4 = 0,
366 MLX5_ROCE_L3_TYPE_IPV6 = 1,
367};
368
369enum {
370 MLX5_ROCE_L3_TYPE_IPV4_CAP = 1 << 1,
371 MLX5_ROCE_L3_TYPE_IPV6_CAP = 1 << 2,
372};
373
374enum {
375 MLX5_OPCODE_NOP = 0x00,
376 MLX5_OPCODE_SEND_INVAL = 0x01,
377 MLX5_OPCODE_RDMA_WRITE = 0x08,
378 MLX5_OPCODE_RDMA_WRITE_IMM = 0x09,
379 MLX5_OPCODE_SEND = 0x0a,
380 MLX5_OPCODE_SEND_IMM = 0x0b,
381 MLX5_OPCODE_LSO = 0x0e,
382 MLX5_OPCODE_RDMA_READ = 0x10,
383 MLX5_OPCODE_ATOMIC_CS = 0x11,
384 MLX5_OPCODE_ATOMIC_FA = 0x12,
385 MLX5_OPCODE_ATOMIC_MASKED_CS = 0x14,
386 MLX5_OPCODE_ATOMIC_MASKED_FA = 0x15,
387 MLX5_OPCODE_BIND_MW = 0x18,
388 MLX5_OPCODE_CONFIG_CMD = 0x1f,
389
390 MLX5_RECV_OPCODE_RDMA_WRITE_IMM = 0x00,
391 MLX5_RECV_OPCODE_SEND = 0x01,
392 MLX5_RECV_OPCODE_SEND_IMM = 0x02,
393 MLX5_RECV_OPCODE_SEND_INVAL = 0x03,
394
395 MLX5_CQE_OPCODE_ERROR = 0x1e,
396 MLX5_CQE_OPCODE_RESIZE = 0x16,
397
398 MLX5_OPCODE_SET_PSV = 0x20,
399 MLX5_OPCODE_GET_PSV = 0x21,
400 MLX5_OPCODE_CHECK_PSV = 0x22,
401 MLX5_OPCODE_RGET_PSV = 0x26,
402 MLX5_OPCODE_RCHECK_PSV = 0x27,
403
404 MLX5_OPCODE_UMR = 0x25,
405
406};
407
408enum {
409 MLX5_SET_PORT_RESET_QKEY = 0,
410 MLX5_SET_PORT_GUID0 = 16,
411 MLX5_SET_PORT_NODE_GUID = 17,
412 MLX5_SET_PORT_SYS_GUID = 18,
413 MLX5_SET_PORT_GID_TABLE = 19,
414 MLX5_SET_PORT_PKEY_TABLE = 20,
415};
416
417enum {
418 MLX5_BW_NO_LIMIT = 0,
419 MLX5_100_MBPS_UNIT = 3,
420 MLX5_GBPS_UNIT = 4,
421};
422
423enum {
424 MLX5_MAX_PAGE_SHIFT = 31
425};
426
427enum {
428 MLX5_CAP_OFF_CMDIF_CSUM = 46,
429};
430
431enum {
432 /*
433 * Max wqe size for rdma read is 512 bytes, so this
434 * limits our max_sge_rd as the wqe needs to fit:
435 * - ctrl segment (16 bytes)
436 * - rdma segment (16 bytes)
437 * - scatter elements (16 bytes each)
438 */
439 MLX5_MAX_SGE_RD = (512 - 16 - 16) / 16
440};
441
442enum mlx5_odp_transport_cap_bits {
443 MLX5_ODP_SUPPORT_SEND = 1 << 31,
444 MLX5_ODP_SUPPORT_RECV = 1 << 30,
445 MLX5_ODP_SUPPORT_WRITE = 1 << 29,
446 MLX5_ODP_SUPPORT_READ = 1 << 28,
447};
448
449struct mlx5_odp_caps {
450 char reserved[0x10];
451 struct {
452 __be32 rc_odp_caps;
453 __be32 uc_odp_caps;
454 __be32 ud_odp_caps;
455 } per_transport_caps;
456 char reserved2[0xe4];
457};
458
459struct mlx5_cmd_layout {
460 u8 type;
461 u8 rsvd0[3];
462 __be32 inlen;
463 __be64 in_ptr;
464 __be32 in[4];
465 __be32 out[4];
466 __be64 out_ptr;
467 __be32 outlen;
468 u8 token;
469 u8 sig;
470 u8 rsvd1;
471 u8 status_own;
472};
473
474struct health_buffer {
475 __be32 assert_var[5];
476 __be32 rsvd0[3];
477 __be32 assert_exit_ptr;
478 __be32 assert_callra;
479 __be32 rsvd1[2];
480 __be32 fw_ver;
481 __be32 hw_id;
482 __be32 rsvd2;
483 u8 irisc_index;
484 u8 synd;
485 __be16 ext_synd;
486};
487
488struct mlx5_init_seg {
489 __be32 fw_rev;
490 __be32 cmdif_rev_fw_sub;
491 __be32 rsvd0[2];
492 __be32 cmdq_addr_h;
493 __be32 cmdq_addr_l_sz;
494 __be32 cmd_dbell;
495 __be32 rsvd1[120];
496 __be32 initializing;
497 struct health_buffer health;
498 __be32 rsvd2[880];
499 __be32 internal_timer_h;
500 __be32 internal_timer_l;
501 __be32 rsvd3[2];
502 __be32 health_counter;
503 __be32 rsvd4[1019];
504 __be64 ieee1588_clk;
505 __be32 ieee1588_clk_type;
506 __be32 clr_intx;
507};
508
509struct mlx5_eqe_comp {
510 __be32 reserved[6];
511 __be32 cqn;
512};
513
514struct mlx5_eqe_qp_srq {
515 __be32 reserved1[5];
516 u8 type;
517 u8 reserved2[3];
518 __be32 qp_srq_n;
519};
520
521struct mlx5_eqe_cq_err {
522 __be32 cqn;
523 u8 reserved1[7];
524 u8 syndrome;
525};
526
527struct mlx5_eqe_port_state {
528 u8 reserved0[8];
529 u8 port;
530};
531
532struct mlx5_eqe_gpio {
533 __be32 reserved0[2];
534 __be64 gpio_event;
535};
536
537struct mlx5_eqe_congestion {
538 u8 type;
539 u8 rsvd0;
540 u8 congestion_level;
541};
542
543struct mlx5_eqe_stall_vl {
544 u8 rsvd0[3];
545 u8 port_vl;
546};
547
548struct mlx5_eqe_cmd {
549 __be32 vector;
550 __be32 rsvd[6];
551};
552
553struct mlx5_eqe_page_req {
554 u8 rsvd0[2];
555 __be16 func_id;
556 __be32 num_pages;
557 __be32 rsvd1[5];
558};
559
560struct mlx5_eqe_page_fault {
561 __be32 bytes_committed;
562 union {
563 struct {
564 u16 reserved1;
565 __be16 wqe_index;
566 u16 reserved2;
567 __be16 packet_length;
568 __be32 token;
569 u8 reserved4[8];
570 __be32 pftype_wq;
571 } __packed wqe;
572 struct {
573 __be32 r_key;
574 u16 reserved1;
575 __be16 packet_length;
576 __be32 rdma_op_len;
577 __be64 rdma_va;
578 __be32 pftype_token;
579 } __packed rdma;
580 } __packed;
581} __packed;
582
583struct mlx5_eqe_vport_change {
584 u8 rsvd0[2];
585 __be16 vport_num;
586 __be32 rsvd1[6];
587} __packed;
588
589struct mlx5_eqe_port_module {
590 u8 reserved_at_0[1];
591 u8 module;
592 u8 reserved_at_2[1];
593 u8 module_status;
594 u8 reserved_at_4[2];
595 u8 error_type;
596} __packed;
597
598struct mlx5_eqe_pps {
599 u8 rsvd0[3];
600 u8 pin;
601 u8 rsvd1[4];
602 union {
603 struct {
604 __be32 time_sec;
605 __be32 time_nsec;
606 };
607 struct {
608 __be64 time_stamp;
609 };
610 };
611 u8 rsvd2[12];
612} __packed;
613
614union ev_data {
615 __be32 raw[7];
616 struct mlx5_eqe_cmd cmd;
617 struct mlx5_eqe_comp comp;
618 struct mlx5_eqe_qp_srq qp_srq;
619 struct mlx5_eqe_cq_err cq_err;
620 struct mlx5_eqe_port_state port;
621 struct mlx5_eqe_gpio gpio;
622 struct mlx5_eqe_congestion cong;
623 struct mlx5_eqe_stall_vl stall_vl;
624 struct mlx5_eqe_page_req req_pages;
625 struct mlx5_eqe_page_fault page_fault;
626 struct mlx5_eqe_vport_change vport_change;
627 struct mlx5_eqe_port_module port_module;
628 struct mlx5_eqe_pps pps;
629} __packed;
630
631struct mlx5_eqe {
632 u8 rsvd0;
633 u8 type;
634 u8 rsvd1;
635 u8 sub_type;
636 __be32 rsvd2[7];
637 union ev_data data;
638 __be16 rsvd3;
639 u8 signature;
640 u8 owner;
641} __packed;
642
643struct mlx5_cmd_prot_block {
644 u8 data[MLX5_CMD_DATA_BLOCK_SIZE];
645 u8 rsvd0[48];
646 __be64 next;
647 __be32 block_num;
648 u8 rsvd1;
649 u8 token;
650 u8 ctrl_sig;
651 u8 sig;
652};
653
654enum {
655 MLX5_CQE_SYND_FLUSHED_IN_ERROR = 5,
656};
657
658struct mlx5_err_cqe {
659 u8 rsvd0[32];
660 __be32 srqn;
661 u8 rsvd1[18];
662 u8 vendor_err_synd;
663 u8 syndrome;
664 __be32 s_wqe_opcode_qpn;
665 __be16 wqe_counter;
666 u8 signature;
667 u8 op_own;
668};
669
670struct mlx5_cqe64 {
671 u8 outer_l3_tunneled;
672 u8 rsvd0;
673 __be16 wqe_id;
674 u8 lro_tcppsh_abort_dupack;
675 u8 lro_min_ttl;
676 __be16 lro_tcp_win;
677 __be32 lro_ack_seq_num;
678 __be32 rss_hash_result;
679 u8 rss_hash_type;
680 u8 ml_path;
681 u8 rsvd20[2];
682 __be16 check_sum;
683 __be16 slid;
684 __be32 flags_rqpn;
685 u8 hds_ip_ext;
686 u8 l4_l3_hdr_type;
687 __be16 vlan_info;
688 __be32 srqn; /* [31:24]: lro_num_seg, [23:0]: srqn */
689 __be32 imm_inval_pkey;
690 u8 rsvd40[4];
691 __be32 byte_cnt;
692 __be32 timestamp_h;
693 __be32 timestamp_l;
694 __be32 sop_drop_qpn;
695 __be16 wqe_counter;
696 u8 signature;
697 u8 op_own;
698};
699
700struct mlx5_mini_cqe8 {
701 union {
702 __be32 rx_hash_result;
703 struct {
704 __be16 checksum;
705 __be16 rsvd;
706 };
707 struct {
708 __be16 wqe_counter;
709 u8 s_wqe_opcode;
710 u8 reserved;
711 } s_wqe_info;
712 };
713 __be32 byte_cnt;
714};
715
716enum {
717 MLX5_NO_INLINE_DATA,
718 MLX5_INLINE_DATA32_SEG,
719 MLX5_INLINE_DATA64_SEG,
720 MLX5_COMPRESSED,
721};
722
723enum {
724 MLX5_CQE_FORMAT_CSUM = 0x1,
725};
726
727#define MLX5_MINI_CQE_ARRAY_SIZE 8
728
729static inline int mlx5_get_cqe_format(struct mlx5_cqe64 *cqe)
730{
731 return (cqe->op_own >> 2) & 0x3;
732}
733
734static inline u8 get_cqe_lro_tcppsh(struct mlx5_cqe64 *cqe)
735{
736 return (cqe->lro_tcppsh_abort_dupack >> 6) & 1;
737}
738
739static inline u8 get_cqe_l4_hdr_type(struct mlx5_cqe64 *cqe)
740{
741 return (cqe->l4_l3_hdr_type >> 4) & 0x7;
742}
743
744static inline u8 get_cqe_l3_hdr_type(struct mlx5_cqe64 *cqe)
745{
746 return (cqe->l4_l3_hdr_type >> 2) & 0x3;
747}
748
749static inline u8 cqe_is_tunneled(struct mlx5_cqe64 *cqe)
750{
751 return cqe->outer_l3_tunneled & 0x1;
752}
753
754static inline int cqe_has_vlan(struct mlx5_cqe64 *cqe)
755{
756 return !!(cqe->l4_l3_hdr_type & 0x1);
757}
758
759static inline u64 get_cqe_ts(struct mlx5_cqe64 *cqe)
760{
761 u32 hi, lo;
762
763 hi = be32_to_cpu(cqe->timestamp_h);
764 lo = be32_to_cpu(cqe->timestamp_l);
765
766 return (u64)lo | ((u64)hi << 32);
767}
768
769struct mpwrq_cqe_bc {
770 __be16 filler_consumed_strides;
771 __be16 byte_cnt;
772};
773
774static inline u16 mpwrq_get_cqe_byte_cnt(struct mlx5_cqe64 *cqe)
775{
776 struct mpwrq_cqe_bc *bc = (struct mpwrq_cqe_bc *)&cqe->byte_cnt;
777
778 return be16_to_cpu(bc->byte_cnt);
779}
780
781static inline u16 mpwrq_get_cqe_bc_consumed_strides(struct mpwrq_cqe_bc *bc)
782{
783 return 0x7fff & be16_to_cpu(bc->filler_consumed_strides);
784}
785
786static inline u16 mpwrq_get_cqe_consumed_strides(struct mlx5_cqe64 *cqe)
787{
788 struct mpwrq_cqe_bc *bc = (struct mpwrq_cqe_bc *)&cqe->byte_cnt;
789
790 return mpwrq_get_cqe_bc_consumed_strides(bc);
791}
792
793static inline bool mpwrq_is_filler_cqe(struct mlx5_cqe64 *cqe)
794{
795 struct mpwrq_cqe_bc *bc = (struct mpwrq_cqe_bc *)&cqe->byte_cnt;
796
797 return 0x8000 & be16_to_cpu(bc->filler_consumed_strides);
798}
799
800static inline u16 mpwrq_get_cqe_stride_index(struct mlx5_cqe64 *cqe)
801{
802 return be16_to_cpu(cqe->wqe_counter);
803}
804
805enum {
806 CQE_L4_HDR_TYPE_NONE = 0x0,
807 CQE_L4_HDR_TYPE_TCP_NO_ACK = 0x1,
808 CQE_L4_HDR_TYPE_UDP = 0x2,
809 CQE_L4_HDR_TYPE_TCP_ACK_NO_DATA = 0x3,
810 CQE_L4_HDR_TYPE_TCP_ACK_AND_DATA = 0x4,
811};
812
813enum {
814 CQE_RSS_HTYPE_IP = 0x3 << 2,
815 /* cqe->rss_hash_type[3:2] - IP destination selected for hash
816 * (00 = none, 01 = IPv4, 10 = IPv6, 11 = Reserved)
817 */
818 CQE_RSS_HTYPE_L4 = 0x3 << 6,
819 /* cqe->rss_hash_type[7:6] - L4 destination selected for hash
820 * (00 = none, 01 = TCP. 10 = UDP, 11 = IPSEC.SPI
821 */
822};
823
824enum {
825 MLX5_CQE_ROCE_L3_HEADER_TYPE_GRH = 0x0,
826 MLX5_CQE_ROCE_L3_HEADER_TYPE_IPV6 = 0x1,
827 MLX5_CQE_ROCE_L3_HEADER_TYPE_IPV4 = 0x2,
828};
829
830enum {
831 CQE_L2_OK = 1 << 0,
832 CQE_L3_OK = 1 << 1,
833 CQE_L4_OK = 1 << 2,
834};
835
836struct mlx5_sig_err_cqe {
837 u8 rsvd0[16];
838 __be32 expected_trans_sig;
839 __be32 actual_trans_sig;
840 __be32 expected_reftag;
841 __be32 actual_reftag;
842 __be16 syndrome;
843 u8 rsvd22[2];
844 __be32 mkey;
845 __be64 err_offset;
846 u8 rsvd30[8];
847 __be32 qpn;
848 u8 rsvd38[2];
849 u8 signature;
850 u8 op_own;
851};
852
853struct mlx5_wqe_srq_next_seg {
854 u8 rsvd0[2];
855 __be16 next_wqe_index;
856 u8 signature;
857 u8 rsvd1[11];
858};
859
860union mlx5_ext_cqe {
861 struct ib_grh grh;
862 u8 inl[64];
863};
864
865struct mlx5_cqe128 {
866 union mlx5_ext_cqe inl_grh;
867 struct mlx5_cqe64 cqe64;
868};
869
870enum {
871 MLX5_MKEY_STATUS_FREE = 1 << 6,
872};
873
874enum {
875 MLX5_MKEY_REMOTE_INVAL = 1 << 24,
876 MLX5_MKEY_FLAG_SYNC_UMR = 1 << 29,
877 MLX5_MKEY_BSF_EN = 1 << 30,
878 MLX5_MKEY_LEN64 = 1 << 31,
879};
880
881struct mlx5_mkey_seg {
882 /* This is a two bit field occupying bits 31-30.
883 * bit 31 is always 0,
884 * bit 30 is zero for regular MRs and 1 (e.g free) for UMRs that do not have tanslation
885 */
886 u8 status;
887 u8 pcie_control;
888 u8 flags;
889 u8 version;
890 __be32 qpn_mkey7_0;
891 u8 rsvd1[4];
892 __be32 flags_pd;
893 __be64 start_addr;
894 __be64 len;
895 __be32 bsfs_octo_size;
896 u8 rsvd2[16];
897 __be32 xlt_oct_size;
898 u8 rsvd3[3];
899 u8 log2_page_size;
900 u8 rsvd4[4];
901};
902
903#define MLX5_ATTR_EXTENDED_PORT_INFO cpu_to_be16(0xff90)
904
905enum {
906 MLX_EXT_PORT_CAP_FLAG_EXTENDED_PORT_INFO = 1 << 0
907};
908
909enum {
910 VPORT_STATE_DOWN = 0x0,
911 VPORT_STATE_UP = 0x1,
912};
913
914enum {
915 MLX5_ESW_VPORT_ADMIN_STATE_DOWN = 0x0,
916 MLX5_ESW_VPORT_ADMIN_STATE_UP = 0x1,
917 MLX5_ESW_VPORT_ADMIN_STATE_AUTO = 0x2,
918};
919
920enum {
921 MLX5_L3_PROT_TYPE_IPV4 = 0,
922 MLX5_L3_PROT_TYPE_IPV6 = 1,
923};
924
925enum {
926 MLX5_L4_PROT_TYPE_TCP = 0,
927 MLX5_L4_PROT_TYPE_UDP = 1,
928};
929
930enum {
931 MLX5_HASH_FIELD_SEL_SRC_IP = 1 << 0,
932 MLX5_HASH_FIELD_SEL_DST_IP = 1 << 1,
933 MLX5_HASH_FIELD_SEL_L4_SPORT = 1 << 2,
934 MLX5_HASH_FIELD_SEL_L4_DPORT = 1 << 3,
935 MLX5_HASH_FIELD_SEL_IPSEC_SPI = 1 << 4,
936};
937
938enum {
939 MLX5_MATCH_OUTER_HEADERS = 1 << 0,
940 MLX5_MATCH_MISC_PARAMETERS = 1 << 1,
941 MLX5_MATCH_INNER_HEADERS = 1 << 2,
942
943};
944
945enum {
946 MLX5_FLOW_TABLE_TYPE_NIC_RCV = 0,
947 MLX5_FLOW_TABLE_TYPE_ESWITCH = 4,
948};
949
950enum {
951 MLX5_FLOW_CONTEXT_DEST_TYPE_VPORT = 0,
952 MLX5_FLOW_CONTEXT_DEST_TYPE_FLOW_TABLE = 1,
953 MLX5_FLOW_CONTEXT_DEST_TYPE_TIR = 2,
954};
955
956enum mlx5_list_type {
957 MLX5_NVPRT_LIST_TYPE_UC = 0x0,
958 MLX5_NVPRT_LIST_TYPE_MC = 0x1,
959 MLX5_NVPRT_LIST_TYPE_VLAN = 0x2,
960};
961
962enum {
963 MLX5_RQC_RQ_TYPE_MEMORY_RQ_INLINE = 0x0,
964 MLX5_RQC_RQ_TYPE_MEMORY_RQ_RPM = 0x1,
965};
966
967enum mlx5_wol_mode {
968 MLX5_WOL_DISABLE = 0,
969 MLX5_WOL_SECURED_MAGIC = 1 << 1,
970 MLX5_WOL_MAGIC = 1 << 2,
971 MLX5_WOL_ARP = 1 << 3,
972 MLX5_WOL_BROADCAST = 1 << 4,
973 MLX5_WOL_MULTICAST = 1 << 5,
974 MLX5_WOL_UNICAST = 1 << 6,
975 MLX5_WOL_PHY_ACTIVITY = 1 << 7,
976};
977
978/* MLX5 DEV CAPs */
979
980/* TODO: EAT.ME */
981enum mlx5_cap_mode {
982 HCA_CAP_OPMOD_GET_MAX = 0,
983 HCA_CAP_OPMOD_GET_CUR = 1,
984};
985
986enum mlx5_cap_type {
987 MLX5_CAP_GENERAL = 0,
988 MLX5_CAP_ETHERNET_OFFLOADS,
989 MLX5_CAP_ODP,
990 MLX5_CAP_ATOMIC,
991 MLX5_CAP_ROCE,
992 MLX5_CAP_IPOIB_OFFLOADS,
993 MLX5_CAP_IPOIB_ENHANCED_OFFLOADS,
994 MLX5_CAP_FLOW_TABLE,
995 MLX5_CAP_ESWITCH_FLOW_TABLE,
996 MLX5_CAP_ESWITCH,
997 MLX5_CAP_RESERVED,
998 MLX5_CAP_VECTOR_CALC,
999 MLX5_CAP_QOS,
1000 /* NUM OF CAP Types */
1001 MLX5_CAP_NUM
1002};
1003
1004enum mlx5_pcam_reg_groups {
1005 MLX5_PCAM_REGS_5000_TO_507F = 0x0,
1006};
1007
1008enum mlx5_pcam_feature_groups {
1009 MLX5_PCAM_FEATURE_ENHANCED_FEATURES = 0x0,
1010};
1011
1012enum mlx5_mcam_reg_groups {
1013 MLX5_MCAM_REGS_FIRST_128 = 0x0,
1014};
1015
1016enum mlx5_mcam_feature_groups {
1017 MLX5_MCAM_FEATURE_ENHANCED_FEATURES = 0x0,
1018};
1019
1020enum mlx5_qcam_reg_groups {
1021 MLX5_QCAM_REGS_FIRST_128 = 0x0,
1022};
1023
1024enum mlx5_qcam_feature_groups {
1025 MLX5_QCAM_FEATURE_ENHANCED_FEATURES = 0x0,
1026};
1027
1028/* GET Dev Caps macros */
1029#define MLX5_CAP_GEN(mdev, cap) \
1030 MLX5_GET(cmd_hca_cap, mdev->caps.hca_cur[MLX5_CAP_GENERAL], cap)
1031
1032#define MLX5_CAP_GEN_MAX(mdev, cap) \
1033 MLX5_GET(cmd_hca_cap, mdev->caps.hca_max[MLX5_CAP_GENERAL], cap)
1034
1035#define MLX5_CAP_ETH(mdev, cap) \
1036 MLX5_GET(per_protocol_networking_offload_caps,\
1037 mdev->caps.hca_cur[MLX5_CAP_ETHERNET_OFFLOADS], cap)
1038
1039#define MLX5_CAP_ETH_MAX(mdev, cap) \
1040 MLX5_GET(per_protocol_networking_offload_caps,\
1041 mdev->caps.hca_max[MLX5_CAP_ETHERNET_OFFLOADS], cap)
1042
1043#define MLX5_CAP_IPOIB_ENHANCED(mdev, cap) \
1044 MLX5_GET(per_protocol_networking_offload_caps,\
1045 mdev->caps.hca_cur[MLX5_CAP_IPOIB_ENHANCED_OFFLOADS], cap)
1046
1047#define MLX5_CAP_ROCE(mdev, cap) \
1048 MLX5_GET(roce_cap, mdev->caps.hca_cur[MLX5_CAP_ROCE], cap)
1049
1050#define MLX5_CAP_ROCE_MAX(mdev, cap) \
1051 MLX5_GET(roce_cap, mdev->caps.hca_max[MLX5_CAP_ROCE], cap)
1052
1053#define MLX5_CAP_ATOMIC(mdev, cap) \
1054 MLX5_GET(atomic_caps, mdev->caps.hca_cur[MLX5_CAP_ATOMIC], cap)
1055
1056#define MLX5_CAP_ATOMIC_MAX(mdev, cap) \
1057 MLX5_GET(atomic_caps, mdev->caps.hca_max[MLX5_CAP_ATOMIC], cap)
1058
1059#define MLX5_CAP_FLOWTABLE(mdev, cap) \
1060 MLX5_GET(flow_table_nic_cap, mdev->caps.hca_cur[MLX5_CAP_FLOW_TABLE], cap)
1061
1062#define MLX5_CAP_FLOWTABLE_MAX(mdev, cap) \
1063 MLX5_GET(flow_table_nic_cap, mdev->caps.hca_max[MLX5_CAP_FLOW_TABLE], cap)
1064
1065#define MLX5_CAP_FLOWTABLE_NIC_RX(mdev, cap) \
1066 MLX5_CAP_FLOWTABLE(mdev, flow_table_properties_nic_receive.cap)
1067
1068#define MLX5_CAP_FLOWTABLE_NIC_RX_MAX(mdev, cap) \
1069 MLX5_CAP_FLOWTABLE_MAX(mdev, flow_table_properties_nic_receive.cap)
1070
1071#define MLX5_CAP_FLOWTABLE_SNIFFER_RX(mdev, cap) \
1072 MLX5_CAP_FLOWTABLE(mdev, flow_table_properties_nic_receive_sniffer.cap)
1073
1074#define MLX5_CAP_FLOWTABLE_SNIFFER_RX_MAX(mdev, cap) \
1075 MLX5_CAP_FLOWTABLE_MAX(mdev, flow_table_properties_nic_receive_sniffer.cap)
1076
1077#define MLX5_CAP_FLOWTABLE_SNIFFER_TX(mdev, cap) \
1078 MLX5_CAP_FLOWTABLE(mdev, flow_table_properties_nic_transmit_sniffer.cap)
1079
1080#define MLX5_CAP_FLOWTABLE_SNIFFER_TX_MAX(mdev, cap) \
1081 MLX5_CAP_FLOWTABLE_MAX(mdev, flow_table_properties_nic_transmit_sniffer.cap)
1082
1083#define MLX5_CAP_ESW_FLOWTABLE(mdev, cap) \
1084 MLX5_GET(flow_table_eswitch_cap, \
1085 mdev->caps.hca_cur[MLX5_CAP_ESWITCH_FLOW_TABLE], cap)
1086
1087#define MLX5_CAP_ESW_FLOWTABLE_MAX(mdev, cap) \
1088 MLX5_GET(flow_table_eswitch_cap, \
1089 mdev->caps.hca_max[MLX5_CAP_ESWITCH_FLOW_TABLE], cap)
1090
1091#define MLX5_CAP_ESW_FLOWTABLE_FDB(mdev, cap) \
1092 MLX5_CAP_ESW_FLOWTABLE(mdev, flow_table_properties_nic_esw_fdb.cap)
1093
1094#define MLX5_CAP_ESW_FLOWTABLE_FDB_MAX(mdev, cap) \
1095 MLX5_CAP_ESW_FLOWTABLE_MAX(mdev, flow_table_properties_nic_esw_fdb.cap)
1096
1097#define MLX5_CAP_ESW_EGRESS_ACL(mdev, cap) \
1098 MLX5_CAP_ESW_FLOWTABLE(mdev, flow_table_properties_esw_acl_egress.cap)
1099
1100#define MLX5_CAP_ESW_EGRESS_ACL_MAX(mdev, cap) \
1101 MLX5_CAP_ESW_FLOWTABLE_MAX(mdev, flow_table_properties_esw_acl_egress.cap)
1102
1103#define MLX5_CAP_ESW_INGRESS_ACL(mdev, cap) \
1104 MLX5_CAP_ESW_FLOWTABLE(mdev, flow_table_properties_esw_acl_ingress.cap)
1105
1106#define MLX5_CAP_ESW_INGRESS_ACL_MAX(mdev, cap) \
1107 MLX5_CAP_ESW_FLOWTABLE_MAX(mdev, flow_table_properties_esw_acl_ingress.cap)
1108
1109#define MLX5_CAP_ESW(mdev, cap) \
1110 MLX5_GET(e_switch_cap, \
1111 mdev->caps.hca_cur[MLX5_CAP_ESWITCH], cap)
1112
1113#define MLX5_CAP_ESW_MAX(mdev, cap) \
1114 MLX5_GET(e_switch_cap, \
1115 mdev->caps.hca_max[MLX5_CAP_ESWITCH], cap)
1116
1117#define MLX5_CAP_ODP(mdev, cap)\
1118 MLX5_GET(odp_cap, mdev->caps.hca_cur[MLX5_CAP_ODP], cap)
1119
1120#define MLX5_CAP_VECTOR_CALC(mdev, cap) \
1121 MLX5_GET(vector_calc_cap, \
1122 mdev->caps.hca_cur[MLX5_CAP_VECTOR_CALC], cap)
1123
1124#define MLX5_CAP_QOS(mdev, cap)\
1125 MLX5_GET(qos_cap, mdev->caps.hca_cur[MLX5_CAP_QOS], cap)
1126
1127#define MLX5_CAP_PCAM_FEATURE(mdev, fld) \
1128 MLX5_GET(pcam_reg, (mdev)->caps.pcam, feature_cap_mask.enhanced_features.fld)
1129
1130#define MLX5_CAP_MCAM_REG(mdev, reg) \
1131 MLX5_GET(mcam_reg, (mdev)->caps.mcam, mng_access_reg_cap_mask.access_regs.reg)
1132
1133#define MLX5_CAP_MCAM_FEATURE(mdev, fld) \
1134 MLX5_GET(mcam_reg, (mdev)->caps.mcam, mng_feature_cap_mask.enhanced_features.fld)
1135
1136#define MLX5_CAP_QCAM_REG(mdev, fld) \
1137 MLX5_GET(qcam_reg, (mdev)->caps.qcam, qos_access_reg_cap_mask.reg_cap.fld)
1138
1139#define MLX5_CAP_QCAM_FEATURE(mdev, fld) \
1140 MLX5_GET(qcam_reg, (mdev)->caps.qcam, qos_feature_cap_mask.feature_cap.fld)
1141
1142#define MLX5_CAP_FPGA(mdev, cap) \
1143 MLX5_GET(fpga_cap, (mdev)->caps.fpga, cap)
1144
1145#define MLX5_CAP64_FPGA(mdev, cap) \
1146 MLX5_GET64(fpga_cap, (mdev)->caps.fpga, cap)
1147
1148enum {
1149 MLX5_CMD_STAT_OK = 0x0,
1150 MLX5_CMD_STAT_INT_ERR = 0x1,
1151 MLX5_CMD_STAT_BAD_OP_ERR = 0x2,
1152 MLX5_CMD_STAT_BAD_PARAM_ERR = 0x3,
1153 MLX5_CMD_STAT_BAD_SYS_STATE_ERR = 0x4,
1154 MLX5_CMD_STAT_BAD_RES_ERR = 0x5,
1155 MLX5_CMD_STAT_RES_BUSY = 0x6,
1156 MLX5_CMD_STAT_LIM_ERR = 0x8,
1157 MLX5_CMD_STAT_BAD_RES_STATE_ERR = 0x9,
1158 MLX5_CMD_STAT_IX_ERR = 0xa,
1159 MLX5_CMD_STAT_NO_RES_ERR = 0xf,
1160 MLX5_CMD_STAT_BAD_INP_LEN_ERR = 0x50,
1161 MLX5_CMD_STAT_BAD_OUTP_LEN_ERR = 0x51,
1162 MLX5_CMD_STAT_BAD_QP_STATE_ERR = 0x10,
1163 MLX5_CMD_STAT_BAD_PKT_ERR = 0x30,
1164 MLX5_CMD_STAT_BAD_SIZE_OUTS_CQES_ERR = 0x40,
1165};
1166
1167enum {
1168 MLX5_IEEE_802_3_COUNTERS_GROUP = 0x0,
1169 MLX5_RFC_2863_COUNTERS_GROUP = 0x1,
1170 MLX5_RFC_2819_COUNTERS_GROUP = 0x2,
1171 MLX5_RFC_3635_COUNTERS_GROUP = 0x3,
1172 MLX5_ETHERNET_EXTENDED_COUNTERS_GROUP = 0x5,
1173 MLX5_PER_PRIORITY_COUNTERS_GROUP = 0x10,
1174 MLX5_PER_TRAFFIC_CLASS_COUNTERS_GROUP = 0x11,
1175 MLX5_PHYSICAL_LAYER_COUNTERS_GROUP = 0x12,
1176 MLX5_PHYSICAL_LAYER_STATISTICAL_GROUP = 0x16,
1177 MLX5_INFINIBAND_PORT_COUNTERS_GROUP = 0x20,
1178};
1179
1180enum {
1181 MLX5_PCIE_PERFORMANCE_COUNTERS_GROUP = 0x0,
1182};
1183
1184static inline u16 mlx5_to_sw_pkey_sz(int pkey_sz)
1185{
1186 if (pkey_sz > MLX5_MAX_LOG_PKEY_TABLE)
1187 return 0;
1188 return MLX5_MIN_PKEY_TABLE_SIZE << pkey_sz;
1189}
1190
1191#define MLX5_BY_PASS_NUM_REGULAR_PRIOS 8
1192#define MLX5_BY_PASS_NUM_DONT_TRAP_PRIOS 8
1193#define MLX5_BY_PASS_NUM_MULTICAST_PRIOS 1
1194#define MLX5_BY_PASS_NUM_PRIOS (MLX5_BY_PASS_NUM_REGULAR_PRIOS +\
1195 MLX5_BY_PASS_NUM_DONT_TRAP_PRIOS +\
1196 MLX5_BY_PASS_NUM_MULTICAST_PRIOS)
1197
1198#endif /* MLX5_DEVICE_H */