tjh.dev
Linux kernel mirror (for testing)
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linux
1/* SPDX-License-Identifier: GPL-2.0 */
2/*
3 * ATI Frame Buffer Device Driver Core Definitions
4 */
5
6#include <linux/spinlock.h>
7#include <linux/wait.h>
8 /*
9 * Elements of the hardware specific atyfb_par structure
10 */
11
12struct crtc {
13 u32 vxres;
14 u32 vyres;
15 u32 xoffset;
16 u32 yoffset;
17 u32 bpp;
18 u32 h_tot_disp;
19 u32 h_sync_strt_wid;
20 u32 v_tot_disp;
21 u32 v_sync_strt_wid;
22 u32 vline_crnt_vline;
23 u32 off_pitch;
24 u32 gen_cntl;
25 u32 dp_pix_width; /* acceleration */
26 u32 dp_chain_mask; /* acceleration */
27#ifdef CONFIG_FB_ATY_GENERIC_LCD
28 u32 horz_stretching;
29 u32 vert_stretching;
30 u32 ext_vert_stretch;
31 u32 shadow_h_tot_disp;
32 u32 shadow_h_sync_strt_wid;
33 u32 shadow_v_tot_disp;
34 u32 shadow_v_sync_strt_wid;
35 u32 lcd_gen_cntl;
36 u32 lcd_config_panel;
37 u32 lcd_index;
38#endif
39};
40
41struct aty_interrupt {
42 wait_queue_head_t wait;
43 unsigned int count;
44 int pan_display;
45};
46
47struct pll_info {
48 int pll_max;
49 int pll_min;
50 int sclk, mclk, mclk_pm, xclk;
51 int ref_div;
52 int ref_clk;
53 int ecp_max;
54};
55
56typedef struct {
57 u16 unknown1;
58 u16 PCLK_min_freq;
59 u16 PCLK_max_freq;
60 u16 unknown2;
61 u16 ref_freq;
62 u16 ref_divider;
63 u16 unknown3;
64 u16 MCLK_pwd;
65 u16 MCLK_max_freq;
66 u16 XCLK_max_freq;
67 u16 SCLK_freq;
68} __attribute__ ((packed)) PLL_BLOCK_MACH64;
69
70struct pll_514 {
71 u8 m;
72 u8 n;
73};
74
75struct pll_18818 {
76 u32 program_bits;
77 u32 locationAddr;
78 u32 period_in_ps;
79 u32 post_divider;
80};
81
82struct pll_ct {
83 u8 pll_ref_div;
84 u8 pll_gen_cntl;
85 u8 mclk_fb_div;
86 u8 mclk_fb_mult; /* 2 ro 4 */
87 u8 sclk_fb_div;
88 u8 pll_vclk_cntl;
89 u8 vclk_post_div;
90 u8 vclk_fb_div;
91 u8 pll_ext_cntl;
92 u8 ext_vpll_cntl;
93 u8 spll_cntl2;
94 u32 dsp_config; /* Mach64 GTB DSP */
95 u32 dsp_on_off; /* Mach64 GTB DSP */
96 u32 dsp_loop_latency;
97 u32 fifo_size;
98 u32 xclkpagefaultdelay;
99 u32 xclkmaxrasdelay;
100 u8 xclk_ref_div;
101 u8 xclk_post_div;
102 u8 mclk_post_div_real;
103 u8 xclk_post_div_real;
104 u8 vclk_post_div_real;
105 u8 features;
106#ifdef CONFIG_FB_ATY_GENERIC_LCD
107 u32 xres; /* use for LCD stretching/scaling */
108#endif
109};
110
111/*
112 for pll_ct.features
113*/
114#define DONT_USE_SPLL 0x1
115#define DONT_USE_XDLL 0x2
116#define USE_CPUCLK 0x4
117#define POWERDOWN_PLL 0x8
118
119union aty_pll {
120 struct pll_ct ct;
121 struct pll_514 ibm514;
122 struct pll_18818 ics2595;
123};
124
125 /*
126 * The hardware parameters for each card
127 */
128
129struct atyfb_par {
130 u32 pseudo_palette[16];
131 struct { u8 red, green, blue; } palette[256];
132 const struct aty_dac_ops *dac_ops;
133 const struct aty_pll_ops *pll_ops;
134 void __iomem *ati_regbase;
135 unsigned long clk_wr_offset; /* meaning overloaded, clock id by CT */
136 struct crtc crtc;
137 union aty_pll pll;
138 struct pll_info pll_limits;
139 u32 features;
140 u32 ref_clk_per;
141 u32 pll_per;
142 u32 mclk_per;
143 u32 xclk_per;
144 u8 bus_type;
145 u8 ram_type;
146 u8 mem_refresh_rate;
147 u16 pci_id;
148 u32 accel_flags;
149 int blitter_may_be_busy;
150 int asleep;
151 int lock_blank;
152 unsigned long res_start;
153 unsigned long res_size;
154 struct pci_dev *pdev;
155#ifdef __sparc__
156 struct pci_mmap_map *mmap_map;
157 u8 mmaped;
158#endif
159 int open;
160#ifdef CONFIG_FB_ATY_GENERIC_LCD
161 unsigned long bios_base_phys;
162 unsigned long bios_base;
163 unsigned long lcd_table;
164 u16 lcd_width;
165 u16 lcd_height;
166 u32 lcd_pixclock;
167 u16 lcd_refreshrate;
168 u16 lcd_htotal;
169 u16 lcd_hdisp;
170 u16 lcd_hsync_dly;
171 u16 lcd_hsync_len;
172 u16 lcd_vtotal;
173 u16 lcd_vdisp;
174 u16 lcd_vsync_len;
175 u16 lcd_right_margin;
176 u16 lcd_lower_margin;
177 u16 lcd_hblank_len;
178 u16 lcd_vblank_len;
179#endif
180 unsigned long aux_start; /* auxiliary aperture */
181 unsigned long aux_size;
182 struct aty_interrupt vblank;
183 unsigned long irq_flags;
184 unsigned int irq;
185 spinlock_t int_lock;
186 int wc_cookie;
187 u32 mem_cntl;
188 struct crtc saved_crtc;
189 union aty_pll saved_pll;
190};
191
192 /*
193 * ATI Mach64 features
194 */
195
196#define M64_HAS(feature) ((par)->features & (M64F_##feature))
197
198#define M64F_RESET_3D 0x00000001
199#define M64F_MAGIC_FIFO 0x00000002
200#define M64F_GTB_DSP 0x00000004
201#define M64F_FIFO_32 0x00000008
202#define M64F_SDRAM_MAGIC_PLL 0x00000010
203#define M64F_MAGIC_POSTDIV 0x00000020
204#define M64F_INTEGRATED 0x00000040
205#define M64F_CT_BUS 0x00000080
206#define M64F_VT_BUS 0x00000100
207#define M64F_MOBIL_BUS 0x00000200
208#define M64F_GX 0x00000400
209#define M64F_CT 0x00000800
210#define M64F_VT 0x00001000
211#define M64F_GT 0x00002000
212#define M64F_MAGIC_VRAM_SIZE 0x00004000
213#define M64F_G3_PB_1_1 0x00008000
214#define M64F_G3_PB_1024x768 0x00010000
215#define M64F_EXTRA_BRIGHT 0x00020000
216#define M64F_LT_LCD_REGS 0x00040000
217#define M64F_XL_DLL 0x00080000
218#define M64F_MFB_FORCE_4 0x00100000
219#define M64F_HW_TRIPLE 0x00200000
220#define M64F_XL_MEM 0x00400000
221 /*
222 * Register access
223 */
224
225static inline u32 aty_ld_le32(int regindex, const struct atyfb_par *par)
226{
227 /* Hack for bloc 1, should be cleanly optimized by compiler */
228 if (regindex >= 0x400)
229 regindex -= 0x800;
230
231#ifdef CONFIG_ATARI
232 return in_le32(par->ati_regbase + regindex);
233#else
234 return readl(par->ati_regbase + regindex);
235#endif
236}
237
238static inline void aty_st_le32(int regindex, u32 val, const struct atyfb_par *par)
239{
240 /* Hack for bloc 1, should be cleanly optimized by compiler */
241 if (regindex >= 0x400)
242 regindex -= 0x800;
243
244#ifdef CONFIG_ATARI
245 out_le32(par->ati_regbase + regindex, val);
246#else
247 writel(val, par->ati_regbase + regindex);
248#endif
249}
250
251static inline void aty_st_le16(int regindex, u16 val,
252 const struct atyfb_par *par)
253{
254 /* Hack for bloc 1, should be cleanly optimized by compiler */
255 if (regindex >= 0x400)
256 regindex -= 0x800;
257#ifdef CONFIG_ATARI
258 out_le16(par->ati_regbase + regindex, val);
259#else
260 writel(val, par->ati_regbase + regindex);
261#endif
262}
263
264static inline u8 aty_ld_8(int regindex, const struct atyfb_par *par)
265{
266 /* Hack for bloc 1, should be cleanly optimized by compiler */
267 if (regindex >= 0x400)
268 regindex -= 0x800;
269#ifdef CONFIG_ATARI
270 return in_8(par->ati_regbase + regindex);
271#else
272 return readb(par->ati_regbase + regindex);
273#endif
274}
275
276static inline void aty_st_8(int regindex, u8 val, const struct atyfb_par *par)
277{
278 /* Hack for bloc 1, should be cleanly optimized by compiler */
279 if (regindex >= 0x400)
280 regindex -= 0x800;
281
282#ifdef CONFIG_ATARI
283 out_8(par->ati_regbase + regindex, val);
284#else
285 writeb(val, par->ati_regbase + regindex);
286#endif
287}
288
289#if defined(CONFIG_PM) || defined(CONFIG_PMAC_BACKLIGHT) || \
290defined (CONFIG_FB_ATY_GENERIC_LCD) || defined (CONFIG_FB_ATY_BACKLIGHT)
291extern void aty_st_lcd(int index, u32 val, const struct atyfb_par *par);
292extern u32 aty_ld_lcd(int index, const struct atyfb_par *par);
293#endif
294
295 /*
296 * DAC operations
297 */
298
299struct aty_dac_ops {
300 int (*set_dac) (const struct fb_info * info,
301 const union aty_pll * pll, u32 bpp, u32 accel);
302};
303
304extern const struct aty_dac_ops aty_dac_ibm514; /* IBM RGB514 */
305extern const struct aty_dac_ops aty_dac_ati68860b; /* ATI 68860-B */
306extern const struct aty_dac_ops aty_dac_att21c498; /* AT&T 21C498 */
307extern const struct aty_dac_ops aty_dac_unsupported; /* unsupported */
308extern const struct aty_dac_ops aty_dac_ct; /* Integrated */
309
310
311 /*
312 * Clock operations
313 */
314
315struct aty_pll_ops {
316 int (*var_to_pll) (const struct fb_info * info, u32 vclk_per, u32 bpp, union aty_pll * pll);
317 u32 (*pll_to_var) (const struct fb_info * info, const union aty_pll * pll);
318 void (*set_pll) (const struct fb_info * info, const union aty_pll * pll);
319 void (*get_pll) (const struct fb_info *info, union aty_pll * pll);
320 int (*init_pll) (const struct fb_info * info, union aty_pll * pll);
321 void (*resume_pll)(const struct fb_info *info, union aty_pll *pll);
322};
323
324extern const struct aty_pll_ops aty_pll_ati18818_1; /* ATI 18818 */
325extern const struct aty_pll_ops aty_pll_stg1703; /* STG 1703 */
326extern const struct aty_pll_ops aty_pll_ch8398; /* Chrontel 8398 */
327extern const struct aty_pll_ops aty_pll_att20c408; /* AT&T 20C408 */
328extern const struct aty_pll_ops aty_pll_ibm514; /* IBM RGB514 */
329extern const struct aty_pll_ops aty_pll_unsupported; /* unsupported */
330extern const struct aty_pll_ops aty_pll_ct; /* Integrated */
331
332
333extern void aty_set_pll_ct(const struct fb_info *info, const union aty_pll *pll);
334extern u8 aty_ld_pll_ct(int offset, const struct atyfb_par *par);
335
336
337 /*
338 * Hardware cursor support
339 */
340
341extern int aty_init_cursor(struct fb_info *info);
342
343 /*
344 * Hardware acceleration
345 */
346
347static inline void wait_for_fifo(u16 entries, const struct atyfb_par *par)
348{
349 while ((aty_ld_le32(FIFO_STAT, par) & 0xffff) >
350 ((u32) (0x8000 >> entries)));
351}
352
353static inline void wait_for_idle(struct atyfb_par *par)
354{
355 wait_for_fifo(16, par);
356 while ((aty_ld_le32(GUI_STAT, par) & 1) != 0);
357 par->blitter_may_be_busy = 0;
358}
359
360extern void aty_reset_engine(const struct atyfb_par *par);
361extern void aty_init_engine(struct atyfb_par *par, struct fb_info *info);
362extern u8 aty_ld_pll_ct(int offset, const struct atyfb_par *par);
363
364void atyfb_copyarea(struct fb_info *info, const struct fb_copyarea *area);
365void atyfb_fillrect(struct fb_info *info, const struct fb_fillrect *rect);
366void atyfb_imageblit(struct fb_info *info, const struct fb_image *image);
367