tjh.dev
Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
1/*
2 * ti_hdmi_4xxx_ip.c
3 *
4 * HDMI TI81xx, TI38xx, TI OMAP4 etc IP driver Library
5 * Copyright (C) 2010-2011 Texas Instruments Incorporated - http://www.ti.com/
6 * Authors: Yong Zhi
7 * Mythri pk <mythripk@ti.com>
8 *
9 * This program is free software; you can redistribute it and/or modify it
10 * under the terms of the GNU General Public License version 2 as published by
11 * the Free Software Foundation.
12 *
13 * This program is distributed in the hope that it will be useful, but WITHOUT
14 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
15 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
16 * more details.
17 *
18 * You should have received a copy of the GNU General Public License along with
19 * this program. If not, see <http://www.gnu.org/licenses/>.
20 */
21
22#define DSS_SUBSYS_NAME "HDMICORE"
23
24#include <linux/kernel.h>
25#include <linux/module.h>
26#include <linux/err.h>
27#include <linux/io.h>
28#include <linux/interrupt.h>
29#include <linux/mutex.h>
30#include <linux/delay.h>
31#include <linux/platform_device.h>
32#include <linux/string.h>
33#include <linux/seq_file.h>
34#include <linux/sys_soc.h>
35#include <sound/asound.h>
36#include <sound/asoundef.h>
37
38#include "hdmi4_core.h"
39
40#define HDMI_CORE_AV 0x500
41
42static inline void __iomem *hdmi_av_base(struct hdmi_core_data *core)
43{
44 return core->base + HDMI_CORE_AV;
45}
46
47static int hdmi_core_ddc_init(struct hdmi_core_data *core)
48{
49 void __iomem *base = core->base;
50
51 /* Turn on CLK for DDC */
52 REG_FLD_MOD(base, HDMI_CORE_AV_DPD, 0x7, 2, 0);
53
54 /* IN_PROG */
55 if (REG_GET(base, HDMI_CORE_DDC_STATUS, 4, 4) == 1) {
56 /* Abort transaction */
57 REG_FLD_MOD(base, HDMI_CORE_DDC_CMD, 0xf, 3, 0);
58 /* IN_PROG */
59 if (hdmi_wait_for_bit_change(base, HDMI_CORE_DDC_STATUS,
60 4, 4, 0) != 0) {
61 DSSERR("Timeout aborting DDC transaction\n");
62 return -ETIMEDOUT;
63 }
64 }
65
66 /* Clk SCL Devices */
67 REG_FLD_MOD(base, HDMI_CORE_DDC_CMD, 0xA, 3, 0);
68
69 /* HDMI_CORE_DDC_STATUS_IN_PROG */
70 if (hdmi_wait_for_bit_change(base, HDMI_CORE_DDC_STATUS,
71 4, 4, 0) != 0) {
72 DSSERR("Timeout starting SCL clock\n");
73 return -ETIMEDOUT;
74 }
75
76 /* Clear FIFO */
77 REG_FLD_MOD(base, HDMI_CORE_DDC_CMD, 0x9, 3, 0);
78
79 /* HDMI_CORE_DDC_STATUS_IN_PROG */
80 if (hdmi_wait_for_bit_change(base, HDMI_CORE_DDC_STATUS,
81 4, 4, 0) != 0) {
82 DSSERR("Timeout clearing DDC fifo\n");
83 return -ETIMEDOUT;
84 }
85
86 return 0;
87}
88
89static int hdmi_core_ddc_edid(struct hdmi_core_data *core,
90 u8 *pedid, int ext)
91{
92 void __iomem *base = core->base;
93 u32 i;
94 char checksum;
95 u32 offset = 0;
96
97 /* HDMI_CORE_DDC_STATUS_IN_PROG */
98 if (hdmi_wait_for_bit_change(base, HDMI_CORE_DDC_STATUS,
99 4, 4, 0) != 0) {
100 DSSERR("Timeout waiting DDC to be ready\n");
101 return -ETIMEDOUT;
102 }
103
104 if (ext % 2 != 0)
105 offset = 0x80;
106
107 /* Load Segment Address Register */
108 REG_FLD_MOD(base, HDMI_CORE_DDC_SEGM, ext / 2, 7, 0);
109
110 /* Load Slave Address Register */
111 REG_FLD_MOD(base, HDMI_CORE_DDC_ADDR, 0xA0 >> 1, 7, 1);
112
113 /* Load Offset Address Register */
114 REG_FLD_MOD(base, HDMI_CORE_DDC_OFFSET, offset, 7, 0);
115
116 /* Load Byte Count */
117 REG_FLD_MOD(base, HDMI_CORE_DDC_COUNT1, 0x80, 7, 0);
118 REG_FLD_MOD(base, HDMI_CORE_DDC_COUNT2, 0x0, 1, 0);
119
120 /* Set DDC_CMD */
121 if (ext)
122 REG_FLD_MOD(base, HDMI_CORE_DDC_CMD, 0x4, 3, 0);
123 else
124 REG_FLD_MOD(base, HDMI_CORE_DDC_CMD, 0x2, 3, 0);
125
126 /* HDMI_CORE_DDC_STATUS_BUS_LOW */
127 if (REG_GET(base, HDMI_CORE_DDC_STATUS, 6, 6) == 1) {
128 DSSERR("I2C Bus Low?\n");
129 return -EIO;
130 }
131 /* HDMI_CORE_DDC_STATUS_NO_ACK */
132 if (REG_GET(base, HDMI_CORE_DDC_STATUS, 5, 5) == 1) {
133 DSSERR("I2C No Ack\n");
134 return -EIO;
135 }
136
137 for (i = 0; i < 0x80; ++i) {
138 int t;
139
140 /* IN_PROG */
141 if (REG_GET(base, HDMI_CORE_DDC_STATUS, 4, 4) == 0) {
142 DSSERR("operation stopped when reading edid\n");
143 return -EIO;
144 }
145
146 t = 0;
147 /* FIFO_EMPTY */
148 while (REG_GET(base, HDMI_CORE_DDC_STATUS, 2, 2) == 1) {
149 if (t++ > 10000) {
150 DSSERR("timeout reading edid\n");
151 return -ETIMEDOUT;
152 }
153 udelay(1);
154 }
155
156 pedid[i] = REG_GET(base, HDMI_CORE_DDC_DATA, 7, 0);
157 }
158
159 checksum = 0;
160 for (i = 0; i < 0x80; ++i)
161 checksum += pedid[i];
162
163 if (checksum != 0) {
164 DSSERR("E-EDID checksum failed!!\n");
165 return -EIO;
166 }
167
168 return 0;
169}
170
171int hdmi4_read_edid(struct hdmi_core_data *core, u8 *edid, int len)
172{
173 int r, l;
174
175 if (len < 128)
176 return -EINVAL;
177
178 r = hdmi_core_ddc_init(core);
179 if (r)
180 return r;
181
182 r = hdmi_core_ddc_edid(core, edid, 0);
183 if (r)
184 return r;
185
186 l = 128;
187
188 if (len >= 128 * 2 && edid[0x7e] > 0) {
189 r = hdmi_core_ddc_edid(core, edid + 0x80, 1);
190 if (r)
191 return r;
192 l += 128;
193 }
194
195 return l;
196}
197
198static void hdmi_core_init(struct hdmi_core_video_config *video_cfg)
199{
200 DSSDBG("Enter hdmi_core_init\n");
201
202 /* video core */
203 video_cfg->ip_bus_width = HDMI_INPUT_8BIT;
204 video_cfg->op_dither_truc = HDMI_OUTPUTTRUNCATION_8BIT;
205 video_cfg->deep_color_pkt = HDMI_DEEPCOLORPACKECTDISABLE;
206 video_cfg->pkt_mode = HDMI_PACKETMODERESERVEDVALUE;
207 video_cfg->hdmi_dvi = HDMI_DVI;
208 video_cfg->tclk_sel_clkmult = HDMI_FPLL10IDCK;
209}
210
211void hdmi4_core_powerdown_disable(struct hdmi_core_data *core)
212{
213 DSSDBG("Enter hdmi4_core_powerdown_disable\n");
214 REG_FLD_MOD(core->base, HDMI_CORE_SYS_SYS_CTRL1, 0x1, 0, 0);
215}
216
217static void hdmi_core_swreset_release(struct hdmi_core_data *core)
218{
219 DSSDBG("Enter hdmi_core_swreset_release\n");
220 REG_FLD_MOD(core->base, HDMI_CORE_SYS_SRST, 0x0, 0, 0);
221}
222
223static void hdmi_core_swreset_assert(struct hdmi_core_data *core)
224{
225 DSSDBG("Enter hdmi_core_swreset_assert\n");
226 REG_FLD_MOD(core->base, HDMI_CORE_SYS_SRST, 0x1, 0, 0);
227}
228
229/* HDMI_CORE_VIDEO_CONFIG */
230static void hdmi_core_video_config(struct hdmi_core_data *core,
231 struct hdmi_core_video_config *cfg)
232{
233 u32 r = 0;
234 void __iomem *core_sys_base = core->base;
235 void __iomem *core_av_base = hdmi_av_base(core);
236
237 /* sys_ctrl1 default configuration not tunable */
238 r = hdmi_read_reg(core_sys_base, HDMI_CORE_SYS_SYS_CTRL1);
239 r = FLD_MOD(r, HDMI_CORE_SYS_SYS_CTRL1_VEN_FOLLOWVSYNC, 5, 5);
240 r = FLD_MOD(r, HDMI_CORE_SYS_SYS_CTRL1_HEN_FOLLOWHSYNC, 4, 4);
241 r = FLD_MOD(r, HDMI_CORE_SYS_SYS_CTRL1_BSEL_24BITBUS, 2, 2);
242 r = FLD_MOD(r, HDMI_CORE_SYS_SYS_CTRL1_EDGE_RISINGEDGE, 1, 1);
243 hdmi_write_reg(core_sys_base, HDMI_CORE_SYS_SYS_CTRL1, r);
244
245 REG_FLD_MOD(core_sys_base,
246 HDMI_CORE_SYS_VID_ACEN, cfg->ip_bus_width, 7, 6);
247
248 /* Vid_Mode */
249 r = hdmi_read_reg(core_sys_base, HDMI_CORE_SYS_VID_MODE);
250
251 /* dither truncation configuration */
252 if (cfg->op_dither_truc > HDMI_OUTPUTTRUNCATION_12BIT) {
253 r = FLD_MOD(r, cfg->op_dither_truc - 3, 7, 6);
254 r = FLD_MOD(r, 1, 5, 5);
255 } else {
256 r = FLD_MOD(r, cfg->op_dither_truc, 7, 6);
257 r = FLD_MOD(r, 0, 5, 5);
258 }
259 hdmi_write_reg(core_sys_base, HDMI_CORE_SYS_VID_MODE, r);
260
261 /* HDMI_Ctrl */
262 r = hdmi_read_reg(core_av_base, HDMI_CORE_AV_HDMI_CTRL);
263 r = FLD_MOD(r, cfg->deep_color_pkt, 6, 6);
264 r = FLD_MOD(r, cfg->pkt_mode, 5, 3);
265 r = FLD_MOD(r, cfg->hdmi_dvi, 0, 0);
266 hdmi_write_reg(core_av_base, HDMI_CORE_AV_HDMI_CTRL, r);
267
268 /* TMDS_CTRL */
269 REG_FLD_MOD(core_sys_base,
270 HDMI_CORE_SYS_TMDS_CTRL, cfg->tclk_sel_clkmult, 6, 5);
271}
272
273static void hdmi_core_write_avi_infoframe(struct hdmi_core_data *core,
274 struct hdmi_avi_infoframe *frame)
275{
276 void __iomem *av_base = hdmi_av_base(core);
277 u8 data[HDMI_INFOFRAME_SIZE(AVI)];
278 int i;
279
280 hdmi_avi_infoframe_pack(frame, data, sizeof(data));
281
282 print_hex_dump_debug("AVI: ", DUMP_PREFIX_NONE, 16, 1, data,
283 HDMI_INFOFRAME_SIZE(AVI), false);
284
285 for (i = 0; i < sizeof(data); ++i) {
286 hdmi_write_reg(av_base, HDMI_CORE_AV_AVI_BASE + i * 4,
287 data[i]);
288 }
289}
290
291static void hdmi_core_av_packet_config(struct hdmi_core_data *core,
292 struct hdmi_core_packet_enable_repeat repeat_cfg)
293{
294 /* enable/repeat the infoframe */
295 hdmi_write_reg(hdmi_av_base(core), HDMI_CORE_AV_PB_CTRL1,
296 (repeat_cfg.audio_pkt << 5) |
297 (repeat_cfg.audio_pkt_repeat << 4) |
298 (repeat_cfg.avi_infoframe << 1) |
299 (repeat_cfg.avi_infoframe_repeat));
300
301 /* enable/repeat the packet */
302 hdmi_write_reg(hdmi_av_base(core), HDMI_CORE_AV_PB_CTRL2,
303 (repeat_cfg.gen_cntrl_pkt << 3) |
304 (repeat_cfg.gen_cntrl_pkt_repeat << 2) |
305 (repeat_cfg.generic_pkt << 1) |
306 (repeat_cfg.generic_pkt_repeat));
307}
308
309void hdmi4_configure(struct hdmi_core_data *core,
310 struct hdmi_wp_data *wp, struct hdmi_config *cfg)
311{
312 /* HDMI */
313 struct videomode vm;
314 struct hdmi_video_format video_format;
315 /* HDMI core */
316 struct hdmi_core_video_config v_core_cfg;
317 struct hdmi_core_packet_enable_repeat repeat_cfg = { 0 };
318
319 hdmi_core_init(&v_core_cfg);
320
321 hdmi_wp_init_vid_fmt_timings(&video_format, &vm, cfg);
322
323 hdmi_wp_video_config_timing(wp, &vm);
324
325 /* video config */
326 video_format.packing_mode = HDMI_PACK_24b_RGB_YUV444_YUV422;
327
328 hdmi_wp_video_config_format(wp, &video_format);
329
330 hdmi_wp_video_config_interface(wp, &vm);
331
332 /*
333 * configure core video part
334 * set software reset in the core
335 */
336 hdmi_core_swreset_assert(core);
337
338 v_core_cfg.pkt_mode = HDMI_PACKETMODE24BITPERPIXEL;
339 v_core_cfg.hdmi_dvi = cfg->hdmi_dvi_mode;
340
341 hdmi_core_video_config(core, &v_core_cfg);
342
343 /* release software reset in the core */
344 hdmi_core_swreset_release(core);
345
346 if (cfg->hdmi_dvi_mode == HDMI_HDMI) {
347 hdmi_core_write_avi_infoframe(core, &cfg->infoframe);
348
349 /* enable/repeat the infoframe */
350 repeat_cfg.avi_infoframe = HDMI_PACKETENABLE;
351 repeat_cfg.avi_infoframe_repeat = HDMI_PACKETREPEATON;
352 /* wakeup */
353 repeat_cfg.audio_pkt = HDMI_PACKETENABLE;
354 repeat_cfg.audio_pkt_repeat = HDMI_PACKETREPEATON;
355 }
356
357 hdmi_core_av_packet_config(core, repeat_cfg);
358}
359
360void hdmi4_core_dump(struct hdmi_core_data *core, struct seq_file *s)
361{
362 int i;
363
364#define CORE_REG(i, name) name(i)
365#define DUMPCORE(r) seq_printf(s, "%-35s %08x\n", #r,\
366 hdmi_read_reg(core->base, r))
367#define DUMPCOREAV(r) seq_printf(s, "%-35s %08x\n", #r,\
368 hdmi_read_reg(hdmi_av_base(core), r))
369#define DUMPCOREAV2(i, r) seq_printf(s, "%s[%d]%*s %08x\n", #r, i, \
370 (i < 10) ? 32 - (int)strlen(#r) : 31 - (int)strlen(#r), " ", \
371 hdmi_read_reg(hdmi_av_base(core), CORE_REG(i, r)))
372
373 DUMPCORE(HDMI_CORE_SYS_VND_IDL);
374 DUMPCORE(HDMI_CORE_SYS_DEV_IDL);
375 DUMPCORE(HDMI_CORE_SYS_DEV_IDH);
376 DUMPCORE(HDMI_CORE_SYS_DEV_REV);
377 DUMPCORE(HDMI_CORE_SYS_SRST);
378 DUMPCORE(HDMI_CORE_SYS_SYS_CTRL1);
379 DUMPCORE(HDMI_CORE_SYS_SYS_STAT);
380 DUMPCORE(HDMI_CORE_SYS_SYS_CTRL3);
381 DUMPCORE(HDMI_CORE_SYS_DE_DLY);
382 DUMPCORE(HDMI_CORE_SYS_DE_CTRL);
383 DUMPCORE(HDMI_CORE_SYS_DE_TOP);
384 DUMPCORE(HDMI_CORE_SYS_DE_CNTL);
385 DUMPCORE(HDMI_CORE_SYS_DE_CNTH);
386 DUMPCORE(HDMI_CORE_SYS_DE_LINL);
387 DUMPCORE(HDMI_CORE_SYS_DE_LINH_1);
388 DUMPCORE(HDMI_CORE_SYS_HRES_L);
389 DUMPCORE(HDMI_CORE_SYS_HRES_H);
390 DUMPCORE(HDMI_CORE_SYS_VRES_L);
391 DUMPCORE(HDMI_CORE_SYS_VRES_H);
392 DUMPCORE(HDMI_CORE_SYS_IADJUST);
393 DUMPCORE(HDMI_CORE_SYS_POLDETECT);
394 DUMPCORE(HDMI_CORE_SYS_HWIDTH1);
395 DUMPCORE(HDMI_CORE_SYS_HWIDTH2);
396 DUMPCORE(HDMI_CORE_SYS_VWIDTH);
397 DUMPCORE(HDMI_CORE_SYS_VID_CTRL);
398 DUMPCORE(HDMI_CORE_SYS_VID_ACEN);
399 DUMPCORE(HDMI_CORE_SYS_VID_MODE);
400 DUMPCORE(HDMI_CORE_SYS_VID_BLANK1);
401 DUMPCORE(HDMI_CORE_SYS_VID_BLANK3);
402 DUMPCORE(HDMI_CORE_SYS_VID_BLANK1);
403 DUMPCORE(HDMI_CORE_SYS_DC_HEADER);
404 DUMPCORE(HDMI_CORE_SYS_VID_DITHER);
405 DUMPCORE(HDMI_CORE_SYS_RGB2XVYCC_CT);
406 DUMPCORE(HDMI_CORE_SYS_R2Y_COEFF_LOW);
407 DUMPCORE(HDMI_CORE_SYS_R2Y_COEFF_UP);
408 DUMPCORE(HDMI_CORE_SYS_G2Y_COEFF_LOW);
409 DUMPCORE(HDMI_CORE_SYS_G2Y_COEFF_UP);
410 DUMPCORE(HDMI_CORE_SYS_B2Y_COEFF_LOW);
411 DUMPCORE(HDMI_CORE_SYS_B2Y_COEFF_UP);
412 DUMPCORE(HDMI_CORE_SYS_R2CB_COEFF_LOW);
413 DUMPCORE(HDMI_CORE_SYS_R2CB_COEFF_UP);
414 DUMPCORE(HDMI_CORE_SYS_G2CB_COEFF_LOW);
415 DUMPCORE(HDMI_CORE_SYS_G2CB_COEFF_UP);
416 DUMPCORE(HDMI_CORE_SYS_B2CB_COEFF_LOW);
417 DUMPCORE(HDMI_CORE_SYS_B2CB_COEFF_UP);
418 DUMPCORE(HDMI_CORE_SYS_R2CR_COEFF_LOW);
419 DUMPCORE(HDMI_CORE_SYS_R2CR_COEFF_UP);
420 DUMPCORE(HDMI_CORE_SYS_G2CR_COEFF_LOW);
421 DUMPCORE(HDMI_CORE_SYS_G2CR_COEFF_UP);
422 DUMPCORE(HDMI_CORE_SYS_B2CR_COEFF_LOW);
423 DUMPCORE(HDMI_CORE_SYS_B2CR_COEFF_UP);
424 DUMPCORE(HDMI_CORE_SYS_RGB_OFFSET_LOW);
425 DUMPCORE(HDMI_CORE_SYS_RGB_OFFSET_UP);
426 DUMPCORE(HDMI_CORE_SYS_Y_OFFSET_LOW);
427 DUMPCORE(HDMI_CORE_SYS_Y_OFFSET_UP);
428 DUMPCORE(HDMI_CORE_SYS_CBCR_OFFSET_LOW);
429 DUMPCORE(HDMI_CORE_SYS_CBCR_OFFSET_UP);
430 DUMPCORE(HDMI_CORE_SYS_INTR_STATE);
431 DUMPCORE(HDMI_CORE_SYS_INTR1);
432 DUMPCORE(HDMI_CORE_SYS_INTR2);
433 DUMPCORE(HDMI_CORE_SYS_INTR3);
434 DUMPCORE(HDMI_CORE_SYS_INTR4);
435 DUMPCORE(HDMI_CORE_SYS_INTR_UNMASK1);
436 DUMPCORE(HDMI_CORE_SYS_INTR_UNMASK2);
437 DUMPCORE(HDMI_CORE_SYS_INTR_UNMASK3);
438 DUMPCORE(HDMI_CORE_SYS_INTR_UNMASK4);
439 DUMPCORE(HDMI_CORE_SYS_INTR_CTRL);
440 DUMPCORE(HDMI_CORE_SYS_TMDS_CTRL);
441
442 DUMPCORE(HDMI_CORE_DDC_ADDR);
443 DUMPCORE(HDMI_CORE_DDC_SEGM);
444 DUMPCORE(HDMI_CORE_DDC_OFFSET);
445 DUMPCORE(HDMI_CORE_DDC_COUNT1);
446 DUMPCORE(HDMI_CORE_DDC_COUNT2);
447 DUMPCORE(HDMI_CORE_DDC_STATUS);
448 DUMPCORE(HDMI_CORE_DDC_CMD);
449 DUMPCORE(HDMI_CORE_DDC_DATA);
450
451 DUMPCOREAV(HDMI_CORE_AV_ACR_CTRL);
452 DUMPCOREAV(HDMI_CORE_AV_FREQ_SVAL);
453 DUMPCOREAV(HDMI_CORE_AV_N_SVAL1);
454 DUMPCOREAV(HDMI_CORE_AV_N_SVAL2);
455 DUMPCOREAV(HDMI_CORE_AV_N_SVAL3);
456 DUMPCOREAV(HDMI_CORE_AV_CTS_SVAL1);
457 DUMPCOREAV(HDMI_CORE_AV_CTS_SVAL2);
458 DUMPCOREAV(HDMI_CORE_AV_CTS_SVAL3);
459 DUMPCOREAV(HDMI_CORE_AV_CTS_HVAL1);
460 DUMPCOREAV(HDMI_CORE_AV_CTS_HVAL2);
461 DUMPCOREAV(HDMI_CORE_AV_CTS_HVAL3);
462 DUMPCOREAV(HDMI_CORE_AV_AUD_MODE);
463 DUMPCOREAV(HDMI_CORE_AV_SPDIF_CTRL);
464 DUMPCOREAV(HDMI_CORE_AV_HW_SPDIF_FS);
465 DUMPCOREAV(HDMI_CORE_AV_SWAP_I2S);
466 DUMPCOREAV(HDMI_CORE_AV_SPDIF_ERTH);
467 DUMPCOREAV(HDMI_CORE_AV_I2S_IN_MAP);
468 DUMPCOREAV(HDMI_CORE_AV_I2S_IN_CTRL);
469 DUMPCOREAV(HDMI_CORE_AV_I2S_CHST0);
470 DUMPCOREAV(HDMI_CORE_AV_I2S_CHST1);
471 DUMPCOREAV(HDMI_CORE_AV_I2S_CHST2);
472 DUMPCOREAV(HDMI_CORE_AV_I2S_CHST4);
473 DUMPCOREAV(HDMI_CORE_AV_I2S_CHST5);
474 DUMPCOREAV(HDMI_CORE_AV_ASRC);
475 DUMPCOREAV(HDMI_CORE_AV_I2S_IN_LEN);
476 DUMPCOREAV(HDMI_CORE_AV_HDMI_CTRL);
477 DUMPCOREAV(HDMI_CORE_AV_AUDO_TXSTAT);
478 DUMPCOREAV(HDMI_CORE_AV_AUD_PAR_BUSCLK_1);
479 DUMPCOREAV(HDMI_CORE_AV_AUD_PAR_BUSCLK_2);
480 DUMPCOREAV(HDMI_CORE_AV_AUD_PAR_BUSCLK_3);
481 DUMPCOREAV(HDMI_CORE_AV_TEST_TXCTRL);
482 DUMPCOREAV(HDMI_CORE_AV_DPD);
483 DUMPCOREAV(HDMI_CORE_AV_PB_CTRL1);
484 DUMPCOREAV(HDMI_CORE_AV_PB_CTRL2);
485 DUMPCOREAV(HDMI_CORE_AV_AVI_TYPE);
486 DUMPCOREAV(HDMI_CORE_AV_AVI_VERS);
487 DUMPCOREAV(HDMI_CORE_AV_AVI_LEN);
488 DUMPCOREAV(HDMI_CORE_AV_AVI_CHSUM);
489
490 for (i = 0; i < HDMI_CORE_AV_AVI_DBYTE_NELEMS; i++)
491 DUMPCOREAV2(i, HDMI_CORE_AV_AVI_DBYTE);
492
493 DUMPCOREAV(HDMI_CORE_AV_SPD_TYPE);
494 DUMPCOREAV(HDMI_CORE_AV_SPD_VERS);
495 DUMPCOREAV(HDMI_CORE_AV_SPD_LEN);
496 DUMPCOREAV(HDMI_CORE_AV_SPD_CHSUM);
497
498 for (i = 0; i < HDMI_CORE_AV_SPD_DBYTE_NELEMS; i++)
499 DUMPCOREAV2(i, HDMI_CORE_AV_SPD_DBYTE);
500
501 DUMPCOREAV(HDMI_CORE_AV_AUDIO_TYPE);
502 DUMPCOREAV(HDMI_CORE_AV_AUDIO_VERS);
503 DUMPCOREAV(HDMI_CORE_AV_AUDIO_LEN);
504 DUMPCOREAV(HDMI_CORE_AV_AUDIO_CHSUM);
505
506 for (i = 0; i < HDMI_CORE_AV_AUD_DBYTE_NELEMS; i++)
507 DUMPCOREAV2(i, HDMI_CORE_AV_AUD_DBYTE);
508
509 DUMPCOREAV(HDMI_CORE_AV_MPEG_TYPE);
510 DUMPCOREAV(HDMI_CORE_AV_MPEG_VERS);
511 DUMPCOREAV(HDMI_CORE_AV_MPEG_LEN);
512 DUMPCOREAV(HDMI_CORE_AV_MPEG_CHSUM);
513
514 for (i = 0; i < HDMI_CORE_AV_MPEG_DBYTE_NELEMS; i++)
515 DUMPCOREAV2(i, HDMI_CORE_AV_MPEG_DBYTE);
516
517 for (i = 0; i < HDMI_CORE_AV_GEN_DBYTE_NELEMS; i++)
518 DUMPCOREAV2(i, HDMI_CORE_AV_GEN_DBYTE);
519
520 DUMPCOREAV(HDMI_CORE_AV_CP_BYTE1);
521
522 for (i = 0; i < HDMI_CORE_AV_GEN2_DBYTE_NELEMS; i++)
523 DUMPCOREAV2(i, HDMI_CORE_AV_GEN2_DBYTE);
524
525 DUMPCOREAV(HDMI_CORE_AV_CEC_ADDR_ID);
526}
527
528static void hdmi_core_audio_config(struct hdmi_core_data *core,
529 struct hdmi_core_audio_config *cfg)
530{
531 u32 r;
532 void __iomem *av_base = hdmi_av_base(core);
533
534 /*
535 * Parameters for generation of Audio Clock Recovery packets
536 */
537 REG_FLD_MOD(av_base, HDMI_CORE_AV_N_SVAL1, cfg->n, 7, 0);
538 REG_FLD_MOD(av_base, HDMI_CORE_AV_N_SVAL2, cfg->n >> 8, 7, 0);
539 REG_FLD_MOD(av_base, HDMI_CORE_AV_N_SVAL3, cfg->n >> 16, 7, 0);
540
541 if (cfg->cts_mode == HDMI_AUDIO_CTS_MODE_SW) {
542 REG_FLD_MOD(av_base, HDMI_CORE_AV_CTS_SVAL1, cfg->cts, 7, 0);
543 REG_FLD_MOD(av_base,
544 HDMI_CORE_AV_CTS_SVAL2, cfg->cts >> 8, 7, 0);
545 REG_FLD_MOD(av_base,
546 HDMI_CORE_AV_CTS_SVAL3, cfg->cts >> 16, 7, 0);
547 } else {
548 REG_FLD_MOD(av_base, HDMI_CORE_AV_AUD_PAR_BUSCLK_1,
549 cfg->aud_par_busclk, 7, 0);
550 REG_FLD_MOD(av_base, HDMI_CORE_AV_AUD_PAR_BUSCLK_2,
551 (cfg->aud_par_busclk >> 8), 7, 0);
552 REG_FLD_MOD(av_base, HDMI_CORE_AV_AUD_PAR_BUSCLK_3,
553 (cfg->aud_par_busclk >> 16), 7, 0);
554 }
555
556 /* Set ACR clock divisor */
557 REG_FLD_MOD(av_base,
558 HDMI_CORE_AV_FREQ_SVAL, cfg->mclk_mode, 2, 0);
559
560 r = hdmi_read_reg(av_base, HDMI_CORE_AV_ACR_CTRL);
561 /*
562 * Use TMDS clock for ACR packets. For devices that use
563 * the MCLK, this is the first part of the MCLK initialization.
564 */
565 r = FLD_MOD(r, 0, 2, 2);
566
567 r = FLD_MOD(r, cfg->en_acr_pkt, 1, 1);
568 r = FLD_MOD(r, cfg->cts_mode, 0, 0);
569 hdmi_write_reg(av_base, HDMI_CORE_AV_ACR_CTRL, r);
570
571 /* For devices using MCLK, this completes its initialization. */
572 if (cfg->use_mclk)
573 REG_FLD_MOD(av_base, HDMI_CORE_AV_ACR_CTRL, 1, 2, 2);
574
575 /* Override of SPDIF sample frequency with value in I2S_CHST4 */
576 REG_FLD_MOD(av_base, HDMI_CORE_AV_SPDIF_CTRL,
577 cfg->fs_override, 1, 1);
578
579 /*
580 * Set IEC-60958-3 channel status word. It is passed to the IP
581 * just as it is received. The user of the driver is responsible
582 * for its contents.
583 */
584 hdmi_write_reg(av_base, HDMI_CORE_AV_I2S_CHST0,
585 cfg->iec60958_cfg->status[0]);
586 hdmi_write_reg(av_base, HDMI_CORE_AV_I2S_CHST1,
587 cfg->iec60958_cfg->status[1]);
588 hdmi_write_reg(av_base, HDMI_CORE_AV_I2S_CHST2,
589 cfg->iec60958_cfg->status[2]);
590 /* yes, this is correct: status[3] goes to CHST4 register */
591 hdmi_write_reg(av_base, HDMI_CORE_AV_I2S_CHST4,
592 cfg->iec60958_cfg->status[3]);
593 /* yes, this is correct: status[4] goes to CHST5 register */
594 hdmi_write_reg(av_base, HDMI_CORE_AV_I2S_CHST5,
595 cfg->iec60958_cfg->status[4]);
596
597 /* set I2S parameters */
598 r = hdmi_read_reg(av_base, HDMI_CORE_AV_I2S_IN_CTRL);
599 r = FLD_MOD(r, cfg->i2s_cfg.sck_edge_mode, 6, 6);
600 r = FLD_MOD(r, cfg->i2s_cfg.vbit, 4, 4);
601 r = FLD_MOD(r, cfg->i2s_cfg.justification, 2, 2);
602 r = FLD_MOD(r, cfg->i2s_cfg.direction, 1, 1);
603 r = FLD_MOD(r, cfg->i2s_cfg.shift, 0, 0);
604 hdmi_write_reg(av_base, HDMI_CORE_AV_I2S_IN_CTRL, r);
605
606 REG_FLD_MOD(av_base, HDMI_CORE_AV_I2S_IN_LEN,
607 cfg->i2s_cfg.in_length_bits, 3, 0);
608
609 /* Audio channels and mode parameters */
610 REG_FLD_MOD(av_base, HDMI_CORE_AV_HDMI_CTRL, cfg->layout, 2, 1);
611 r = hdmi_read_reg(av_base, HDMI_CORE_AV_AUD_MODE);
612 r = FLD_MOD(r, cfg->i2s_cfg.active_sds, 7, 4);
613 r = FLD_MOD(r, cfg->en_dsd_audio, 3, 3);
614 r = FLD_MOD(r, cfg->en_parallel_aud_input, 2, 2);
615 r = FLD_MOD(r, cfg->en_spdif, 1, 1);
616 hdmi_write_reg(av_base, HDMI_CORE_AV_AUD_MODE, r);
617
618 /* Audio channel mappings */
619 /* TODO: Make channel mapping dynamic. For now, map channels
620 * in the ALSA order: FL/FR/RL/RR/C/LFE/SL/SR. Remapping is needed as
621 * HDMI speaker order is different. See CEA-861 Section 6.6.2.
622 */
623 hdmi_write_reg(av_base, HDMI_CORE_AV_I2S_IN_MAP, 0x78);
624 REG_FLD_MOD(av_base, HDMI_CORE_AV_SWAP_I2S, 1, 5, 5);
625}
626
627static void hdmi_core_audio_infoframe_cfg(struct hdmi_core_data *core,
628 struct snd_cea_861_aud_if *info_aud)
629{
630 u8 sum = 0, checksum = 0;
631 void __iomem *av_base = hdmi_av_base(core);
632
633 /*
634 * Set audio info frame type, version and length as
635 * described in HDMI 1.4a Section 8.2.2 specification.
636 * Checksum calculation is defined in Section 5.3.5.
637 */
638 hdmi_write_reg(av_base, HDMI_CORE_AV_AUDIO_TYPE, 0x84);
639 hdmi_write_reg(av_base, HDMI_CORE_AV_AUDIO_VERS, 0x01);
640 hdmi_write_reg(av_base, HDMI_CORE_AV_AUDIO_LEN, 0x0a);
641 sum += 0x84 + 0x001 + 0x00a;
642
643 hdmi_write_reg(av_base, HDMI_CORE_AV_AUD_DBYTE(0),
644 info_aud->db1_ct_cc);
645 sum += info_aud->db1_ct_cc;
646
647 hdmi_write_reg(av_base, HDMI_CORE_AV_AUD_DBYTE(1),
648 info_aud->db2_sf_ss);
649 sum += info_aud->db2_sf_ss;
650
651 hdmi_write_reg(av_base, HDMI_CORE_AV_AUD_DBYTE(2), info_aud->db3);
652 sum += info_aud->db3;
653
654 /*
655 * The OMAP HDMI IP requires to use the 8-channel channel code when
656 * transmitting more than two channels.
657 */
658 if (info_aud->db4_ca != 0x00)
659 info_aud->db4_ca = 0x13;
660
661 hdmi_write_reg(av_base, HDMI_CORE_AV_AUD_DBYTE(3), info_aud->db4_ca);
662 sum += info_aud->db4_ca;
663
664 hdmi_write_reg(av_base, HDMI_CORE_AV_AUD_DBYTE(4),
665 info_aud->db5_dminh_lsv);
666 sum += info_aud->db5_dminh_lsv;
667
668 hdmi_write_reg(av_base, HDMI_CORE_AV_AUD_DBYTE(5), 0x00);
669 hdmi_write_reg(av_base, HDMI_CORE_AV_AUD_DBYTE(6), 0x00);
670 hdmi_write_reg(av_base, HDMI_CORE_AV_AUD_DBYTE(7), 0x00);
671 hdmi_write_reg(av_base, HDMI_CORE_AV_AUD_DBYTE(8), 0x00);
672 hdmi_write_reg(av_base, HDMI_CORE_AV_AUD_DBYTE(9), 0x00);
673
674 checksum = 0x100 - sum;
675 hdmi_write_reg(av_base,
676 HDMI_CORE_AV_AUDIO_CHSUM, checksum);
677
678 /*
679 * TODO: Add MPEG and SPD enable and repeat cfg when EDID parsing
680 * is available.
681 */
682}
683
684int hdmi4_audio_config(struct hdmi_core_data *core, struct hdmi_wp_data *wp,
685 struct omap_dss_audio *audio, u32 pclk)
686{
687 struct hdmi_audio_format audio_format;
688 struct hdmi_audio_dma audio_dma;
689 struct hdmi_core_audio_config acore;
690 int err, n, cts, channel_count;
691 unsigned int fs_nr;
692 bool word_length_16b = false;
693
694 if (!audio || !audio->iec || !audio->cea || !core)
695 return -EINVAL;
696
697 acore.iec60958_cfg = audio->iec;
698 /*
699 * In the IEC-60958 status word, check if the audio sample word length
700 * is 16-bit as several optimizations can be performed in such case.
701 */
702 if (!(audio->iec->status[4] & IEC958_AES4_CON_MAX_WORDLEN_24))
703 if (audio->iec->status[4] & IEC958_AES4_CON_WORDLEN_20_16)
704 word_length_16b = true;
705
706 /* I2S configuration. See Phillips' specification */
707 if (word_length_16b)
708 acore.i2s_cfg.justification = HDMI_AUDIO_JUSTIFY_LEFT;
709 else
710 acore.i2s_cfg.justification = HDMI_AUDIO_JUSTIFY_RIGHT;
711 /*
712 * The I2S input word length is twice the lenght given in the IEC-60958
713 * status word. If the word size is greater than
714 * 20 bits, increment by one.
715 */
716 acore.i2s_cfg.in_length_bits = audio->iec->status[4]
717 & IEC958_AES4_CON_WORDLEN;
718 if (audio->iec->status[4] & IEC958_AES4_CON_MAX_WORDLEN_24)
719 acore.i2s_cfg.in_length_bits++;
720 acore.i2s_cfg.sck_edge_mode = HDMI_AUDIO_I2S_SCK_EDGE_RISING;
721 acore.i2s_cfg.vbit = HDMI_AUDIO_I2S_VBIT_FOR_PCM;
722 acore.i2s_cfg.direction = HDMI_AUDIO_I2S_MSB_SHIFTED_FIRST;
723 acore.i2s_cfg.shift = HDMI_AUDIO_I2S_FIRST_BIT_SHIFT;
724
725 /* convert sample frequency to a number */
726 switch (audio->iec->status[3] & IEC958_AES3_CON_FS) {
727 case IEC958_AES3_CON_FS_32000:
728 fs_nr = 32000;
729 break;
730 case IEC958_AES3_CON_FS_44100:
731 fs_nr = 44100;
732 break;
733 case IEC958_AES3_CON_FS_48000:
734 fs_nr = 48000;
735 break;
736 case IEC958_AES3_CON_FS_88200:
737 fs_nr = 88200;
738 break;
739 case IEC958_AES3_CON_FS_96000:
740 fs_nr = 96000;
741 break;
742 case IEC958_AES3_CON_FS_176400:
743 fs_nr = 176400;
744 break;
745 case IEC958_AES3_CON_FS_192000:
746 fs_nr = 192000;
747 break;
748 default:
749 return -EINVAL;
750 }
751
752 err = hdmi_compute_acr(pclk, fs_nr, &n, &cts);
753
754 /* Audio clock regeneration settings */
755 acore.n = n;
756 acore.cts = cts;
757 if (core->cts_swmode) {
758 acore.aud_par_busclk = 0;
759 acore.cts_mode = HDMI_AUDIO_CTS_MODE_SW;
760 acore.use_mclk = core->audio_use_mclk;
761 } else {
762 acore.aud_par_busclk = (((128 * 31) - 1) << 8);
763 acore.cts_mode = HDMI_AUDIO_CTS_MODE_HW;
764 acore.use_mclk = true;
765 }
766
767 if (acore.use_mclk)
768 acore.mclk_mode = HDMI_AUDIO_MCLK_128FS;
769
770 /* Audio channels settings */
771 channel_count = (audio->cea->db1_ct_cc &
772 CEA861_AUDIO_INFOFRAME_DB1CC) + 1;
773
774 switch (channel_count) {
775 case 2:
776 audio_format.active_chnnls_msk = 0x03;
777 break;
778 case 3:
779 audio_format.active_chnnls_msk = 0x07;
780 break;
781 case 4:
782 audio_format.active_chnnls_msk = 0x0f;
783 break;
784 case 5:
785 audio_format.active_chnnls_msk = 0x1f;
786 break;
787 case 6:
788 audio_format.active_chnnls_msk = 0x3f;
789 break;
790 case 7:
791 audio_format.active_chnnls_msk = 0x7f;
792 break;
793 case 8:
794 audio_format.active_chnnls_msk = 0xff;
795 break;
796 default:
797 return -EINVAL;
798 }
799
800 /*
801 * the HDMI IP needs to enable four stereo channels when transmitting
802 * more than 2 audio channels. Similarly, the channel count in the
803 * Audio InfoFrame has to match the sample_present bits (some channels
804 * are padded with zeroes)
805 */
806 if (channel_count == 2) {
807 audio_format.stereo_channels = HDMI_AUDIO_STEREO_ONECHANNEL;
808 acore.i2s_cfg.active_sds = HDMI_AUDIO_I2S_SD0_EN;
809 acore.layout = HDMI_AUDIO_LAYOUT_2CH;
810 } else {
811 audio_format.stereo_channels = HDMI_AUDIO_STEREO_FOURCHANNELS;
812 acore.i2s_cfg.active_sds = HDMI_AUDIO_I2S_SD0_EN |
813 HDMI_AUDIO_I2S_SD1_EN | HDMI_AUDIO_I2S_SD2_EN |
814 HDMI_AUDIO_I2S_SD3_EN;
815 acore.layout = HDMI_AUDIO_LAYOUT_8CH;
816 audio->cea->db1_ct_cc = 7;
817 }
818
819 acore.en_spdif = false;
820 /* use sample frequency from channel status word */
821 acore.fs_override = true;
822 /* enable ACR packets */
823 acore.en_acr_pkt = true;
824 /* disable direct streaming digital audio */
825 acore.en_dsd_audio = false;
826 /* use parallel audio interface */
827 acore.en_parallel_aud_input = true;
828
829 /* DMA settings */
830 if (word_length_16b)
831 audio_dma.transfer_size = 0x10;
832 else
833 audio_dma.transfer_size = 0x20;
834 audio_dma.block_size = 0xC0;
835 audio_dma.mode = HDMI_AUDIO_TRANSF_DMA;
836 audio_dma.fifo_threshold = 0x20; /* in number of samples */
837
838 /* audio FIFO format settings */
839 if (word_length_16b) {
840 audio_format.samples_per_word = HDMI_AUDIO_ONEWORD_TWOSAMPLES;
841 audio_format.sample_size = HDMI_AUDIO_SAMPLE_16BITS;
842 audio_format.justification = HDMI_AUDIO_JUSTIFY_LEFT;
843 } else {
844 audio_format.samples_per_word = HDMI_AUDIO_ONEWORD_ONESAMPLE;
845 audio_format.sample_size = HDMI_AUDIO_SAMPLE_24BITS;
846 audio_format.justification = HDMI_AUDIO_JUSTIFY_RIGHT;
847 }
848 audio_format.type = HDMI_AUDIO_TYPE_LPCM;
849 audio_format.sample_order = HDMI_AUDIO_SAMPLE_LEFT_FIRST;
850 /* disable start/stop signals of IEC 60958 blocks */
851 audio_format.en_sig_blk_strt_end = HDMI_AUDIO_BLOCK_SIG_STARTEND_ON;
852
853 /* configure DMA and audio FIFO format*/
854 hdmi_wp_audio_config_dma(wp, &audio_dma);
855 hdmi_wp_audio_config_format(wp, &audio_format);
856
857 /* configure the core*/
858 hdmi_core_audio_config(core, &acore);
859
860 /* configure CEA 861 audio infoframe*/
861 hdmi_core_audio_infoframe_cfg(core, audio->cea);
862
863 return 0;
864}
865
866int hdmi4_audio_start(struct hdmi_core_data *core, struct hdmi_wp_data *wp)
867{
868 REG_FLD_MOD(hdmi_av_base(core),
869 HDMI_CORE_AV_AUD_MODE, true, 0, 0);
870
871 hdmi_wp_audio_core_req_enable(wp, true);
872
873 return 0;
874}
875
876void hdmi4_audio_stop(struct hdmi_core_data *core, struct hdmi_wp_data *wp)
877{
878 REG_FLD_MOD(hdmi_av_base(core),
879 HDMI_CORE_AV_AUD_MODE, false, 0, 0);
880
881 hdmi_wp_audio_core_req_enable(wp, false);
882}
883
884struct hdmi4_features {
885 bool cts_swmode;
886 bool audio_use_mclk;
887};
888
889static const struct hdmi4_features hdmi4430_es1_features = {
890 .cts_swmode = false,
891 .audio_use_mclk = false,
892};
893
894static const struct hdmi4_features hdmi4430_es2_features = {
895 .cts_swmode = true,
896 .audio_use_mclk = false,
897};
898
899static const struct hdmi4_features hdmi4_features = {
900 .cts_swmode = true,
901 .audio_use_mclk = true,
902};
903
904static const struct soc_device_attribute hdmi4_soc_devices[] = {
905 {
906 .machine = "OMAP4430",
907 .revision = "ES1.?",
908 .data = &hdmi4430_es1_features,
909 },
910 {
911 .machine = "OMAP4430",
912 .revision = "ES2.?",
913 .data = &hdmi4430_es2_features,
914 },
915 {
916 .family = "OMAP4",
917 .data = &hdmi4_features,
918 },
919 { /* sentinel */ }
920};
921
922int hdmi4_core_init(struct platform_device *pdev, struct hdmi_core_data *core)
923{
924 const struct hdmi4_features *features;
925 struct resource *res;
926
927 features = soc_device_match(hdmi4_soc_devices)->data;
928 core->cts_swmode = features->cts_swmode;
929 core->audio_use_mclk = features->audio_use_mclk;
930
931 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "core");
932 core->base = devm_ioremap_resource(&pdev->dev, res);
933 if (IS_ERR(core->base))
934 return PTR_ERR(core->base);
935
936 return 0;
937}