tjh.dev
Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
1/*
2 * Copyright 2012-16 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: AMD
23 *
24 */
25
26
27#ifndef _DCE_ABM_H_
28#define _DCE_ABM_H_
29
30#include "abm.h"
31
32#define ABM_COMMON_REG_LIST_DCE_BASE() \
33 SR(BL_PWM_PERIOD_CNTL), \
34 SR(BL_PWM_CNTL), \
35 SR(BL_PWM_CNTL2), \
36 SR(BL_PWM_GRP1_REG_LOCK), \
37 SR(LVTMA_PWRSEQ_REF_DIV), \
38 SR(MASTER_COMM_CNTL_REG), \
39 SR(MASTER_COMM_CMD_REG), \
40 SR(MASTER_COMM_DATA_REG1), \
41 SR(DMCU_STATUS)
42
43#define ABM_DCE110_COMMON_REG_LIST() \
44 ABM_COMMON_REG_LIST_DCE_BASE(), \
45 SR(DC_ABM1_HG_SAMPLE_RATE), \
46 SR(DC_ABM1_LS_SAMPLE_RATE), \
47 SR(BL1_PWM_BL_UPDATE_SAMPLE_RATE), \
48 SR(DC_ABM1_HG_MISC_CTRL), \
49 SR(DC_ABM1_IPCSC_COEFF_SEL), \
50 SR(BL1_PWM_CURRENT_ABM_LEVEL), \
51 SR(BL1_PWM_TARGET_ABM_LEVEL), \
52 SR(BL1_PWM_USER_LEVEL), \
53 SR(DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES), \
54 SR(DC_ABM1_HGLS_REG_READ_PROGRESS), \
55 SR(BIOS_SCRATCH_2)
56
57#define ABM_DCN10_REG_LIST(id)\
58 ABM_COMMON_REG_LIST_DCE_BASE(), \
59 SRI(DC_ABM1_HG_SAMPLE_RATE, ABM, id), \
60 SRI(DC_ABM1_LS_SAMPLE_RATE, ABM, id), \
61 SRI(BL1_PWM_BL_UPDATE_SAMPLE_RATE, ABM, id), \
62 SRI(DC_ABM1_HG_MISC_CTRL, ABM, id), \
63 SRI(DC_ABM1_IPCSC_COEFF_SEL, ABM, id), \
64 SRI(BL1_PWM_CURRENT_ABM_LEVEL, ABM, id), \
65 SRI(BL1_PWM_TARGET_ABM_LEVEL, ABM, id), \
66 SRI(BL1_PWM_USER_LEVEL, ABM, id), \
67 SRI(DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES, ABM, id), \
68 SRI(DC_ABM1_HGLS_REG_READ_PROGRESS, ABM, id), \
69 NBIO_SR(BIOS_SCRATCH_2)
70
71#define ABM_SF(reg_name, field_name, post_fix)\
72 .field_name = reg_name ## __ ## field_name ## post_fix
73
74#define ABM_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(mask_sh) \
75 ABM_SF(BL_PWM_PERIOD_CNTL, BL_PWM_PERIOD, mask_sh), \
76 ABM_SF(BL_PWM_PERIOD_CNTL, BL_PWM_PERIOD_BITCNT, mask_sh), \
77 ABM_SF(BL_PWM_CNTL, BL_ACTIVE_INT_FRAC_CNT, mask_sh), \
78 ABM_SF(BL_PWM_CNTL, BL_PWM_FRACTIONAL_EN, mask_sh), \
79 ABM_SF(BL_PWM_CNTL, BL_PWM_EN, mask_sh), \
80 ABM_SF(BL_PWM_GRP1_REG_LOCK, BL_PWM_GRP1_IGNORE_MASTER_LOCK_EN, mask_sh), \
81 ABM_SF(BL_PWM_GRP1_REG_LOCK, BL_PWM_GRP1_REG_LOCK, mask_sh), \
82 ABM_SF(BL_PWM_GRP1_REG_LOCK, BL_PWM_GRP1_REG_UPDATE_PENDING, mask_sh), \
83 ABM_SF(LVTMA_PWRSEQ_REF_DIV, BL_PWM_REF_DIV, mask_sh), \
84 ABM_SF(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, mask_sh), \
85 ABM_SF(MASTER_COMM_CMD_REG, MASTER_COMM_CMD_REG_BYTE0, mask_sh), \
86 ABM_SF(MASTER_COMM_CMD_REG, MASTER_COMM_CMD_REG_BYTE1, mask_sh), \
87 ABM_SF(MASTER_COMM_CMD_REG, MASTER_COMM_CMD_REG_BYTE2, mask_sh), \
88 ABM_SF(DMCU_STATUS, UC_IN_RESET, mask_sh)
89
90#define ABM_MASK_SH_LIST_DCE110(mask_sh) \
91 ABM_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(mask_sh), \
92 ABM_SF(DC_ABM1_HG_MISC_CTRL, \
93 ABM1_HG_NUM_OF_BINS_SEL, mask_sh), \
94 ABM_SF(DC_ABM1_HG_MISC_CTRL, \
95 ABM1_HG_VMAX_SEL, mask_sh), \
96 ABM_SF(DC_ABM1_HG_MISC_CTRL, \
97 ABM1_HG_BIN_BITWIDTH_SIZE_SEL, mask_sh), \
98 ABM_SF(DC_ABM1_IPCSC_COEFF_SEL, \
99 ABM1_IPCSC_COEFF_SEL_R, mask_sh), \
100 ABM_SF(DC_ABM1_IPCSC_COEFF_SEL, \
101 ABM1_IPCSC_COEFF_SEL_G, mask_sh), \
102 ABM_SF(DC_ABM1_IPCSC_COEFF_SEL, \
103 ABM1_IPCSC_COEFF_SEL_B, mask_sh), \
104 ABM_SF(BL1_PWM_CURRENT_ABM_LEVEL, \
105 BL1_PWM_CURRENT_ABM_LEVEL, mask_sh), \
106 ABM_SF(BL1_PWM_TARGET_ABM_LEVEL, \
107 BL1_PWM_TARGET_ABM_LEVEL, mask_sh), \
108 ABM_SF(BL1_PWM_USER_LEVEL, \
109 BL1_PWM_USER_LEVEL, mask_sh), \
110 ABM_SF(DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES, \
111 ABM1_LS_MIN_PIXEL_VALUE_THRES, mask_sh), \
112 ABM_SF(DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES, \
113 ABM1_LS_MAX_PIXEL_VALUE_THRES, mask_sh), \
114 ABM_SF(DC_ABM1_HGLS_REG_READ_PROGRESS, \
115 ABM1_HG_REG_READ_MISSED_FRAME_CLEAR, mask_sh), \
116 ABM_SF(DC_ABM1_HGLS_REG_READ_PROGRESS, \
117 ABM1_LS_REG_READ_MISSED_FRAME_CLEAR, mask_sh), \
118 ABM_SF(DC_ABM1_HGLS_REG_READ_PROGRESS, \
119 ABM1_BL_REG_READ_MISSED_FRAME_CLEAR, mask_sh)
120
121#define ABM_MASK_SH_LIST_DCN10(mask_sh) \
122 ABM_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(mask_sh), \
123 ABM_SF(ABM0_DC_ABM1_HG_MISC_CTRL, \
124 ABM1_HG_NUM_OF_BINS_SEL, mask_sh), \
125 ABM_SF(ABM0_DC_ABM1_HG_MISC_CTRL, \
126 ABM1_HG_VMAX_SEL, mask_sh), \
127 ABM_SF(ABM0_DC_ABM1_HG_MISC_CTRL, \
128 ABM1_HG_BIN_BITWIDTH_SIZE_SEL, mask_sh), \
129 ABM_SF(ABM0_DC_ABM1_IPCSC_COEFF_SEL, \
130 ABM1_IPCSC_COEFF_SEL_R, mask_sh), \
131 ABM_SF(ABM0_DC_ABM1_IPCSC_COEFF_SEL, \
132 ABM1_IPCSC_COEFF_SEL_G, mask_sh), \
133 ABM_SF(ABM0_DC_ABM1_IPCSC_COEFF_SEL, \
134 ABM1_IPCSC_COEFF_SEL_B, mask_sh), \
135 ABM_SF(ABM0_BL1_PWM_CURRENT_ABM_LEVEL, \
136 BL1_PWM_CURRENT_ABM_LEVEL, mask_sh), \
137 ABM_SF(ABM0_BL1_PWM_TARGET_ABM_LEVEL, \
138 BL1_PWM_TARGET_ABM_LEVEL, mask_sh), \
139 ABM_SF(ABM0_BL1_PWM_USER_LEVEL, \
140 BL1_PWM_USER_LEVEL, mask_sh), \
141 ABM_SF(ABM0_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES, \
142 ABM1_LS_MIN_PIXEL_VALUE_THRES, mask_sh), \
143 ABM_SF(ABM0_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES, \
144 ABM1_LS_MAX_PIXEL_VALUE_THRES, mask_sh), \
145 ABM_SF(ABM0_DC_ABM1_HGLS_REG_READ_PROGRESS, \
146 ABM1_HG_REG_READ_MISSED_FRAME_CLEAR, mask_sh), \
147 ABM_SF(ABM0_DC_ABM1_HGLS_REG_READ_PROGRESS, \
148 ABM1_LS_REG_READ_MISSED_FRAME_CLEAR, mask_sh), \
149 ABM_SF(ABM0_DC_ABM1_HGLS_REG_READ_PROGRESS, \
150 ABM1_BL_REG_READ_MISSED_FRAME_CLEAR, mask_sh)
151
152#define ABM_REG_FIELD_LIST(type) \
153 type ABM1_HG_NUM_OF_BINS_SEL; \
154 type ABM1_HG_VMAX_SEL; \
155 type ABM1_HG_BIN_BITWIDTH_SIZE_SEL; \
156 type ABM1_IPCSC_COEFF_SEL_R; \
157 type ABM1_IPCSC_COEFF_SEL_G; \
158 type ABM1_IPCSC_COEFF_SEL_B; \
159 type BL1_PWM_CURRENT_ABM_LEVEL; \
160 type BL1_PWM_TARGET_ABM_LEVEL; \
161 type BL1_PWM_USER_LEVEL; \
162 type ABM1_LS_MIN_PIXEL_VALUE_THRES; \
163 type ABM1_LS_MAX_PIXEL_VALUE_THRES; \
164 type ABM1_HG_REG_READ_MISSED_FRAME_CLEAR; \
165 type ABM1_LS_REG_READ_MISSED_FRAME_CLEAR; \
166 type ABM1_BL_REG_READ_MISSED_FRAME_CLEAR; \
167 type BL_PWM_PERIOD; \
168 type BL_PWM_PERIOD_BITCNT; \
169 type BL_ACTIVE_INT_FRAC_CNT; \
170 type BL_PWM_FRACTIONAL_EN; \
171 type MASTER_COMM_INTERRUPT; \
172 type MASTER_COMM_CMD_REG_BYTE0; \
173 type MASTER_COMM_CMD_REG_BYTE1; \
174 type MASTER_COMM_CMD_REG_BYTE2; \
175 type BL_PWM_REF_DIV; \
176 type BL_PWM_EN; \
177 type UC_IN_RESET; \
178 type BL_PWM_GRP1_IGNORE_MASTER_LOCK_EN; \
179 type BL_PWM_GRP1_REG_LOCK; \
180 type BL_PWM_GRP1_REG_UPDATE_PENDING
181
182struct dce_abm_shift {
183 ABM_REG_FIELD_LIST(uint8_t);
184};
185
186struct dce_abm_mask {
187 ABM_REG_FIELD_LIST(uint32_t);
188};
189
190struct dce_abm_registers {
191 uint32_t BL_PWM_PERIOD_CNTL;
192 uint32_t BL_PWM_CNTL;
193 uint32_t BL_PWM_CNTL2;
194 uint32_t LVTMA_PWRSEQ_REF_DIV;
195 uint32_t DC_ABM1_HG_SAMPLE_RATE;
196 uint32_t DC_ABM1_LS_SAMPLE_RATE;
197 uint32_t BL1_PWM_BL_UPDATE_SAMPLE_RATE;
198 uint32_t DC_ABM1_HG_MISC_CTRL;
199 uint32_t DC_ABM1_IPCSC_COEFF_SEL;
200 uint32_t BL1_PWM_CURRENT_ABM_LEVEL;
201 uint32_t BL1_PWM_TARGET_ABM_LEVEL;
202 uint32_t BL1_PWM_USER_LEVEL;
203 uint32_t DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES;
204 uint32_t DC_ABM1_HGLS_REG_READ_PROGRESS;
205 uint32_t MASTER_COMM_CNTL_REG;
206 uint32_t MASTER_COMM_CMD_REG;
207 uint32_t MASTER_COMM_DATA_REG1;
208 uint32_t BIOS_SCRATCH_2;
209 uint32_t DMCU_STATUS;
210 uint32_t BL_PWM_GRP1_REG_LOCK;
211};
212
213struct dce_abm {
214 struct abm base;
215 const struct dce_abm_registers *regs;
216 const struct dce_abm_shift *abm_shift;
217 const struct dce_abm_mask *abm_mask;
218};
219
220struct abm *dce_abm_create(
221 struct dc_context *ctx,
222 const struct dce_abm_registers *regs,
223 const struct dce_abm_shift *abm_shift,
224 const struct dce_abm_mask *abm_mask);
225
226void dce_abm_destroy(struct abm **abm);
227
228#endif /* _DCE_ABM_H_ */