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1/*
2 * sama5d4.dtsi - Device Tree Include file for SAMA5D4 family SoC
3 *
4 * Copyright (C) 2014 Atmel,
5 * 2014 Nicolas Ferre <nicolas.ferre@atmel.com>
6 *
7 * This file is dual-licensed: you can use it either under the terms
8 * of the GPL or the X11 license, at your option. Note that this dual
9 * licensing only applies to this file, and not this project as a
10 * whole.
11 *
12 * a) This file is free software; you can redistribute it and/or
13 * modify it under the terms of the GNU General Public License as
14 * published by the Free Software Foundation; either version 2 of the
15 * License, or (at your option) any later version.
16 *
17 * This file is distributed in the hope that it will be useful,
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 * GNU General Public License for more details.
21 *
22 * Or, alternatively,
23 *
24 * b) Permission is hereby granted, free of charge, to any person
25 * obtaining a copy of this software and associated documentation
26 * files (the "Software"), to deal in the Software without
27 * restriction, including without limitation the rights to use,
28 * copy, modify, merge, publish, distribute, sublicense, and/or
29 * sell copies of the Software, and to permit persons to whom the
30 * Software is furnished to do so, subject to the following
31 * conditions:
32 *
33 * The above copyright notice and this permission notice shall be
34 * included in all copies or substantial portions of the Software.
35 *
36 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
37 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
38 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
39 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
40 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
41 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
42 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
43 * OTHER DEALINGS IN THE SOFTWARE.
44 */
45
46#include "skeleton.dtsi"
47#include <dt-bindings/clock/at91.h>
48#include <dt-bindings/dma/at91.h>
49#include <dt-bindings/pinctrl/at91.h>
50#include <dt-bindings/interrupt-controller/irq.h>
51#include <dt-bindings/gpio/gpio.h>
52
53/ {
54 model = "Atmel SAMA5D4 family SoC";
55 compatible = "atmel,sama5d4";
56 interrupt-parent = <&aic>;
57
58 aliases {
59 serial0 = &usart3;
60 serial1 = &usart4;
61 serial2 = &usart2;
62 serial3 = &usart0;
63 serial4 = &usart1;
64 serial5 = &uart0;
65 serial6 = &uart1;
66 gpio0 = &pioA;
67 gpio1 = &pioB;
68 gpio2 = &pioC;
69 gpio3 = &pioD;
70 gpio4 = &pioE;
71 pwm0 = &pwm0;
72 ssc0 = &ssc0;
73 ssc1 = &ssc1;
74 tcb0 = &tcb0;
75 tcb1 = &tcb1;
76 i2c0 = &i2c0;
77 i2c1 = &i2c1;
78 i2c2 = &i2c2;
79 };
80 cpus {
81 #address-cells = <1>;
82 #size-cells = <0>;
83
84 cpu@0 {
85 device_type = "cpu";
86 compatible = "arm,cortex-a5";
87 reg = <0>;
88 next-level-cache = <&L2>;
89 };
90 };
91
92 memory {
93 reg = <0x20000000 0x20000000>;
94 };
95
96 clocks {
97 slow_xtal: slow_xtal {
98 compatible = "fixed-clock";
99 #clock-cells = <0>;
100 clock-frequency = <0>;
101 };
102
103 main_xtal: main_xtal {
104 compatible = "fixed-clock";
105 #clock-cells = <0>;
106 clock-frequency = <0>;
107 };
108
109 adc_op_clk: adc_op_clk{
110 compatible = "fixed-clock";
111 #clock-cells = <0>;
112 clock-frequency = <1000000>;
113 };
114 };
115
116 ns_sram: sram@210000 {
117 compatible = "mmio-sram";
118 reg = <0x00210000 0x10000>;
119 };
120
121 ahb {
122 compatible = "simple-bus";
123 #address-cells = <1>;
124 #size-cells = <1>;
125 ranges;
126
127 nfc_sram: sram@100000 {
128 compatible = "mmio-sram";
129 no-memory-wc;
130 reg = <0x100000 0x2400>;
131 };
132
133 usb0: gadget@400000 {
134 #address-cells = <1>;
135 #size-cells = <0>;
136 compatible = "atmel,sama5d3-udc";
137 reg = <0x00400000 0x100000
138 0xfc02c000 0x4000>;
139 interrupts = <47 IRQ_TYPE_LEVEL_HIGH 2>;
140 clocks = <&udphs_clk>, <&utmi>;
141 clock-names = "pclk", "hclk";
142 status = "disabled";
143
144 ep@0 {
145 reg = <0>;
146 atmel,fifo-size = <64>;
147 atmel,nb-banks = <1>;
148 };
149
150 ep@1 {
151 reg = <1>;
152 atmel,fifo-size = <1024>;
153 atmel,nb-banks = <3>;
154 atmel,can-dma;
155 atmel,can-isoc;
156 };
157
158 ep@2 {
159 reg = <2>;
160 atmel,fifo-size = <1024>;
161 atmel,nb-banks = <3>;
162 atmel,can-dma;
163 atmel,can-isoc;
164 };
165
166 ep@3 {
167 reg = <3>;
168 atmel,fifo-size = <1024>;
169 atmel,nb-banks = <2>;
170 atmel,can-dma;
171 atmel,can-isoc;
172 };
173
174 ep@4 {
175 reg = <4>;
176 atmel,fifo-size = <1024>;
177 atmel,nb-banks = <2>;
178 atmel,can-dma;
179 atmel,can-isoc;
180 };
181
182 ep@5 {
183 reg = <5>;
184 atmel,fifo-size = <1024>;
185 atmel,nb-banks = <2>;
186 atmel,can-dma;
187 atmel,can-isoc;
188 };
189
190 ep@6 {
191 reg = <6>;
192 atmel,fifo-size = <1024>;
193 atmel,nb-banks = <2>;
194 atmel,can-dma;
195 atmel,can-isoc;
196 };
197
198 ep@7 {
199 reg = <7>;
200 atmel,fifo-size = <1024>;
201 atmel,nb-banks = <2>;
202 atmel,can-dma;
203 atmel,can-isoc;
204 };
205
206 ep@8 {
207 reg = <8>;
208 atmel,fifo-size = <1024>;
209 atmel,nb-banks = <2>;
210 atmel,can-isoc;
211 };
212
213 ep@9 {
214 reg = <9>;
215 atmel,fifo-size = <1024>;
216 atmel,nb-banks = <2>;
217 atmel,can-isoc;
218 };
219
220 ep@10 {
221 reg = <10>;
222 atmel,fifo-size = <1024>;
223 atmel,nb-banks = <2>;
224 atmel,can-isoc;
225 };
226
227 ep@11 {
228 reg = <11>;
229 atmel,fifo-size = <1024>;
230 atmel,nb-banks = <2>;
231 atmel,can-isoc;
232 };
233
234 ep@12 {
235 reg = <12>;
236 atmel,fifo-size = <1024>;
237 atmel,nb-banks = <2>;
238 atmel,can-isoc;
239 };
240
241 ep@13 {
242 reg = <13>;
243 atmel,fifo-size = <1024>;
244 atmel,nb-banks = <2>;
245 atmel,can-isoc;
246 };
247
248 ep@14 {
249 reg = <14>;
250 atmel,fifo-size = <1024>;
251 atmel,nb-banks = <2>;
252 atmel,can-isoc;
253 };
254
255 ep@15 {
256 reg = <15>;
257 atmel,fifo-size = <1024>;
258 atmel,nb-banks = <2>;
259 atmel,can-isoc;
260 };
261 };
262
263 usb1: ohci@500000 {
264 compatible = "atmel,at91rm9200-ohci", "usb-ohci";
265 reg = <0x00500000 0x100000>;
266 interrupts = <46 IRQ_TYPE_LEVEL_HIGH 2>;
267 clocks = <&uhphs_clk>, <&uhphs_clk>, <&uhpck>;
268 clock-names = "ohci_clk", "hclk", "uhpck";
269 status = "disabled";
270 };
271
272 usb2: ehci@600000 {
273 compatible = "atmel,at91sam9g45-ehci", "usb-ehci";
274 reg = <0x00600000 0x100000>;
275 interrupts = <46 IRQ_TYPE_LEVEL_HIGH 2>;
276 clocks = <&utmi>, <&uhphs_clk>;
277 clock-names = "usb_clk", "ehci_clk";
278 status = "disabled";
279 };
280
281 L2: cache-controller@a00000 {
282 compatible = "arm,pl310-cache";
283 reg = <0x00a00000 0x1000>;
284 interrupts = <67 IRQ_TYPE_LEVEL_HIGH 4>;
285 cache-unified;
286 cache-level = <2>;
287 };
288
289 ebi: ebi@10000000 {
290 compatible = "atmel,sama5d3-ebi";
291 #address-cells = <2>;
292 #size-cells = <1>;
293 atmel,smc = <&hsmc>;
294 reg = <0x10000000 0x10000000
295 0x60000000 0x28000000>;
296 ranges = <0x0 0x0 0x10000000 0x10000000
297 0x1 0x0 0x60000000 0x10000000
298 0x2 0x0 0x70000000 0x10000000
299 0x3 0x0 0x80000000 0x8000000>;
300 clocks = <&mck>;
301 status = "disabled";
302
303 nand_controller: nand-controller {
304 compatible = "atmel,sama5d3-nand-controller";
305 atmel,nfc-sram = <&nfc_sram>;
306 atmel,nfc-io = <&nfc_io>;
307 ecc-engine = <&pmecc>;
308 #address-cells = <2>;
309 #size-cells = <1>;
310 ranges;
311 status = "disabled";
312 };
313 };
314
315 nfc_io: nfc-io@90000000 {
316 compatible = "atmel,sama5d3-nfc-io", "syscon";
317 reg = <0x90000000 0x8000000>;
318 };
319
320 apb {
321 compatible = "simple-bus";
322 #address-cells = <1>;
323 #size-cells = <1>;
324 ranges;
325
326 hlcdc: hlcdc@f0000000 {
327 compatible = "atmel,sama5d4-hlcdc";
328 reg = <0xf0000000 0x4000>;
329 interrupts = <51 IRQ_TYPE_LEVEL_HIGH 0>;
330 clocks = <&lcdc_clk>, <&lcdck>, <&clk32k>;
331 clock-names = "periph_clk","sys_clk", "slow_clk";
332 status = "disabled";
333
334 hlcdc-display-controller {
335 compatible = "atmel,hlcdc-display-controller";
336 #address-cells = <1>;
337 #size-cells = <0>;
338
339 port@0 {
340 #address-cells = <1>;
341 #size-cells = <0>;
342 reg = <0>;
343 };
344 };
345
346 hlcdc_pwm: hlcdc-pwm {
347 compatible = "atmel,hlcdc-pwm";
348 pinctrl-names = "default";
349 pinctrl-0 = <&pinctrl_lcd_pwm>;
350 #pwm-cells = <3>;
351 };
352 };
353
354 dma1: dma-controller@f0004000 {
355 compatible = "atmel,sama5d4-dma";
356 reg = <0xf0004000 0x200>;
357 interrupts = <50 IRQ_TYPE_LEVEL_HIGH 0>;
358 #dma-cells = <1>;
359 clocks = <&dma1_clk>;
360 clock-names = "dma_clk";
361 };
362
363 isi: isi@f0008000 {
364 compatible = "atmel,at91sam9g45-isi";
365 reg = <0xf0008000 0x4000>;
366 interrupts = <52 IRQ_TYPE_LEVEL_HIGH 5>;
367 pinctrl-names = "default";
368 pinctrl-0 = <&pinctrl_isi_data_0_7>;
369 clocks = <&isi_clk>;
370 clock-names = "isi_clk";
371 status = "disabled";
372 port {
373 #address-cells = <1>;
374 #size-cells = <0>;
375 };
376 };
377
378 ramc0: ramc@f0010000 {
379 compatible = "atmel,sama5d3-ddramc";
380 reg = <0xf0010000 0x200>;
381 clocks = <&ddrck>, <&mpddr_clk>;
382 clock-names = "ddrck", "mpddr";
383 };
384
385 dma0: dma-controller@f0014000 {
386 compatible = "atmel,sama5d4-dma";
387 reg = <0xf0014000 0x200>;
388 interrupts = <8 IRQ_TYPE_LEVEL_HIGH 0>;
389 #dma-cells = <1>;
390 clocks = <&dma0_clk>;
391 clock-names = "dma_clk";
392 };
393
394 pmc: pmc@f0018000 {
395 compatible = "atmel,sama5d3-pmc", "syscon";
396 reg = <0xf0018000 0x120>;
397 interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
398 interrupt-controller;
399 #address-cells = <1>;
400 #size-cells = <0>;
401 #interrupt-cells = <1>;
402
403 main_rc_osc: main_rc_osc {
404 compatible = "atmel,at91sam9x5-clk-main-rc-osc";
405 #clock-cells = <0>;
406 interrupt-parent = <&pmc>;
407 interrupts = <AT91_PMC_MOSCRCS>;
408 clock-frequency = <12000000>;
409 clock-accuracy = <100000000>;
410 };
411
412 main_osc: main_osc {
413 compatible = "atmel,at91rm9200-clk-main-osc";
414 #clock-cells = <0>;
415 interrupt-parent = <&pmc>;
416 interrupts = <AT91_PMC_MOSCS>;
417 clocks = <&main_xtal>;
418 };
419
420 main: mainck {
421 compatible = "atmel,at91sam9x5-clk-main";
422 #clock-cells = <0>;
423 interrupt-parent = <&pmc>;
424 interrupts = <AT91_PMC_MOSCSELS>;
425 clocks = <&main_rc_osc &main_osc>;
426 };
427
428 plla: pllack {
429 compatible = "atmel,sama5d3-clk-pll";
430 #clock-cells = <0>;
431 interrupt-parent = <&pmc>;
432 interrupts = <AT91_PMC_LOCKA>;
433 clocks = <&main>;
434 reg = <0>;
435 atmel,clk-input-range = <12000000 12000000>;
436 #atmel,pll-clk-output-range-cells = <4>;
437 atmel,pll-clk-output-ranges = <600000000 1200000000 0 0>;
438 };
439
440 plladiv: plladivck {
441 compatible = "atmel,at91sam9x5-clk-plldiv";
442 #clock-cells = <0>;
443 clocks = <&plla>;
444 };
445
446 utmi: utmick {
447 compatible = "atmel,at91sam9x5-clk-utmi";
448 #clock-cells = <0>;
449 interrupt-parent = <&pmc>;
450 interrupts = <AT91_PMC_LOCKU>;
451 clocks = <&main>;
452 };
453
454 mck: masterck {
455 compatible = "atmel,at91sam9x5-clk-master";
456 #clock-cells = <0>;
457 interrupt-parent = <&pmc>;
458 interrupts = <AT91_PMC_MCKRDY>;
459 clocks = <&clk32k>, <&main>, <&plladiv>, <&utmi>;
460 atmel,clk-output-range = <125000000 200000000>;
461 atmel,clk-divisors = <1 2 4 3>;
462 };
463
464 h32ck: h32mxck {
465 #clock-cells = <0>;
466 compatible = "atmel,sama5d4-clk-h32mx";
467 clocks = <&mck>;
468 };
469
470 usb: usbck {
471 compatible = "atmel,at91sam9x5-clk-usb";
472 #clock-cells = <0>;
473 clocks = <&plladiv>, <&utmi>;
474 };
475
476 prog: progck {
477 compatible = "atmel,at91sam9x5-clk-programmable";
478 #address-cells = <1>;
479 #size-cells = <0>;
480 interrupt-parent = <&pmc>;
481 clocks = <&clk32k>, <&main>, <&plladiv>, <&utmi>, <&mck>;
482
483 prog0: prog0 {
484 #clock-cells = <0>;
485 reg = <0>;
486 interrupts = <AT91_PMC_PCKRDY(0)>;
487 };
488
489 prog1: prog1 {
490 #clock-cells = <0>;
491 reg = <1>;
492 interrupts = <AT91_PMC_PCKRDY(1)>;
493 };
494
495 prog2: prog2 {
496 #clock-cells = <0>;
497 reg = <2>;
498 interrupts = <AT91_PMC_PCKRDY(2)>;
499 };
500 };
501
502 smd: smdclk {
503 compatible = "atmel,at91sam9x5-clk-smd";
504 #clock-cells = <0>;
505 clocks = <&plladiv>, <&utmi>;
506 };
507
508 systemck {
509 compatible = "atmel,at91rm9200-clk-system";
510 #address-cells = <1>;
511 #size-cells = <0>;
512
513 ddrck: ddrck {
514 #clock-cells = <0>;
515 reg = <2>;
516 clocks = <&mck>;
517 };
518
519 lcdck: lcdck {
520 #clock-cells = <0>;
521 reg = <3>;
522 clocks = <&mck>;
523 };
524
525 smdck: smdck {
526 #clock-cells = <0>;
527 reg = <4>;
528 clocks = <&smd>;
529 };
530
531 uhpck: uhpck {
532 #clock-cells = <0>;
533 reg = <6>;
534 clocks = <&usb>;
535 };
536
537 udpck: udpck {
538 #clock-cells = <0>;
539 reg = <7>;
540 clocks = <&usb>;
541 };
542
543 pck0: pck0 {
544 #clock-cells = <0>;
545 reg = <8>;
546 clocks = <&prog0>;
547 };
548
549 pck1: pck1 {
550 #clock-cells = <0>;
551 reg = <9>;
552 clocks = <&prog1>;
553 };
554
555 pck2: pck2 {
556 #clock-cells = <0>;
557 reg = <10>;
558 clocks = <&prog2>;
559 };
560 };
561
562 periph32ck {
563 compatible = "atmel,at91sam9x5-clk-peripheral";
564 #address-cells = <1>;
565 #size-cells = <0>;
566 clocks = <&h32ck>;
567
568 pioD_clk: pioD_clk {
569 #clock-cells = <0>;
570 reg = <5>;
571 };
572
573 usart0_clk: usart0_clk {
574 #clock-cells = <0>;
575 reg = <6>;
576 };
577
578 usart1_clk: usart1_clk {
579 #clock-cells = <0>;
580 reg = <7>;
581 };
582
583 icm_clk: icm_clk {
584 #clock-cells = <0>;
585 reg = <9>;
586 };
587
588 aes_clk: aes_clk {
589 #clock-cells = <0>;
590 reg = <12>;
591 };
592
593 tdes_clk: tdes_clk {
594 #clock-cells = <0>;
595 reg = <14>;
596 };
597
598 sha_clk: sha_clk {
599 #clock-cells = <0>;
600 reg = <15>;
601 };
602
603 matrix1_clk: matrix1_clk {
604 #clock-cells = <0>;
605 reg = <17>;
606 };
607
608 hsmc_clk: hsmc_clk {
609 #clock-cells = <0>;
610 reg = <22>;
611 };
612
613 pioA_clk: pioA_clk {
614 #clock-cells = <0>;
615 reg = <23>;
616 };
617
618 pioB_clk: pioB_clk {
619 #clock-cells = <0>;
620 reg = <24>;
621 };
622
623 pioC_clk: pioC_clk {
624 #clock-cells = <0>;
625 reg = <25>;
626 };
627
628 pioE_clk: pioE_clk {
629 #clock-cells = <0>;
630 reg = <26>;
631 };
632
633 uart0_clk: uart0_clk {
634 #clock-cells = <0>;
635 reg = <27>;
636 };
637
638 uart1_clk: uart1_clk {
639 #clock-cells = <0>;
640 reg = <28>;
641 };
642
643 usart2_clk: usart2_clk {
644 #clock-cells = <0>;
645 reg = <29>;
646 };
647
648 usart3_clk: usart3_clk {
649 #clock-cells = <0>;
650 reg = <30>;
651 };
652
653 usart4_clk: usart4_clk {
654 #clock-cells = <0>;
655 reg = <31>;
656 };
657
658 twi0_clk: twi0_clk {
659 reg = <32>;
660 #clock-cells = <0>;
661 };
662
663 twi1_clk: twi1_clk {
664 #clock-cells = <0>;
665 reg = <33>;
666 };
667
668 twi2_clk: twi2_clk {
669 #clock-cells = <0>;
670 reg = <34>;
671 };
672
673 mci0_clk: mci0_clk {
674 #clock-cells = <0>;
675 reg = <35>;
676 };
677
678 mci1_clk: mci1_clk {
679 #clock-cells = <0>;
680 reg = <36>;
681 };
682
683 spi0_clk: spi0_clk {
684 #clock-cells = <0>;
685 reg = <37>;
686 };
687
688 spi1_clk: spi1_clk {
689 #clock-cells = <0>;
690 reg = <38>;
691 };
692
693 spi2_clk: spi2_clk {
694 #clock-cells = <0>;
695 reg = <39>;
696 };
697
698 tcb0_clk: tcb0_clk {
699 #clock-cells = <0>;
700 reg = <40>;
701 };
702
703 tcb1_clk: tcb1_clk {
704 #clock-cells = <0>;
705 reg = <41>;
706 };
707
708 tcb2_clk: tcb2_clk {
709 #clock-cells = <0>;
710 reg = <42>;
711 };
712
713 pwm_clk: pwm_clk {
714 #clock-cells = <0>;
715 reg = <43>;
716 };
717
718 adc_clk: adc_clk {
719 #clock-cells = <0>;
720 reg = <44>;
721 };
722
723 dbgu_clk: dbgu_clk {
724 #clock-cells = <0>;
725 reg = <45>;
726 };
727
728 uhphs_clk: uhphs_clk {
729 #clock-cells = <0>;
730 reg = <46>;
731 };
732
733 udphs_clk: udphs_clk {
734 #clock-cells = <0>;
735 reg = <47>;
736 };
737
738 ssc0_clk: ssc0_clk {
739 #clock-cells = <0>;
740 reg = <48>;
741 };
742
743 ssc1_clk: ssc1_clk {
744 #clock-cells = <0>;
745 reg = <49>;
746 };
747
748 trng_clk: trng_clk {
749 #clock-cells = <0>;
750 reg = <53>;
751 };
752
753 macb0_clk: macb0_clk {
754 #clock-cells = <0>;
755 reg = <54>;
756 };
757
758 macb1_clk: macb1_clk {
759 #clock-cells = <0>;
760 reg = <55>;
761 };
762
763 fuse_clk: fuse_clk {
764 #clock-cells = <0>;
765 reg = <57>;
766 };
767
768 securam_clk: securam_clk {
769 #clock-cells = <0>;
770 reg = <59>;
771 };
772
773 smd_clk: smd_clk {
774 #clock-cells = <0>;
775 reg = <61>;
776 };
777
778 twi3_clk: twi3_clk {
779 #clock-cells = <0>;
780 reg = <62>;
781 };
782
783 catb_clk: catb_clk {
784 #clock-cells = <0>;
785 reg = <63>;
786 };
787 };
788
789 periph64ck {
790 compatible = "atmel,at91sam9x5-clk-peripheral";
791 #address-cells = <1>;
792 #size-cells = <0>;
793 clocks = <&mck>;
794
795 dma0_clk: dma0_clk {
796 #clock-cells = <0>;
797 reg = <8>;
798 };
799
800 cpkcc_clk: cpkcc_clk {
801 #clock-cells = <0>;
802 reg = <10>;
803 };
804
805 aesb_clk: aesb_clk {
806 #clock-cells = <0>;
807 reg = <13>;
808 };
809
810 mpddr_clk: mpddr_clk {
811 #clock-cells = <0>;
812 reg = <16>;
813 };
814
815 matrix0_clk: matrix0_clk {
816 #clock-cells = <0>;
817 reg = <18>;
818 };
819
820 vdec_clk: vdec_clk {
821 #clock-cells = <0>;
822 reg = <19>;
823 };
824
825 dma1_clk: dma1_clk {
826 #clock-cells = <0>;
827 reg = <50>;
828 };
829
830 lcdc_clk: lcdc_clk {
831 #clock-cells = <0>;
832 reg = <51>;
833 };
834
835 isi_clk: isi_clk {
836 #clock-cells = <0>;
837 reg = <52>;
838 };
839 };
840 };
841
842 mmc0: mmc@f8000000 {
843 compatible = "atmel,hsmci";
844 reg = <0xf8000000 0x600>;
845 interrupts = <35 IRQ_TYPE_LEVEL_HIGH 0>;
846 dmas = <&dma1
847 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)
848 | AT91_XDMAC_DT_PERID(0))>;
849 dma-names = "rxtx";
850 pinctrl-names = "default";
851 pinctrl-0 = <&pinctrl_mmc0_clk_cmd_dat0 &pinctrl_mmc0_dat1_3>;
852 status = "disabled";
853 #address-cells = <1>;
854 #size-cells = <0>;
855 clocks = <&mci0_clk>;
856 clock-names = "mci_clk";
857 };
858
859 uart0: serial@f8004000 {
860 compatible = "atmel,at91sam9260-usart";
861 reg = <0xf8004000 0x100>;
862 interrupts = <27 IRQ_TYPE_LEVEL_HIGH 5>;
863 dmas = <&dma0
864 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)
865 | AT91_XDMAC_DT_PERID(22))>,
866 <&dma0
867 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)
868 | AT91_XDMAC_DT_PERID(23))>;
869 dma-names = "tx", "rx";
870 pinctrl-names = "default";
871 pinctrl-0 = <&pinctrl_uart0>;
872 clocks = <&uart0_clk>;
873 clock-names = "usart";
874 status = "disabled";
875 };
876
877 ssc0: ssc@f8008000 {
878 compatible = "atmel,at91sam9g45-ssc";
879 reg = <0xf8008000 0x4000>;
880 interrupts = <48 IRQ_TYPE_LEVEL_HIGH 0>;
881 pinctrl-names = "default";
882 pinctrl-0 = <&pinctrl_ssc0_tx &pinctrl_ssc0_rx>;
883 dmas = <&dma1
884 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)
885 | AT91_XDMAC_DT_PERID(26))>,
886 <&dma1
887 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)
888 | AT91_XDMAC_DT_PERID(27))>;
889 dma-names = "tx", "rx";
890 clocks = <&ssc0_clk>;
891 clock-names = "pclk";
892 status = "disabled";
893 };
894
895 pwm0: pwm@f800c000 {
896 compatible = "atmel,sama5d3-pwm";
897 reg = <0xf800c000 0x300>;
898 interrupts = <43 IRQ_TYPE_LEVEL_HIGH 4>;
899 #pwm-cells = <3>;
900 clocks = <&pwm_clk>;
901 status = "disabled";
902 };
903
904 spi0: spi@f8010000 {
905 #address-cells = <1>;
906 #size-cells = <0>;
907 compatible = "atmel,at91rm9200-spi";
908 reg = <0xf8010000 0x100>;
909 interrupts = <37 IRQ_TYPE_LEVEL_HIGH 3>;
910 dmas = <&dma1
911 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)
912 | AT91_XDMAC_DT_PERID(10))>,
913 <&dma1
914 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)
915 | AT91_XDMAC_DT_PERID(11))>;
916 dma-names = "tx", "rx";
917 pinctrl-names = "default";
918 pinctrl-0 = <&pinctrl_spi0>;
919 clocks = <&spi0_clk>;
920 clock-names = "spi_clk";
921 status = "disabled";
922 };
923
924 i2c0: i2c@f8014000 {
925 compatible = "atmel,sama5d4-i2c";
926 reg = <0xf8014000 0x4000>;
927 interrupts = <32 IRQ_TYPE_LEVEL_HIGH 6>;
928 dmas = <&dma1
929 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)
930 | AT91_XDMAC_DT_PERID(2))>,
931 <&dma1
932 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)
933 | AT91_XDMAC_DT_PERID(3))>;
934 dma-names = "tx", "rx";
935 pinctrl-names = "default";
936 pinctrl-0 = <&pinctrl_i2c0>;
937 #address-cells = <1>;
938 #size-cells = <0>;
939 clocks = <&twi0_clk>;
940 status = "disabled";
941 };
942
943 i2c1: i2c@f8018000 {
944 compatible = "atmel,sama5d4-i2c";
945 reg = <0xf8018000 0x4000>;
946 interrupts = <33 IRQ_TYPE_LEVEL_HIGH 6>;
947 dmas = <&dma0
948 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)
949 | AT91_XDMAC_DT_PERID(4))>,
950 <&dma0
951 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)
952 | AT91_XDMAC_DT_PERID(5))>;
953 dma-names = "tx", "rx";
954 pinctrl-names = "default";
955 pinctrl-0 = <&pinctrl_i2c1>;
956 #address-cells = <1>;
957 #size-cells = <0>;
958 clocks = <&twi1_clk>;
959 status = "disabled";
960 };
961
962 tcb0: timer@f801c000 {
963 compatible = "atmel,at91sam9x5-tcb";
964 reg = <0xf801c000 0x100>;
965 interrupts = <40 IRQ_TYPE_LEVEL_HIGH 0>;
966 clocks = <&tcb0_clk>, <&clk32k>;
967 clock-names = "t0_clk", "slow_clk";
968 };
969
970 macb0: ethernet@f8020000 {
971 compatible = "atmel,sama5d4-gem";
972 reg = <0xf8020000 0x100>;
973 interrupts = <54 IRQ_TYPE_LEVEL_HIGH 3>;
974 pinctrl-names = "default";
975 pinctrl-0 = <&pinctrl_macb0_rmii>;
976 #address-cells = <1>;
977 #size-cells = <0>;
978 clocks = <&macb0_clk>, <&macb0_clk>;
979 clock-names = "hclk", "pclk";
980 status = "disabled";
981 };
982
983 i2c2: i2c@f8024000 {
984 compatible = "atmel,sama5d4-i2c";
985 reg = <0xf8024000 0x4000>;
986 interrupts = <34 IRQ_TYPE_LEVEL_HIGH 6>;
987 dmas = <&dma1
988 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)
989 | AT91_XDMAC_DT_PERID(6))>,
990 <&dma1
991 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)
992 | AT91_XDMAC_DT_PERID(7))>;
993 dma-names = "tx", "rx";
994 pinctrl-names = "default";
995 pinctrl-0 = <&pinctrl_i2c2>;
996 #address-cells = <1>;
997 #size-cells = <0>;
998 clocks = <&twi2_clk>;
999 status = "disabled";
1000 };
1001
1002 sfr: sfr@f8028000 {
1003 compatible = "atmel,sama5d4-sfr", "syscon";
1004 reg = <0xf8028000 0x60>;
1005 };
1006
1007 usart0: serial@f802c000 {
1008 compatible = "atmel,at91sam9260-usart";
1009 reg = <0xf802c000 0x100>;
1010 interrupts = <6 IRQ_TYPE_LEVEL_HIGH 5>;
1011 dmas = <&dma0
1012 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)
1013 | AT91_XDMAC_DT_PERID(36))>,
1014 <&dma0
1015 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)
1016 | AT91_XDMAC_DT_PERID(37))>;
1017 dma-names = "tx", "rx";
1018 pinctrl-names = "default";
1019 pinctrl-0 = <&pinctrl_usart0 &pinctrl_usart0_rts &pinctrl_usart0_cts>;
1020 clocks = <&usart0_clk>;
1021 clock-names = "usart";
1022 status = "disabled";
1023 };
1024
1025 usart1: serial@f8030000 {
1026 compatible = "atmel,at91sam9260-usart";
1027 reg = <0xf8030000 0x100>;
1028 interrupts = <7 IRQ_TYPE_LEVEL_HIGH 5>;
1029 dmas = <&dma0
1030 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)
1031 | AT91_XDMAC_DT_PERID(38))>,
1032 <&dma0
1033 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)
1034 | AT91_XDMAC_DT_PERID(39))>;
1035 dma-names = "tx", "rx";
1036 pinctrl-names = "default";
1037 pinctrl-0 = <&pinctrl_usart1 &pinctrl_usart1_rts &pinctrl_usart1_cts>;
1038 clocks = <&usart1_clk>;
1039 clock-names = "usart";
1040 status = "disabled";
1041 };
1042
1043 mmc1: mmc@fc000000 {
1044 compatible = "atmel,hsmci";
1045 reg = <0xfc000000 0x600>;
1046 interrupts = <36 IRQ_TYPE_LEVEL_HIGH 0>;
1047 dmas = <&dma1
1048 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)
1049 | AT91_XDMAC_DT_PERID(1))>;
1050 dma-names = "rxtx";
1051 pinctrl-names = "default";
1052 pinctrl-0 = <&pinctrl_mmc1_clk_cmd_dat0 &pinctrl_mmc1_dat1_3>;
1053 status = "disabled";
1054 #address-cells = <1>;
1055 #size-cells = <0>;
1056 clocks = <&mci1_clk>;
1057 clock-names = "mci_clk";
1058 };
1059
1060 uart1: serial@fc004000 {
1061 compatible = "atmel,at91sam9260-usart";
1062 reg = <0xfc004000 0x100>;
1063 interrupts = <28 IRQ_TYPE_LEVEL_HIGH 5>;
1064 dmas = <&dma0
1065 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)
1066 | AT91_XDMAC_DT_PERID(24))>,
1067 <&dma0
1068 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)
1069 | AT91_XDMAC_DT_PERID(25))>;
1070 dma-names = "tx", "rx";
1071 pinctrl-names = "default";
1072 pinctrl-0 = <&pinctrl_uart1>;
1073 clocks = <&uart1_clk>;
1074 clock-names = "usart";
1075 status = "disabled";
1076 };
1077
1078 usart2: serial@fc008000 {
1079 compatible = "atmel,at91sam9260-usart";
1080 reg = <0xfc008000 0x100>;
1081 interrupts = <29 IRQ_TYPE_LEVEL_HIGH 5>;
1082 dmas = <&dma1
1083 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)
1084 | AT91_XDMAC_DT_PERID(16))>,
1085 <&dma1
1086 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)
1087 | AT91_XDMAC_DT_PERID(17))>;
1088 dma-names = "tx", "rx";
1089 pinctrl-names = "default";
1090 pinctrl-0 = <&pinctrl_usart2 &pinctrl_usart2_rts &pinctrl_usart2_cts>;
1091 clocks = <&usart2_clk>;
1092 clock-names = "usart";
1093 status = "disabled";
1094 };
1095
1096 usart3: serial@fc00c000 {
1097 compatible = "atmel,at91sam9260-usart";
1098 reg = <0xfc00c000 0x100>;
1099 interrupts = <30 IRQ_TYPE_LEVEL_HIGH 5>;
1100 dmas = <&dma1
1101 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)
1102 | AT91_XDMAC_DT_PERID(18))>,
1103 <&dma1
1104 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)
1105 | AT91_XDMAC_DT_PERID(19))>;
1106 dma-names = "tx", "rx";
1107 pinctrl-names = "default";
1108 pinctrl-0 = <&pinctrl_usart3>;
1109 clocks = <&usart3_clk>;
1110 clock-names = "usart";
1111 status = "disabled";
1112 };
1113
1114 usart4: serial@fc010000 {
1115 compatible = "atmel,at91sam9260-usart";
1116 reg = <0xfc010000 0x100>;
1117 interrupts = <31 IRQ_TYPE_LEVEL_HIGH 5>;
1118 dmas = <&dma1
1119 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)
1120 | AT91_XDMAC_DT_PERID(20))>,
1121 <&dma1
1122 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)
1123 | AT91_XDMAC_DT_PERID(21))>;
1124 dma-names = "tx", "rx";
1125 pinctrl-names = "default";
1126 pinctrl-0 = <&pinctrl_usart4>;
1127 clocks = <&usart4_clk>;
1128 clock-names = "usart";
1129 status = "disabled";
1130 };
1131
1132 ssc1: ssc@fc014000 {
1133 compatible = "atmel,at91sam9g45-ssc";
1134 reg = <0xfc014000 0x4000>;
1135 interrupts = <49 IRQ_TYPE_LEVEL_HIGH 0>;
1136 pinctrl-names = "default";
1137 pinctrl-0 = <&pinctrl_ssc1_tx &pinctrl_ssc1_rx>;
1138 dmas = <&dma1
1139 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)
1140 | AT91_XDMAC_DT_PERID(28))>,
1141 <&dma1
1142 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)
1143 | AT91_XDMAC_DT_PERID(29))>;
1144 dma-names = "tx", "rx";
1145 clocks = <&ssc1_clk>;
1146 clock-names = "pclk";
1147 status = "disabled";
1148 };
1149
1150 spi1: spi@fc018000 {
1151 #address-cells = <1>;
1152 #size-cells = <0>;
1153 compatible = "atmel,at91rm9200-spi";
1154 reg = <0xfc018000 0x100>;
1155 interrupts = <38 IRQ_TYPE_LEVEL_HIGH 3>;
1156 dmas = <&dma1
1157 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)
1158 | AT91_XDMAC_DT_PERID(12))>,
1159 <&dma1
1160 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)
1161 | AT91_XDMAC_DT_PERID(13))>;
1162 dma-names = "tx", "rx";
1163 pinctrl-names = "default";
1164 pinctrl-0 = <&pinctrl_spi1>;
1165 clocks = <&spi1_clk>;
1166 clock-names = "spi_clk";
1167 status = "disabled";
1168 };
1169
1170 spi2: spi@fc01c000 {
1171 #address-cells = <1>;
1172 #size-cells = <0>;
1173 compatible = "atmel,at91rm9200-spi";
1174 reg = <0xfc01c000 0x100>;
1175 interrupts = <39 IRQ_TYPE_LEVEL_HIGH 3>;
1176 dmas = <&dma0
1177 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)
1178 | AT91_XDMAC_DT_PERID(14))>,
1179 <&dma0
1180 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)
1181 | AT91_XDMAC_DT_PERID(15))>;
1182 dma-names = "tx", "rx";
1183 pinctrl-names = "default";
1184 pinctrl-0 = <&pinctrl_spi2>;
1185 clocks = <&spi2_clk>;
1186 clock-names = "spi_clk";
1187 status = "disabled";
1188 };
1189
1190 tcb1: timer@fc020000 {
1191 compatible = "atmel,at91sam9x5-tcb";
1192 reg = <0xfc020000 0x100>;
1193 interrupts = <41 IRQ_TYPE_LEVEL_HIGH 0>;
1194 clocks = <&tcb1_clk>, <&clk32k>;
1195 clock-names = "t0_clk", "slow_clk";
1196 };
1197
1198 macb1: ethernet@fc028000 {
1199 compatible = "atmel,sama5d4-gem";
1200 reg = <0xfc028000 0x100>;
1201 interrupts = <55 IRQ_TYPE_LEVEL_HIGH 3>;
1202 pinctrl-names = "default";
1203 pinctrl-0 = <&pinctrl_macb1_rmii>;
1204 #address-cells = <1>;
1205 #size-cells = <0>;
1206 clocks = <&macb1_clk>, <&macb1_clk>;
1207 clock-names = "hclk", "pclk";
1208 status = "disabled";
1209 };
1210
1211 trng@fc030000 {
1212 compatible = "atmel,at91sam9g45-trng";
1213 reg = <0xfc030000 0x100>;
1214 interrupts = <53 IRQ_TYPE_LEVEL_HIGH 0>;
1215 clocks = <&trng_clk>;
1216 };
1217
1218 adc0: adc@fc034000 {
1219 compatible = "atmel,at91sam9x5-adc";
1220 reg = <0xfc034000 0x100>;
1221 interrupts = <44 IRQ_TYPE_LEVEL_HIGH 5>;
1222 clocks = <&adc_clk>,
1223 <&adc_op_clk>;
1224 clock-names = "adc_clk", "adc_op_clk";
1225 atmel,adc-channels-used = <0x01f>;
1226 atmel,adc-startup-time = <40>;
1227 atmel,adc-use-external-triggers;
1228 atmel,adc-vref = <3000>;
1229 atmel,adc-res = <8 10>;
1230 atmel,adc-sample-hold-time = <11>;
1231 atmel,adc-res-names = "lowres", "highres";
1232 atmel,adc-ts-pressure-threshold = <10000>;
1233 status = "disabled";
1234
1235 trigger0 {
1236 trigger-name = "external-rising";
1237 trigger-value = <0x1>;
1238 trigger-external;
1239 };
1240 trigger1 {
1241 trigger-name = "external-falling";
1242 trigger-value = <0x2>;
1243 trigger-external;
1244 };
1245 trigger2 {
1246 trigger-name = "external-any";
1247 trigger-value = <0x3>;
1248 trigger-external;
1249 };
1250 trigger3 {
1251 trigger-name = "continuous";
1252 trigger-value = <0x6>;
1253 };
1254 };
1255
1256 aes@fc044000 {
1257 compatible = "atmel,at91sam9g46-aes";
1258 reg = <0xfc044000 0x100>;
1259 interrupts = <12 IRQ_TYPE_LEVEL_HIGH 0>;
1260 dmas = <&dma0 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)
1261 | AT91_XDMAC_DT_PERID(41))>,
1262 <&dma0 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)
1263 | AT91_XDMAC_DT_PERID(40))>;
1264 dma-names = "tx", "rx";
1265 clocks = <&aes_clk>;
1266 clock-names = "aes_clk";
1267 status = "okay";
1268 };
1269
1270 tdes@fc04c000 {
1271 compatible = "atmel,at91sam9g46-tdes";
1272 reg = <0xfc04c000 0x100>;
1273 interrupts = <14 IRQ_TYPE_LEVEL_HIGH 0>;
1274 dmas = <&dma0 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)
1275 | AT91_XDMAC_DT_PERID(42))>,
1276 <&dma0 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)
1277 | AT91_XDMAC_DT_PERID(43))>;
1278 dma-names = "tx", "rx";
1279 clocks = <&tdes_clk>;
1280 clock-names = "tdes_clk";
1281 status = "okay";
1282 };
1283
1284 sha@fc050000 {
1285 compatible = "atmel,at91sam9g46-sha";
1286 reg = <0xfc050000 0x100>;
1287 interrupts = <15 IRQ_TYPE_LEVEL_HIGH 0>;
1288 dmas = <&dma0 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)
1289 | AT91_XDMAC_DT_PERID(44))>;
1290 dma-names = "tx";
1291 clocks = <&sha_clk>;
1292 clock-names = "sha_clk";
1293 status = "okay";
1294 };
1295
1296 hsmc: smc@fc05c000 {
1297 compatible = "atmel,sama5d3-smc", "syscon", "simple-mfd";
1298 reg = <0xfc05c000 0x1000>;
1299 interrupts = <22 IRQ_TYPE_LEVEL_HIGH 6>;
1300 clocks = <&hsmc_clk>;
1301 #address-cells = <1>;
1302 #size-cells = <1>;
1303 ranges;
1304
1305 pmecc: ecc-engine@ffffc070 {
1306 compatible = "atmel,sama5d4-pmecc";
1307 reg = <0xfc05c070 0x490>,
1308 <0xfc05c500 0x100>;
1309 };
1310 };
1311
1312 rstc@fc068600 {
1313 compatible = "atmel,sama5d3-rstc", "atmel,at91sam9g45-rstc";
1314 reg = <0xfc068600 0x10>;
1315 clocks = <&clk32k>;
1316 };
1317
1318 shdwc@fc068610 {
1319 compatible = "atmel,at91sam9x5-shdwc";
1320 reg = <0xfc068610 0x10>;
1321 clocks = <&clk32k>;
1322 };
1323
1324 pit: timer@fc068630 {
1325 compatible = "atmel,at91sam9260-pit";
1326 reg = <0xfc068630 0x10>;
1327 interrupts = <3 IRQ_TYPE_LEVEL_HIGH 5>;
1328 clocks = <&h32ck>;
1329 };
1330
1331 watchdog@fc068640 {
1332 compatible = "atmel,sama5d4-wdt";
1333 reg = <0xfc068640 0x10>;
1334 interrupts = <4 IRQ_TYPE_LEVEL_HIGH 7>;
1335 clocks = <&clk32k>;
1336 status = "disabled";
1337 };
1338
1339 clk32k: sckc@fc068650 {
1340 compatible = "atmel,sama5d4-sckc";
1341 reg = <0xfc068650 0x4>;
1342 #clock-cells = <0>;
1343 clocks = <&slow_xtal>;
1344 };
1345
1346 rtc@fc0686b0 {
1347 compatible = "atmel,at91rm9200-rtc";
1348 reg = <0xfc0686b0 0x30>;
1349 interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
1350 clocks = <&clk32k>;
1351 };
1352
1353 dbgu: serial@fc069000 {
1354 compatible = "atmel,at91sam9260-dbgu", "atmel,at91sam9260-usart";
1355 reg = <0xfc069000 0x200>;
1356 interrupts = <45 IRQ_TYPE_LEVEL_HIGH 7>;
1357 pinctrl-names = "default";
1358 pinctrl-0 = <&pinctrl_dbgu>;
1359 clocks = <&dbgu_clk>;
1360 clock-names = "usart";
1361 status = "disabled";
1362 };
1363
1364
1365 pinctrl@fc06a000 {
1366 #address-cells = <1>;
1367 #size-cells = <1>;
1368 compatible = "atmel,at91sam9x5-pinctrl", "atmel,at91rm9200-pinctrl", "simple-bus";
1369 ranges = <0xfc068000 0xfc068000 0x100
1370 0xfc06a000 0xfc06a000 0x4000>;
1371 /* WARNING: revisit as pin spec has changed */
1372 atmel,mux-mask = <
1373 /* A B C */
1374 0xffffffff 0x3ffcfe7c 0x1c010101 /* pioA */
1375 0x7fffffff 0xfffccc3a 0x3f00cc3a /* pioB */
1376 0xffffffff 0x3ff83fff 0xff00ffff /* pioC */
1377 0x0003ff00 0x8002a800 0x00000000 /* pioD */
1378 0xffffffff 0x7fffffff 0x76fff1bf /* pioE */
1379 >;
1380
1381 pioA: gpio@fc06a000 {
1382 compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
1383 reg = <0xfc06a000 0x100>;
1384 interrupts = <23 IRQ_TYPE_LEVEL_HIGH 1>;
1385 #gpio-cells = <2>;
1386 gpio-controller;
1387 interrupt-controller;
1388 #interrupt-cells = <2>;
1389 clocks = <&pioA_clk>;
1390 };
1391
1392 pioB: gpio@fc06b000 {
1393 compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
1394 reg = <0xfc06b000 0x100>;
1395 interrupts = <24 IRQ_TYPE_LEVEL_HIGH 1>;
1396 #gpio-cells = <2>;
1397 gpio-controller;
1398 interrupt-controller;
1399 #interrupt-cells = <2>;
1400 clocks = <&pioB_clk>;
1401 };
1402
1403 pioC: gpio@fc06c000 {
1404 compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
1405 reg = <0xfc06c000 0x100>;
1406 interrupts = <25 IRQ_TYPE_LEVEL_HIGH 1>;
1407 #gpio-cells = <2>;
1408 gpio-controller;
1409 interrupt-controller;
1410 #interrupt-cells = <2>;
1411 clocks = <&pioC_clk>;
1412 };
1413
1414 pioD: gpio@fc068000 {
1415 compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
1416 reg = <0xfc068000 0x100>;
1417 interrupts = <5 IRQ_TYPE_LEVEL_HIGH 1>;
1418 #gpio-cells = <2>;
1419 gpio-controller;
1420 interrupt-controller;
1421 #interrupt-cells = <2>;
1422 clocks = <&pioD_clk>;
1423 };
1424
1425 pioE: gpio@fc06d000 {
1426 compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
1427 reg = <0xfc06d000 0x100>;
1428 interrupts = <26 IRQ_TYPE_LEVEL_HIGH 1>;
1429 #gpio-cells = <2>;
1430 gpio-controller;
1431 interrupt-controller;
1432 #interrupt-cells = <2>;
1433 clocks = <&pioE_clk>;
1434 };
1435
1436 /* pinctrl pin settings */
1437 adc0 {
1438 pinctrl_adc0_adtrg: adc0_adtrg {
1439 atmel,pins =
1440 <AT91_PIOE 31 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* conflicts with USBA_VBUS */
1441 };
1442 pinctrl_adc0_ad0: adc0_ad0 {
1443 atmel,pins =
1444 <AT91_PIOC 27 AT91_PERIPH_A AT91_PINCTRL_NONE>;
1445 };
1446 pinctrl_adc0_ad1: adc0_ad1 {
1447 atmel,pins =
1448 <AT91_PIOC 28 AT91_PERIPH_A AT91_PINCTRL_NONE>;
1449 };
1450 pinctrl_adc0_ad2: adc0_ad2 {
1451 atmel,pins =
1452 <AT91_PIOC 29 AT91_PERIPH_A AT91_PINCTRL_NONE>;
1453 };
1454 pinctrl_adc0_ad3: adc0_ad3 {
1455 atmel,pins =
1456 <AT91_PIOC 30 AT91_PERIPH_A AT91_PINCTRL_NONE>;
1457 };
1458 pinctrl_adc0_ad4: adc0_ad4 {
1459 atmel,pins =
1460 <AT91_PIOC 31 AT91_PERIPH_A AT91_PINCTRL_NONE>;
1461 };
1462 };
1463
1464 dbgu {
1465 pinctrl_dbgu: dbgu-0 {
1466 atmel,pins =
1467 <AT91_PIOB 24 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* conflicts with D14 and TDI */
1468 AT91_PIOB 25 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* conflicts with D15 and TDO */
1469 };
1470 };
1471
1472 ebi {
1473 pinctrl_ebi_addr: ebi-addr-0 {
1474 atmel,pins =
1475 <AT91_PIOE 0 AT91_PERIPH_A AT91_PINCTRL_NONE
1476 AT91_PIOE 1 AT91_PERIPH_A AT91_PINCTRL_NONE
1477 AT91_PIOE 2 AT91_PERIPH_A AT91_PINCTRL_NONE
1478 AT91_PIOE 3 AT91_PERIPH_A AT91_PINCTRL_NONE
1479 AT91_PIOE 4 AT91_PERIPH_A AT91_PINCTRL_NONE
1480 AT91_PIOE 5 AT91_PERIPH_A AT91_PINCTRL_NONE
1481 AT91_PIOE 6 AT91_PERIPH_A AT91_PINCTRL_NONE
1482 AT91_PIOE 7 AT91_PERIPH_A AT91_PINCTRL_NONE
1483 AT91_PIOE 8 AT91_PERIPH_A AT91_PINCTRL_NONE
1484 AT91_PIOE 9 AT91_PERIPH_A AT91_PINCTRL_NONE
1485 AT91_PIOE 10 AT91_PERIPH_A AT91_PINCTRL_NONE
1486 AT91_PIOE 11 AT91_PERIPH_A AT91_PINCTRL_NONE
1487 AT91_PIOE 12 AT91_PERIPH_A AT91_PINCTRL_NONE
1488 AT91_PIOE 13 AT91_PERIPH_A AT91_PINCTRL_NONE
1489 AT91_PIOE 14 AT91_PERIPH_A AT91_PINCTRL_NONE
1490 AT91_PIOE 15 AT91_PERIPH_A AT91_PINCTRL_NONE
1491 AT91_PIOE 16 AT91_PERIPH_A AT91_PINCTRL_NONE
1492 AT91_PIOE 17 AT91_PERIPH_A AT91_PINCTRL_NONE
1493 AT91_PIOE 18 AT91_PERIPH_A AT91_PINCTRL_NONE
1494 AT91_PIOE 19 AT91_PERIPH_A AT91_PINCTRL_NONE
1495 AT91_PIOE 20 AT91_PERIPH_A AT91_PINCTRL_NONE
1496 AT91_PIOC 17 AT91_PERIPH_A AT91_PINCTRL_NONE
1497 AT91_PIOC 18 AT91_PERIPH_A AT91_PINCTRL_NONE
1498 AT91_PIOE 21 AT91_PERIPH_A AT91_PINCTRL_NONE
1499 AT91_PIOE 22 AT91_PERIPH_A AT91_PINCTRL_NONE
1500 AT91_PIOE 23 AT91_PERIPH_A AT91_PINCTRL_NONE>;
1501 };
1502
1503 pinctrl_ebi_nand_addr: ebi-addr-1 {
1504 atmel,pins =
1505 <AT91_PIOC 17 AT91_PERIPH_A AT91_PINCTRL_NONE
1506 AT91_PIOC 18 AT91_PERIPH_A AT91_PINCTRL_NONE>;
1507 };
1508
1509 pinctrl_ebi_cs0: ebi-cs0-0 {
1510 atmel,pins =
1511 <AT91_PIOE 26 AT91_PERIPH_A AT91_PINCTRL_NONE>;
1512 };
1513
1514 pinctrl_ebi_cs1: ebi-cs1-0 {
1515 atmel,pins =
1516 <AT91_PIOE 27 AT91_PERIPH_A AT91_PINCTRL_NONE>;
1517 };
1518
1519 pinctrl_ebi_cs2: ebi-cs2-0 {
1520 atmel,pins =
1521 <AT91_PIOE 28 AT91_PERIPH_A AT91_PINCTRL_NONE>;
1522 };
1523
1524 pinctrl_ebi_cs3: ebi-cs3-0 {
1525 atmel,pins =
1526 <AT91_PIOC 15 AT91_PERIPH_A AT91_PINCTRL_NONE>;
1527 };
1528
1529 pinctrl_ebi_data_0_7: ebi-data-lsb-0 {
1530 atmel,pins =
1531 <AT91_PIOC 5 AT91_PERIPH_A AT91_PINCTRL_NONE
1532 AT91_PIOC 6 AT91_PERIPH_A AT91_PINCTRL_NONE
1533 AT91_PIOC 7 AT91_PERIPH_A AT91_PINCTRL_NONE
1534 AT91_PIOC 8 AT91_PERIPH_A AT91_PINCTRL_NONE
1535 AT91_PIOC 9 AT91_PERIPH_A AT91_PINCTRL_NONE
1536 AT91_PIOC 10 AT91_PERIPH_A AT91_PINCTRL_NONE
1537 AT91_PIOC 11 AT91_PERIPH_A AT91_PINCTRL_NONE
1538 AT91_PIOC 12 AT91_PERIPH_A AT91_PINCTRL_NONE>;
1539 };
1540
1541 pinctrl_ebi_data_8_15: ebi-data-msb-0 {
1542 atmel,pins =
1543 <AT91_PIOB 18 AT91_PERIPH_B AT91_PINCTRL_NONE
1544 AT91_PIOB 19 AT91_PERIPH_B AT91_PINCTRL_NONE
1545 AT91_PIOB 20 AT91_PERIPH_B AT91_PINCTRL_NONE
1546 AT91_PIOB 21 AT91_PERIPH_B AT91_PINCTRL_NONE
1547 AT91_PIOB 22 AT91_PERIPH_B AT91_PINCTRL_NONE
1548 AT91_PIOB 23 AT91_PERIPH_B AT91_PINCTRL_NONE
1549 AT91_PIOB 24 AT91_PERIPH_B AT91_PINCTRL_NONE
1550 AT91_PIOB 25 AT91_PERIPH_B AT91_PINCTRL_NONE>;
1551 };
1552
1553 pinctrl_ebi_nandrdy: ebi-nandrdy-0 {
1554 atmel,pins =
1555 <AT91_PIOC 16 AT91_PERIPH_A AT91_PINCTRL_NONE>;
1556 };
1557
1558 pinctrl_ebi_nrd_nandoe: ebi-nrd-nandoe-0 {
1559 atmel,pins =
1560 <AT91_PIOC 13 AT91_PERIPH_A AT91_PINCTRL_NONE>;
1561 };
1562
1563 pinctrl_ebi_nwait: ebi-nwait-0 {
1564 atmel,pins =
1565 <AT91_PIOE 30 AT91_PERIPH_A AT91_PINCTRL_NONE>;
1566 };
1567
1568 pinctrl_ebi_nwe_nandwe: ebi-nwe-nandwe-0 {
1569 atmel,pins =
1570 <AT91_PIOC 14 AT91_PERIPH_A AT91_PINCTRL_NONE>;
1571 };
1572
1573 pinctrl_ebi_nwr1_nbs1: ebi-nwr1-nbs1-0 {
1574 atmel,pins =
1575 <AT91_PIOE 29 AT91_PERIPH_A AT91_PINCTRL_NONE>;
1576 };
1577 };
1578
1579 i2c0 {
1580 pinctrl_i2c0: i2c0-0 {
1581 atmel,pins =
1582 <AT91_PIOA 30 AT91_PERIPH_A AT91_PINCTRL_NONE
1583 AT91_PIOA 31 AT91_PERIPH_A AT91_PINCTRL_NONE>;
1584 };
1585 };
1586
1587 i2c1 {
1588 pinctrl_i2c1: i2c1-0 {
1589 atmel,pins =
1590 <AT91_PIOE 29 AT91_PERIPH_C AT91_PINCTRL_NONE /* TWD1, conflicts with UART0 RX and DIBP */
1591 AT91_PIOE 30 AT91_PERIPH_C AT91_PINCTRL_NONE>; /* TWCK1, conflicts with UART0 TX and DIBN */
1592 };
1593 };
1594
1595 i2c2 {
1596 pinctrl_i2c2: i2c2-0 {
1597 atmel,pins =
1598 <AT91_PIOB 29 AT91_PERIPH_A AT91_PINCTRL_NONE /* TWD2, conflicts with RD0 and PWML1 */
1599 AT91_PIOB 30 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* TWCK2, conflicts with RF0 */
1600 };
1601 };
1602
1603 isi {
1604 pinctrl_isi_data_0_7: isi-0-data-0-7 {
1605 atmel,pins =
1606 <AT91_PIOC 19 AT91_PERIPH_A AT91_PINCTRL_NONE /* ISI_D0 */
1607 AT91_PIOC 20 AT91_PERIPH_A AT91_PINCTRL_NONE /* ISI_D1 */
1608 AT91_PIOC 21 AT91_PERIPH_A AT91_PINCTRL_NONE /* ISI_D2 */
1609 AT91_PIOC 22 AT91_PERIPH_A AT91_PINCTRL_NONE /* ISI_D3 */
1610 AT91_PIOC 23 AT91_PERIPH_A AT91_PINCTRL_NONE /* ISI_D4 */
1611 AT91_PIOC 24 AT91_PERIPH_A AT91_PINCTRL_NONE /* ISI_D5 */
1612 AT91_PIOC 25 AT91_PERIPH_A AT91_PINCTRL_NONE /* ISI_D6 */
1613 AT91_PIOC 26 AT91_PERIPH_A AT91_PINCTRL_NONE /* ISI_D7 */
1614 AT91_PIOB 1 AT91_PERIPH_C AT91_PINCTRL_NONE /* ISI_PCK, conflict with G0_RXCK */
1615 AT91_PIOB 3 AT91_PERIPH_C AT91_PINCTRL_NONE /* ISI_VSYNC */
1616 AT91_PIOB 4 AT91_PERIPH_C AT91_PINCTRL_NONE>; /* ISI_HSYNC */
1617 };
1618 pinctrl_isi_data_8_9: isi-0-data-8-9 {
1619 atmel,pins =
1620 <AT91_PIOC 0 AT91_PERIPH_C AT91_PINCTRL_NONE /* ISI_D8, conflicts with SPI0_MISO, PWMH2 */
1621 AT91_PIOC 1 AT91_PERIPH_C AT91_PINCTRL_NONE>; /* ISI_D9, conflicts with SPI0_MOSI, PWML2 */
1622 };
1623 pinctrl_isi_data_10_11: isi-0-data-10-11 {
1624 atmel,pins =
1625 <AT91_PIOC 2 AT91_PERIPH_C AT91_PINCTRL_NONE /* ISI_D10, conflicts with SPI0_SPCK, PWMH3 */
1626 AT91_PIOC 3 AT91_PERIPH_C AT91_PINCTRL_NONE>; /* ISI_D11, conflicts with SPI0_NPCS0, PWML3 */
1627 };
1628 };
1629
1630 lcd {
1631 pinctrl_lcd_base: lcd-base-0 {
1632 atmel,pins =
1633 <AT91_PIOA 26 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDVSYNC */
1634 AT91_PIOA 27 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDHSYNC */
1635 AT91_PIOA 29 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDDEN */
1636 AT91_PIOA 28 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* LCDPCK */
1637 };
1638 pinctrl_lcd_pwm: lcd-pwm-0 {
1639 atmel,pins = <AT91_PIOA 24 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* LCDPWM */
1640 };
1641 pinctrl_lcd_rgb444: lcd-rgb-0 {
1642 atmel,pins =
1643 <AT91_PIOA 0 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD0 pin */
1644 AT91_PIOA 1 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD1 pin */
1645 AT91_PIOA 2 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD2 pin */
1646 AT91_PIOA 3 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD3 pin */
1647 AT91_PIOA 4 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD4 pin */
1648 AT91_PIOA 5 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD5 pin */
1649 AT91_PIOA 6 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD6 pin */
1650 AT91_PIOA 7 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD7 pin */
1651 AT91_PIOA 8 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD8 pin */
1652 AT91_PIOA 9 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD9 pin */
1653 AT91_PIOA 10 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD10 pin */
1654 AT91_PIOA 11 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* LCDD11 pin */
1655 };
1656 pinctrl_lcd_rgb565: lcd-rgb-1 {
1657 atmel,pins =
1658 <AT91_PIOA 0 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD0 pin */
1659 AT91_PIOA 1 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD1 pin */
1660 AT91_PIOA 2 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD2 pin */
1661 AT91_PIOA 3 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD3 pin */
1662 AT91_PIOA 4 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD4 pin */
1663 AT91_PIOA 5 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD5 pin */
1664 AT91_PIOA 6 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD6 pin */
1665 AT91_PIOA 7 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD7 pin */
1666 AT91_PIOA 8 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD8 pin */
1667 AT91_PIOA 9 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD9 pin */
1668 AT91_PIOA 10 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD10 pin */
1669 AT91_PIOA 11 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD11 pin */
1670 AT91_PIOA 12 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD12 pin */
1671 AT91_PIOA 13 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD13 pin */
1672 AT91_PIOA 14 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD14 pin */
1673 AT91_PIOA 15 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* LCDD15 pin */
1674 };
1675 pinctrl_lcd_rgb666: lcd-rgb-2 {
1676 atmel,pins =
1677 <AT91_PIOA 2 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD2 pin */
1678 AT91_PIOA 3 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD3 pin */
1679 AT91_PIOA 4 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD4 pin */
1680 AT91_PIOA 5 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD5 pin */
1681 AT91_PIOA 6 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD6 pin */
1682 AT91_PIOA 7 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD7 pin */
1683 AT91_PIOA 10 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD10 pin */
1684 AT91_PIOA 11 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD11 pin */
1685 AT91_PIOA 12 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD12 pin */
1686 AT91_PIOA 13 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD13 pin */
1687 AT91_PIOA 14 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD14 pin */
1688 AT91_PIOA 15 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD15 pin */
1689 AT91_PIOA 18 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD18 pin */
1690 AT91_PIOA 19 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD19 pin */
1691 AT91_PIOA 20 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD20 pin */
1692 AT91_PIOA 21 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD21 pin */
1693 AT91_PIOA 22 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD22 pin */
1694 AT91_PIOA 23 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* LCDD23 pin */
1695 };
1696 pinctrl_lcd_rgb777: lcd-rgb-3 {
1697 atmel,pins =
1698 /* LCDDAT0 conflicts with TMS */
1699 <AT91_PIOA 1 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD1 pin */
1700 AT91_PIOA 2 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD2 pin */
1701 AT91_PIOA 3 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD3 pin */
1702 AT91_PIOA 4 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD4 pin */
1703 AT91_PIOA 5 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD5 pin */
1704 AT91_PIOA 6 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD6 pin */
1705 AT91_PIOA 7 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD7 pin */
1706 /* LCDDAT8 conflicts with TCK */
1707 AT91_PIOA 9 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD9 pin */
1708 AT91_PIOA 10 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD10 pin */
1709 AT91_PIOA 11 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD11 pin */
1710 AT91_PIOA 12 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD12 pin */
1711 AT91_PIOA 13 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD13 pin */
1712 AT91_PIOA 14 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD14 pin */
1713 AT91_PIOA 15 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD15 pin */
1714 /* LCDDAT16 conflicts with NTRST */
1715 AT91_PIOA 17 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD17 pin */
1716 AT91_PIOA 18 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD18 pin */
1717 AT91_PIOA 19 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD19 pin */
1718 AT91_PIOA 20 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD20 pin */
1719 AT91_PIOA 21 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD21 pin */
1720 AT91_PIOA 22 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD22 pin */
1721 AT91_PIOA 23 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* LCDD23 pin */
1722 };
1723 pinctrl_lcd_rgb888: lcd-rgb-4 {
1724 atmel,pins =
1725 <AT91_PIOA 0 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD0 pin */
1726 AT91_PIOA 1 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD1 pin */
1727 AT91_PIOA 2 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD2 pin */
1728 AT91_PIOA 3 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD3 pin */
1729 AT91_PIOA 4 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD4 pin */
1730 AT91_PIOA 5 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD5 pin */
1731 AT91_PIOA 6 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD6 pin */
1732 AT91_PIOA 7 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD7 pin */
1733 AT91_PIOA 8 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD8 pin */
1734 AT91_PIOA 9 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD9 pin */
1735 AT91_PIOA 10 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD10 pin */
1736 AT91_PIOA 11 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD11 pin */
1737 AT91_PIOA 12 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD12 pin */
1738 AT91_PIOA 13 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD13 pin */
1739 AT91_PIOA 14 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD14 pin */
1740 AT91_PIOA 15 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD15 pin */
1741 AT91_PIOA 16 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD16 pin */
1742 AT91_PIOA 17 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD17 pin */
1743 AT91_PIOA 18 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD18 pin */
1744 AT91_PIOA 19 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD19 pin */
1745 AT91_PIOA 20 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD20 pin */
1746 AT91_PIOA 21 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD21 pin */
1747 AT91_PIOA 22 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD22 pin */
1748 AT91_PIOA 23 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* LCDD23 pin */
1749 };
1750 };
1751
1752 macb0 {
1753 pinctrl_macb0_rmii: macb0_rmii-0 {
1754 atmel,pins =
1755 <AT91_PIOB 12 AT91_PERIPH_A AT91_PINCTRL_NONE /* G0_TX0 */
1756 AT91_PIOB 13 AT91_PERIPH_A AT91_PINCTRL_NONE /* G0_TX1 */
1757 AT91_PIOB 8 AT91_PERIPH_A AT91_PINCTRL_NONE /* G0_RX0 */
1758 AT91_PIOB 9 AT91_PERIPH_A AT91_PINCTRL_NONE /* G0_RX1 */
1759 AT91_PIOB 6 AT91_PERIPH_A AT91_PINCTRL_NONE /* G0_RXDV */
1760 AT91_PIOB 7 AT91_PERIPH_A AT91_PINCTRL_NONE /* G0_RXER */
1761 AT91_PIOB 2 AT91_PERIPH_A AT91_PINCTRL_NONE /* G0_TXEN */
1762 AT91_PIOB 0 AT91_PERIPH_A AT91_PINCTRL_NONE /* G0_TXCK */
1763 AT91_PIOB 16 AT91_PERIPH_A AT91_PINCTRL_NONE /* G0_MDC */
1764 AT91_PIOB 17 AT91_PERIPH_A AT91_PINCTRL_NONE /* G0_MDIO */
1765 >;
1766 };
1767 };
1768
1769 macb1 {
1770 pinctrl_macb1_rmii: macb1_rmii-0 {
1771 atmel,pins =
1772 <AT91_PIOA 14 AT91_PERIPH_B AT91_PINCTRL_NONE /* G1_TX0 */
1773 AT91_PIOA 15 AT91_PERIPH_B AT91_PINCTRL_NONE /* G1_TX1 */
1774 AT91_PIOA 12 AT91_PERIPH_B AT91_PINCTRL_NONE /* G1_RX0 */
1775 AT91_PIOA 13 AT91_PERIPH_B AT91_PINCTRL_NONE /* G1_RX1 */
1776 AT91_PIOA 10 AT91_PERIPH_B AT91_PINCTRL_NONE /* G1_RXDV */
1777 AT91_PIOA 11 AT91_PERIPH_B AT91_PINCTRL_NONE /* G1_RXER */
1778 AT91_PIOA 4 AT91_PERIPH_B AT91_PINCTRL_NONE /* G1_TXEN */
1779 AT91_PIOA 2 AT91_PERIPH_B AT91_PINCTRL_NONE /* G1_TXCK */
1780 AT91_PIOA 22 AT91_PERIPH_B AT91_PINCTRL_NONE /* G1_MDC */
1781 AT91_PIOA 23 AT91_PERIPH_B AT91_PINCTRL_NONE /* G1_MDIO */
1782 >;
1783 };
1784 };
1785
1786 mmc0 {
1787 pinctrl_mmc0_clk_cmd_dat0: mmc0_clk_cmd_dat0 {
1788 atmel,pins =
1789 <AT91_PIOC 4 AT91_PERIPH_B AT91_PINCTRL_NONE /* MCI0_CK, conflict with PCK1(ISI_MCK) */
1790 AT91_PIOC 5 AT91_PERIPH_B AT91_PINCTRL_PULL_UP /* MCI0_CDA, conflict with NAND_D0 */
1791 AT91_PIOC 6 AT91_PERIPH_B AT91_PINCTRL_PULL_UP /* MCI0_DA0, conflict with NAND_D1 */
1792 >;
1793 };
1794 pinctrl_mmc0_dat1_3: mmc0_dat1_3 {
1795 atmel,pins =
1796 <AT91_PIOC 7 AT91_PERIPH_B AT91_PINCTRL_PULL_UP /* MCI0_DA1, conflict with NAND_D2 */
1797 AT91_PIOC 8 AT91_PERIPH_B AT91_PINCTRL_PULL_UP /* MCI0_DA2, conflict with NAND_D3 */
1798 AT91_PIOC 9 AT91_PERIPH_B AT91_PINCTRL_PULL_UP /* MCI0_DA3, conflict with NAND_D4 */
1799 >;
1800 };
1801 pinctrl_mmc0_dat4_7: mmc0_dat4_7 {
1802 atmel,pins =
1803 <AT91_PIOC 10 AT91_PERIPH_B AT91_PINCTRL_PULL_UP /* MCI0_DA4, conflict with NAND_D5 */
1804 AT91_PIOC 11 AT91_PERIPH_B AT91_PINCTRL_PULL_UP /* MCI0_DA5, conflict with NAND_D6 */
1805 AT91_PIOC 12 AT91_PERIPH_B AT91_PINCTRL_PULL_UP /* MCI0_DA6, conflict with NAND_D7 */
1806 AT91_PIOC 13 AT91_PERIPH_B AT91_PINCTRL_PULL_UP /* MCI0_DA7, conflict with NAND_OE */
1807 >;
1808 };
1809 };
1810
1811 mmc1 {
1812 pinctrl_mmc1_clk_cmd_dat0: mmc1_clk_cmd_dat0 {
1813 atmel,pins =
1814 <AT91_PIOE 18 AT91_PERIPH_C AT91_PINCTRL_NONE /* MCI1_CK */
1815 AT91_PIOE 19 AT91_PERIPH_C AT91_PINCTRL_PULL_UP /* MCI1_CDA */
1816 AT91_PIOE 20 AT91_PERIPH_C AT91_PINCTRL_PULL_UP /* MCI1_DA0 */
1817 >;
1818 };
1819 pinctrl_mmc1_dat1_3: mmc1_dat1_3 {
1820 atmel,pins =
1821 <AT91_PIOE 21 AT91_PERIPH_C AT91_PINCTRL_PULL_UP /* MCI1_DA1 */
1822 AT91_PIOE 22 AT91_PERIPH_C AT91_PINCTRL_PULL_UP /* MCI1_DA2 */
1823 AT91_PIOE 23 AT91_PERIPH_C AT91_PINCTRL_PULL_UP /* MCI1_DA3 */
1824 >;
1825 };
1826 };
1827
1828 nand0 {
1829 pinctrl_nand: nand-0 {
1830 atmel,pins =
1831 <AT91_PIOC 13 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC13 periph A Read Enable */
1832 AT91_PIOC 14 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC14 periph A Write Enable */
1833
1834 AT91_PIOC 17 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PC17 ALE */
1835 AT91_PIOC 18 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PC18 CLE */
1836
1837 AT91_PIOC 15 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PC15 NCS3/Chip Enable */
1838 AT91_PIOC 16 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PC16 NANDRDY */
1839 AT91_PIOC 5 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC5 Data bit 0 */
1840 AT91_PIOC 6 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC6 Data bit 1 */
1841 AT91_PIOC 7 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC7 Data bit 2 */
1842 AT91_PIOC 8 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC8 Data bit 3 */
1843 AT91_PIOC 9 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC9 Data bit 4 */
1844 AT91_PIOC 10 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC10 Data bit 5 */
1845 AT91_PIOC 11 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC11 periph A Data bit 6 */
1846 AT91_PIOC 12 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PC12 periph A Data bit 7 */
1847 };
1848 };
1849
1850 spi0 {
1851 pinctrl_spi0: spi0-0 {
1852 atmel,pins =
1853 <AT91_PIOC 0 AT91_PERIPH_A AT91_PINCTRL_NONE /* SPI0_MISO */
1854 AT91_PIOC 1 AT91_PERIPH_A AT91_PINCTRL_NONE /* SPI0_MOSI */
1855 AT91_PIOC 2 AT91_PERIPH_A AT91_PINCTRL_NONE /* SPI0_SPCK */
1856 >;
1857 };
1858 };
1859
1860 ssc0 {
1861 pinctrl_ssc0_tx: ssc0_tx {
1862 atmel,pins =
1863 <AT91_PIOB 27 AT91_PERIPH_B AT91_PINCTRL_NONE /* TK0 */
1864 AT91_PIOB 31 AT91_PERIPH_B AT91_PINCTRL_NONE /* TF0 */
1865 AT91_PIOB 28 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* TD0 */
1866 };
1867
1868 pinctrl_ssc0_rx: ssc0_rx {
1869 atmel,pins =
1870 <AT91_PIOB 26 AT91_PERIPH_B AT91_PINCTRL_NONE /* RK0 */
1871 AT91_PIOB 30 AT91_PERIPH_B AT91_PINCTRL_NONE /* RF0 */
1872 AT91_PIOB 29 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* RD0 */
1873 };
1874 };
1875
1876 ssc1 {
1877 pinctrl_ssc1_tx: ssc1_tx {
1878 atmel,pins =
1879 <AT91_PIOC 19 AT91_PERIPH_B AT91_PINCTRL_NONE /* TK1 */
1880 AT91_PIOC 20 AT91_PERIPH_B AT91_PINCTRL_NONE /* TF1 */
1881 AT91_PIOC 21 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* TD1 */
1882 };
1883
1884 pinctrl_ssc1_rx: ssc1_rx {
1885 atmel,pins =
1886 <AT91_PIOC 24 AT91_PERIPH_B AT91_PINCTRL_NONE /* RK1 */
1887 AT91_PIOC 22 AT91_PERIPH_B AT91_PINCTRL_NONE /* RF1 */
1888 AT91_PIOC 23 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* RD1 */
1889 };
1890 };
1891
1892 spi1 {
1893 pinctrl_spi1: spi1-0 {
1894 atmel,pins =
1895 <AT91_PIOB 18 AT91_PERIPH_A AT91_PINCTRL_NONE /* SPI1_MISO */
1896 AT91_PIOB 19 AT91_PERIPH_A AT91_PINCTRL_NONE /* SPI1_MOSI */
1897 AT91_PIOB 20 AT91_PERIPH_A AT91_PINCTRL_NONE /* SPI1_SPCK */
1898 >;
1899 };
1900 };
1901
1902 spi2 {
1903 pinctrl_spi2: spi2-0 {
1904 atmel,pins =
1905 <AT91_PIOD 11 AT91_PERIPH_B AT91_PINCTRL_NONE /* SPI2_MISO conflicts with RTS0 */
1906 AT91_PIOD 13 AT91_PERIPH_B AT91_PINCTRL_NONE /* SPI2_MOSI conflicts with TXD0 */
1907 AT91_PIOD 15 AT91_PERIPH_B AT91_PINCTRL_NONE /* SPI2_SPCK conflicts with RTS1 */
1908 >;
1909 };
1910 };
1911
1912 uart0 {
1913 pinctrl_uart0: uart0-0 {
1914 atmel,pins =
1915 <AT91_PIOE 29 AT91_PERIPH_B AT91_PINCTRL_NONE /* RXD */
1916 AT91_PIOE 30 AT91_PERIPH_B AT91_PINCTRL_PULL_UP /* TXD */
1917 >;
1918 };
1919 };
1920
1921 uart1 {
1922 pinctrl_uart1: uart1-0 {
1923 atmel,pins =
1924 <AT91_PIOC 25 AT91_PERIPH_C AT91_PINCTRL_NONE /* RXD */
1925 AT91_PIOC 26 AT91_PERIPH_C AT91_PINCTRL_PULL_UP /* TXD */
1926 >;
1927 };
1928 };
1929
1930 usart0 {
1931 pinctrl_usart0: usart0-0 {
1932 atmel,pins =
1933 <AT91_PIOD 12 AT91_PERIPH_A AT91_PINCTRL_NONE /* RXD */
1934 AT91_PIOD 13 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* TXD */
1935 >;
1936 };
1937 pinctrl_usart0_rts: usart0_rts-0 {
1938 atmel,pins = <AT91_PIOD 11 AT91_PERIPH_A AT91_PINCTRL_NONE>;
1939 };
1940 pinctrl_usart0_cts: usart0_cts-0 {
1941 atmel,pins = <AT91_PIOD 10 AT91_PERIPH_A AT91_PINCTRL_NONE>;
1942 };
1943 };
1944
1945 usart1 {
1946 pinctrl_usart1: usart1-0 {
1947 atmel,pins =
1948 <AT91_PIOD 16 AT91_PERIPH_A AT91_PINCTRL_NONE /* RXD */
1949 AT91_PIOD 17 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* TXD */
1950 >;
1951 };
1952 pinctrl_usart1_rts: usart1_rts-0 {
1953 atmel,pins = <AT91_PIOD 15 AT91_PERIPH_A AT91_PINCTRL_NONE>;
1954 };
1955 pinctrl_usart1_cts: usart1_cts-0 {
1956 atmel,pins = <AT91_PIOD 14 AT91_PERIPH_A AT91_PINCTRL_NONE>;
1957 };
1958 };
1959
1960 usart2 {
1961 pinctrl_usart2: usart2-0 {
1962 atmel,pins =
1963 <AT91_PIOB 4 AT91_PERIPH_B AT91_PINCTRL_NONE /* RXD - conflicts with G0_CRS, ISI_HSYNC */
1964 AT91_PIOB 5 AT91_PERIPH_B AT91_PINCTRL_PULL_UP /* TXD - conflicts with G0_COL, PCK2 */
1965 >;
1966 };
1967 pinctrl_usart2_rts: usart2_rts-0 {
1968 atmel,pins = <AT91_PIOB 11 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* conflicts with G0_RX3, PWMH1 */
1969 };
1970 pinctrl_usart2_cts: usart2_cts-0 {
1971 atmel,pins = <AT91_PIOB 3 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* conflicts with G0_TXER, ISI_VSYNC */
1972 };
1973 };
1974
1975 usart3 {
1976 pinctrl_usart3: usart3-0 {
1977 atmel,pins =
1978 <AT91_PIOE 16 AT91_PERIPH_B AT91_PINCTRL_NONE /* RXD */
1979 AT91_PIOE 17 AT91_PERIPH_B AT91_PINCTRL_PULL_UP /* TXD */
1980 >;
1981 };
1982 };
1983
1984 usart4 {
1985 pinctrl_usart4: usart4-0 {
1986 atmel,pins =
1987 <AT91_PIOE 26 AT91_PERIPH_B AT91_PINCTRL_NONE /* RXD */
1988 AT91_PIOE 27 AT91_PERIPH_B AT91_PINCTRL_PULL_UP /* TXD */
1989 >;
1990 };
1991 pinctrl_usart4_rts: usart4_rts-0 {
1992 atmel,pins = <AT91_PIOE 28 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* conflicts with NWAIT, A19 */
1993 };
1994 pinctrl_usart4_cts: usart4_cts-0 {
1995 atmel,pins = <AT91_PIOE 0 AT91_PERIPH_C AT91_PINCTRL_NONE>; /* conflicts with A0/NBS0, MCI0_CDB */
1996 };
1997 };
1998 };
1999
2000 aic: interrupt-controller@fc06e000 {
2001 #interrupt-cells = <3>;
2002 compatible = "atmel,sama5d4-aic";
2003 interrupt-controller;
2004 reg = <0xfc06e000 0x200>;
2005 atmel,external-irqs = <56>;
2006 };
2007 };
2008 };
2009};