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1* Qualcomm Atheros ath10k wireless devices
2
3Required properties:
4- compatible: Should be one of the following:
5 * "qcom,ath10k"
6 * "qcom,ipq4019-wifi"
7
8PCI based devices uses compatible string "qcom,ath10k" and takes calibration
9data along with board specific data via "qcom,ath10k-calibration-data".
10Rest of the properties are not applicable for PCI based devices.
11
12AHB based devices (i.e. ipq4019) uses compatible string "qcom,ipq4019-wifi"
13and also uses most of the properties defined in this doc (except
14"qcom,ath10k-calibration-data"). It uses "qcom,ath10k-pre-calibration-data"
15to carry pre calibration data.
16
17In general, entry "qcom,ath10k-pre-calibration-data" and
18"qcom,ath10k-calibration-data" conflict with each other and only one
19can be provided per device.
20
21Optional properties:
22- reg: Address and length of the register set for the device.
23- resets: Must contain an entry for each entry in reset-names.
24 See ../reset/reseti.txt for details.
25- reset-names: Must include the list of following reset names,
26 "wifi_cpu_init"
27 "wifi_radio_srif"
28 "wifi_radio_warm"
29 "wifi_radio_cold"
30 "wifi_core_warm"
31 "wifi_core_cold"
32- clocks: List of clock specifiers, must contain an entry for each required
33 entry in clock-names.
34- clock-names: Should contain the clock names "wifi_wcss_cmd", "wifi_wcss_ref",
35 "wifi_wcss_rtc".
36- interrupts: List of interrupt lines. Must contain an entry
37 for each entry in the interrupt-names property.
38- interrupt-names: Must include the entries for MSI interrupt
39 names ("msi0" to "msi15") and legacy interrupt
40 name ("legacy"),
41- qcom,msi_addr: MSI interrupt address.
42- qcom,msi_base: Base value to add before writing MSI data into
43 MSI address register.
44- qcom,ath10k-calibration-data : calibration data + board specific data
45 as an array, the length can vary between
46 hw versions.
47- qcom,ath10k-pre-calibration-data : pre calibration data as an array,
48 the length can vary between hw versions.
49
50Example (to supply the calibration data alone):
51
52In this example, the node is defined as child node of the PCI controller.
53
54pci {
55 pcie@0 {
56 reg = <0 0 0 0 0>;
57 #interrupt-cells = <1>;
58 #size-cells = <2>;
59 #address-cells = <3>;
60 device_type = "pci";
61
62 ath10k@0,0 {
63 reg = <0 0 0 0 0>;
64 device_type = "pci";
65 qcom,ath10k-calibration-data = [ 01 02 03 ... ];
66 };
67 };
68};
69
70Example (to supply ipq4019 SoC wifi block details):
71
72wifi0: wifi@a000000 {
73 compatible = "qcom,ipq4019-wifi";
74 reg = <0xa000000 0x200000>;
75 resets = <&gcc WIFI0_CPU_INIT_RESET>,
76 <&gcc WIFI0_RADIO_SRIF_RESET>,
77 <&gcc WIFI0_RADIO_WARM_RESET>,
78 <&gcc WIFI0_RADIO_COLD_RESET>,
79 <&gcc WIFI0_CORE_WARM_RESET>,
80 <&gcc WIFI0_CORE_COLD_RESET>;
81 reset-names = "wifi_cpu_init",
82 "wifi_radio_srif",
83 "wifi_radio_warm",
84 "wifi_radio_cold",
85 "wifi_core_warm",
86 "wifi_core_cold";
87 clocks = <&gcc GCC_WCSS2G_CLK>,
88 <&gcc GCC_WCSS2G_REF_CLK>,
89 <&gcc GCC_WCSS2G_RTC_CLK>;
90 clock-names = "wifi_wcss_cmd",
91 "wifi_wcss_ref",
92 "wifi_wcss_rtc";
93 interrupts = <0 0x20 0x1>,
94 <0 0x21 0x1>,
95 <0 0x22 0x1>,
96 <0 0x23 0x1>,
97 <0 0x24 0x1>,
98 <0 0x25 0x1>,
99 <0 0x26 0x1>,
100 <0 0x27 0x1>,
101 <0 0x28 0x1>,
102 <0 0x29 0x1>,
103 <0 0x2a 0x1>,
104 <0 0x2b 0x1>,
105 <0 0x2c 0x1>,
106 <0 0x2d 0x1>,
107 <0 0x2e 0x1>,
108 <0 0x2f 0x1>,
109 <0 0xa8 0x0>;
110 interrupt-names = "msi0", "msi1", "msi2", "msi3",
111 "msi4", "msi5", "msi6", "msi7",
112 "msi8", "msi9", "msi10", "msi11",
113 "msi12", "msi13", "msi14", "msi15",
114 "legacy";
115 qcom,msi_addr = <0x0b006040>;
116 qcom,msi_base = <0x40>;
117 qcom,ath10k-pre-calibration-data = [ 01 02 03 ... ];
118};