Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
tjh.dev
kernel
os
linux
1/*
2 * Microsemi Switchtec PCIe Driver
3 * Copyright (c) 2017, Microsemi Corporation
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms and conditions of the GNU General Public License,
7 * version 2, as published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 */
15
16#ifndef _SWITCHTEC_H
17#define _SWITCHTEC_H
18
19#include <linux/pci.h>
20#include <linux/cdev.h>
21
22#define MICROSEMI_VENDOR_ID 0x11f8
23#define MICROSEMI_NTB_CLASSCODE 0x068000
24#define MICROSEMI_MGMT_CLASSCODE 0x058000
25
26#define SWITCHTEC_MRPC_PAYLOAD_SIZE 1024
27#define SWITCHTEC_MAX_PFF_CSR 48
28
29#define SWITCHTEC_EVENT_OCCURRED BIT(0)
30#define SWITCHTEC_EVENT_CLEAR BIT(0)
31#define SWITCHTEC_EVENT_EN_LOG BIT(1)
32#define SWITCHTEC_EVENT_EN_CLI BIT(2)
33#define SWITCHTEC_EVENT_EN_IRQ BIT(3)
34#define SWITCHTEC_EVENT_FATAL BIT(4)
35
36enum {
37 SWITCHTEC_GAS_MRPC_OFFSET = 0x0000,
38 SWITCHTEC_GAS_TOP_CFG_OFFSET = 0x1000,
39 SWITCHTEC_GAS_SW_EVENT_OFFSET = 0x1800,
40 SWITCHTEC_GAS_SYS_INFO_OFFSET = 0x2000,
41 SWITCHTEC_GAS_FLASH_INFO_OFFSET = 0x2200,
42 SWITCHTEC_GAS_PART_CFG_OFFSET = 0x4000,
43 SWITCHTEC_GAS_NTB_OFFSET = 0x10000,
44 SWITCHTEC_GAS_PFF_CSR_OFFSET = 0x134000,
45};
46
47struct mrpc_regs {
48 u8 input_data[SWITCHTEC_MRPC_PAYLOAD_SIZE];
49 u8 output_data[SWITCHTEC_MRPC_PAYLOAD_SIZE];
50 u32 cmd;
51 u32 status;
52 u32 ret_value;
53} __packed;
54
55enum mrpc_status {
56 SWITCHTEC_MRPC_STATUS_INPROGRESS = 1,
57 SWITCHTEC_MRPC_STATUS_DONE = 2,
58 SWITCHTEC_MRPC_STATUS_ERROR = 0xFF,
59 SWITCHTEC_MRPC_STATUS_INTERRUPTED = 0x100,
60};
61
62struct sw_event_regs {
63 u64 event_report_ctrl;
64 u64 reserved1;
65 u64 part_event_bitmap;
66 u64 reserved2;
67 u32 global_summary;
68 u32 reserved3[3];
69 u32 stack_error_event_hdr;
70 u32 stack_error_event_data;
71 u32 reserved4[4];
72 u32 ppu_error_event_hdr;
73 u32 ppu_error_event_data;
74 u32 reserved5[4];
75 u32 isp_error_event_hdr;
76 u32 isp_error_event_data;
77 u32 reserved6[4];
78 u32 sys_reset_event_hdr;
79 u32 reserved7[5];
80 u32 fw_exception_hdr;
81 u32 reserved8[5];
82 u32 fw_nmi_hdr;
83 u32 reserved9[5];
84 u32 fw_non_fatal_hdr;
85 u32 reserved10[5];
86 u32 fw_fatal_hdr;
87 u32 reserved11[5];
88 u32 twi_mrpc_comp_hdr;
89 u32 twi_mrpc_comp_data;
90 u32 reserved12[4];
91 u32 twi_mrpc_comp_async_hdr;
92 u32 twi_mrpc_comp_async_data;
93 u32 reserved13[4];
94 u32 cli_mrpc_comp_hdr;
95 u32 cli_mrpc_comp_data;
96 u32 reserved14[4];
97 u32 cli_mrpc_comp_async_hdr;
98 u32 cli_mrpc_comp_async_data;
99 u32 reserved15[4];
100 u32 gpio_interrupt_hdr;
101 u32 gpio_interrupt_data;
102 u32 reserved16[4];
103} __packed;
104
105enum {
106 SWITCHTEC_CFG0_RUNNING = 0x04,
107 SWITCHTEC_CFG1_RUNNING = 0x05,
108 SWITCHTEC_IMG0_RUNNING = 0x03,
109 SWITCHTEC_IMG1_RUNNING = 0x07,
110};
111
112struct sys_info_regs {
113 u32 device_id;
114 u32 device_version;
115 u32 firmware_version;
116 u32 reserved1;
117 u32 vendor_table_revision;
118 u32 table_format_version;
119 u32 partition_id;
120 u32 cfg_file_fmt_version;
121 u16 cfg_running;
122 u16 img_running;
123 u32 reserved2[57];
124 char vendor_id[8];
125 char product_id[16];
126 char product_revision[4];
127 char component_vendor[8];
128 u16 component_id;
129 u8 component_revision;
130} __packed;
131
132struct flash_info_regs {
133 u32 flash_part_map_upd_idx;
134
135 struct active_partition_info {
136 u32 address;
137 u32 build_version;
138 u32 build_string;
139 } active_img;
140
141 struct active_partition_info active_cfg;
142 struct active_partition_info inactive_img;
143 struct active_partition_info inactive_cfg;
144
145 u32 flash_length;
146
147 struct partition_info {
148 u32 address;
149 u32 length;
150 } cfg0;
151
152 struct partition_info cfg1;
153 struct partition_info img0;
154 struct partition_info img1;
155 struct partition_info nvlog;
156 struct partition_info vendor[8];
157};
158
159enum {
160 SWITCHTEC_NTB_REG_INFO_OFFSET = 0x0000,
161 SWITCHTEC_NTB_REG_CTRL_OFFSET = 0x4000,
162 SWITCHTEC_NTB_REG_DBMSG_OFFSET = 0x64000,
163};
164
165struct ntb_info_regs {
166 u8 partition_count;
167 u8 partition_id;
168 u16 reserved1;
169 u64 ep_map;
170 u16 requester_id;
171} __packed;
172
173struct part_cfg_regs {
174 u32 status;
175 u32 state;
176 u32 port_cnt;
177 u32 usp_port_mode;
178 u32 usp_pff_inst_id;
179 u32 vep_pff_inst_id;
180 u32 dsp_pff_inst_id[47];
181 u32 reserved1[11];
182 u16 vep_vector_number;
183 u16 usp_vector_number;
184 u32 port_event_bitmap;
185 u32 reserved2[3];
186 u32 part_event_summary;
187 u32 reserved3[3];
188 u32 part_reset_hdr;
189 u32 part_reset_data[5];
190 u32 mrpc_comp_hdr;
191 u32 mrpc_comp_data[5];
192 u32 mrpc_comp_async_hdr;
193 u32 mrpc_comp_async_data[5];
194 u32 dyn_binding_hdr;
195 u32 dyn_binding_data[5];
196 u32 reserved4[159];
197} __packed;
198
199enum {
200 NTB_CTRL_PART_OP_LOCK = 0x1,
201 NTB_CTRL_PART_OP_CFG = 0x2,
202 NTB_CTRL_PART_OP_RESET = 0x3,
203
204 NTB_CTRL_PART_STATUS_NORMAL = 0x1,
205 NTB_CTRL_PART_STATUS_LOCKED = 0x2,
206 NTB_CTRL_PART_STATUS_LOCKING = 0x3,
207 NTB_CTRL_PART_STATUS_CONFIGURING = 0x4,
208 NTB_CTRL_PART_STATUS_RESETTING = 0x5,
209
210 NTB_CTRL_BAR_VALID = 1 << 0,
211 NTB_CTRL_BAR_DIR_WIN_EN = 1 << 4,
212 NTB_CTRL_BAR_LUT_WIN_EN = 1 << 5,
213
214 NTB_CTRL_REQ_ID_EN = 1 << 0,
215
216 NTB_CTRL_LUT_EN = 1 << 0,
217
218 NTB_PART_CTRL_ID_PROT_DIS = 1 << 0,
219};
220
221struct ntb_ctrl_regs {
222 u32 partition_status;
223 u32 partition_op;
224 u32 partition_ctrl;
225 u32 bar_setup;
226 u32 bar_error;
227 u16 lut_table_entries;
228 u16 lut_table_offset;
229 u32 lut_error;
230 u16 req_id_table_size;
231 u16 req_id_table_offset;
232 u32 req_id_error;
233 u32 reserved1[7];
234 struct {
235 u32 ctl;
236 u32 win_size;
237 u64 xlate_addr;
238 } bar_entry[6];
239 u32 reserved2[216];
240 u32 req_id_table[256];
241 u32 reserved3[512];
242 u64 lut_entry[512];
243} __packed;
244
245#define NTB_DBMSG_IMSG_STATUS BIT_ULL(32)
246#define NTB_DBMSG_IMSG_MASK BIT_ULL(40)
247
248struct ntb_dbmsg_regs {
249 u32 reserved1[1024];
250 u64 odb;
251 u64 odb_mask;
252 u64 idb;
253 u64 idb_mask;
254 u8 idb_vec_map[64];
255 u32 msg_map;
256 u32 reserved2;
257 struct {
258 u32 msg;
259 u32 status;
260 } omsg[4];
261
262 struct {
263 u32 msg;
264 u8 status;
265 u8 mask;
266 u8 src;
267 u8 reserved;
268 } imsg[4];
269
270 u8 reserved3[3928];
271 u8 msix_table[1024];
272 u8 reserved4[3072];
273 u8 pba[24];
274 u8 reserved5[4072];
275} __packed;
276
277enum {
278 SWITCHTEC_PART_CFG_EVENT_RESET = 1 << 0,
279 SWITCHTEC_PART_CFG_EVENT_MRPC_CMP = 1 << 1,
280 SWITCHTEC_PART_CFG_EVENT_MRPC_ASYNC_CMP = 1 << 2,
281 SWITCHTEC_PART_CFG_EVENT_DYN_PART_CMP = 1 << 3,
282};
283
284struct pff_csr_regs {
285 u16 vendor_id;
286 u16 device_id;
287 u32 pci_cfg_header[15];
288 u32 pci_cap_region[48];
289 u32 pcie_cap_region[448];
290 u32 indirect_gas_window[128];
291 u32 indirect_gas_window_off;
292 u32 reserved[127];
293 u32 pff_event_summary;
294 u32 reserved2[3];
295 u32 aer_in_p2p_hdr;
296 u32 aer_in_p2p_data[5];
297 u32 aer_in_vep_hdr;
298 u32 aer_in_vep_data[5];
299 u32 dpc_hdr;
300 u32 dpc_data[5];
301 u32 cts_hdr;
302 u32 cts_data[5];
303 u32 reserved3[6];
304 u32 hotplug_hdr;
305 u32 hotplug_data[5];
306 u32 ier_hdr;
307 u32 ier_data[5];
308 u32 threshold_hdr;
309 u32 threshold_data[5];
310 u32 power_mgmt_hdr;
311 u32 power_mgmt_data[5];
312 u32 tlp_throttling_hdr;
313 u32 tlp_throttling_data[5];
314 u32 force_speed_hdr;
315 u32 force_speed_data[5];
316 u32 credit_timeout_hdr;
317 u32 credit_timeout_data[5];
318 u32 link_state_hdr;
319 u32 link_state_data[5];
320 u32 reserved4[174];
321} __packed;
322
323struct switchtec_ntb;
324
325struct switchtec_dev {
326 struct pci_dev *pdev;
327 struct device dev;
328 struct cdev cdev;
329
330 int partition;
331 int partition_count;
332 int pff_csr_count;
333 char pff_local[SWITCHTEC_MAX_PFF_CSR];
334
335 void __iomem *mmio;
336 struct mrpc_regs __iomem *mmio_mrpc;
337 struct sw_event_regs __iomem *mmio_sw_event;
338 struct sys_info_regs __iomem *mmio_sys_info;
339 struct flash_info_regs __iomem *mmio_flash_info;
340 struct ntb_info_regs __iomem *mmio_ntb;
341 struct part_cfg_regs __iomem *mmio_part_cfg;
342 struct part_cfg_regs __iomem *mmio_part_cfg_all;
343 struct pff_csr_regs __iomem *mmio_pff_csr;
344
345 /*
346 * The mrpc mutex must be held when accessing the other
347 * mrpc_ fields, alive flag and stuser->state field
348 */
349 struct mutex mrpc_mutex;
350 struct list_head mrpc_queue;
351 int mrpc_busy;
352 struct work_struct mrpc_work;
353 struct delayed_work mrpc_timeout;
354 bool alive;
355
356 wait_queue_head_t event_wq;
357 atomic_t event_cnt;
358
359 struct work_struct link_event_work;
360 void (*link_notifier)(struct switchtec_dev *stdev);
361 u8 link_event_count[SWITCHTEC_MAX_PFF_CSR];
362
363 struct switchtec_ntb *sndev;
364};
365
366static inline struct switchtec_dev *to_stdev(struct device *dev)
367{
368 return container_of(dev, struct switchtec_dev, dev);
369}
370
371extern struct class *switchtec_class;
372
373#endif