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1/*
2 * Copyright 2016 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Author: Monk.liu@amd.com
23 */
24#ifndef AMDGPU_VIRT_H
25#define AMDGPU_VIRT_H
26
27#define AMDGPU_SRIOV_CAPS_SRIOV_VBIOS (1 << 0) /* vBIOS is sr-iov ready */
28#define AMDGPU_SRIOV_CAPS_ENABLE_IOV (1 << 1) /* sr-iov is enabled on this GPU */
29#define AMDGPU_SRIOV_CAPS_IS_VF (1 << 2) /* this GPU is a virtual function */
30#define AMDGPU_PASSTHROUGH_MODE (1 << 3) /* thw whole GPU is pass through for VM */
31#define AMDGPU_SRIOV_CAPS_RUNTIME (1 << 4) /* is out of full access mode */
32
33struct amdgpu_mm_table {
34 struct amdgpu_bo *bo;
35 uint32_t *cpu_addr;
36 uint64_t gpu_addr;
37};
38
39#define AMDGPU_VF_ERROR_ENTRY_SIZE 16
40
41/* struct error_entry - amdgpu VF error information. */
42struct amdgpu_vf_error_buffer {
43 struct mutex lock;
44 int read_count;
45 int write_count;
46 uint16_t code[AMDGPU_VF_ERROR_ENTRY_SIZE];
47 uint16_t flags[AMDGPU_VF_ERROR_ENTRY_SIZE];
48 uint64_t data[AMDGPU_VF_ERROR_ENTRY_SIZE];
49};
50
51/**
52 * struct amdgpu_virt_ops - amdgpu device virt operations
53 */
54struct amdgpu_virt_ops {
55 int (*req_full_gpu)(struct amdgpu_device *adev, bool init);
56 int (*rel_full_gpu)(struct amdgpu_device *adev, bool init);
57 int (*reset_gpu)(struct amdgpu_device *adev);
58 void (*trans_msg)(struct amdgpu_device *adev, u32 req, u32 data1, u32 data2, u32 data3);
59};
60
61/*
62 * Firmware Reserve Frame buffer
63 */
64struct amdgpu_virt_fw_reserve {
65 struct amdgim_pf2vf_info_header *p_pf2vf;
66 struct amdgim_vf2pf_info_header *p_vf2pf;
67 unsigned int checksum_key;
68};
69/*
70 * Defination between PF and VF
71 * Structures forcibly aligned to 4 to keep the same style as PF.
72 */
73#define AMDGIM_DATAEXCHANGE_OFFSET (64 * 1024)
74
75#define AMDGIM_GET_STRUCTURE_RESERVED_SIZE(total, u8, u16, u32, u64) \
76 (total - (((u8)+3) / 4 + ((u16)+1) / 2 + (u32) + (u64)*2))
77
78enum AMDGIM_FEATURE_FLAG {
79 /* GIM supports feature of Error log collecting */
80 AMDGIM_FEATURE_ERROR_LOG_COLLECT = 0x1,
81 /* GIM supports feature of loading uCodes */
82 AMDGIM_FEATURE_GIM_LOAD_UCODES = 0x2,
83};
84
85struct amdgim_pf2vf_info_header {
86 /* the total structure size in byte. */
87 uint32_t size;
88 /* version of this structure, written by the GIM */
89 uint32_t version;
90} __aligned(4);
91struct amdgim_pf2vf_info_v1 {
92 /* header contains size and version */
93 struct amdgim_pf2vf_info_header header;
94 /* max_width * max_height */
95 unsigned int uvd_enc_max_pixels_count;
96 /* 16x16 pixels/sec, codec independent */
97 unsigned int uvd_enc_max_bandwidth;
98 /* max_width * max_height */
99 unsigned int vce_enc_max_pixels_count;
100 /* 16x16 pixels/sec, codec independent */
101 unsigned int vce_enc_max_bandwidth;
102 /* MEC FW position in kb from the start of visible frame buffer */
103 unsigned int mecfw_kboffset;
104 /* The features flags of the GIM driver supports. */
105 unsigned int feature_flags;
106 /* use private key from mailbox 2 to create chueksum */
107 unsigned int checksum;
108} __aligned(4);
109
110struct amdgim_pf2vf_info_v2 {
111 /* header contains size and version */
112 struct amdgim_pf2vf_info_header header;
113 /* use private key from mailbox 2 to create chueksum */
114 uint32_t checksum;
115 /* The features flags of the GIM driver supports. */
116 uint32_t feature_flags;
117 /* max_width * max_height */
118 uint32_t uvd_enc_max_pixels_count;
119 /* 16x16 pixels/sec, codec independent */
120 uint32_t uvd_enc_max_bandwidth;
121 /* max_width * max_height */
122 uint32_t vce_enc_max_pixels_count;
123 /* 16x16 pixels/sec, codec independent */
124 uint32_t vce_enc_max_bandwidth;
125 /* MEC FW position in kb from the start of VF visible frame buffer */
126 uint64_t mecfw_kboffset;
127 /* MEC FW size in KB */
128 uint32_t mecfw_ksize;
129 /* UVD FW position in kb from the start of VF visible frame buffer */
130 uint64_t uvdfw_kboffset;
131 /* UVD FW size in KB */
132 uint32_t uvdfw_ksize;
133 /* VCE FW position in kb from the start of VF visible frame buffer */
134 uint64_t vcefw_kboffset;
135 /* VCE FW size in KB */
136 uint32_t vcefw_ksize;
137 uint32_t reserved[AMDGIM_GET_STRUCTURE_RESERVED_SIZE(256, 0, 0, (9 + sizeof(struct amdgim_pf2vf_info_header)/sizeof(uint32_t)), 3)];
138} __aligned(4);
139
140
141struct amdgim_vf2pf_info_header {
142 /* the total structure size in byte. */
143 uint32_t size;
144 /*version of this structure, written by the guest */
145 uint32_t version;
146} __aligned(4);
147
148struct amdgim_vf2pf_info_v1 {
149 /* header contains size and version */
150 struct amdgim_vf2pf_info_header header;
151 /* driver version */
152 char driver_version[64];
153 /* driver certification, 1=WHQL, 0=None */
154 unsigned int driver_cert;
155 /* guest OS type and version: need a define */
156 unsigned int os_info;
157 /* in the unit of 1M */
158 unsigned int fb_usage;
159 /* guest gfx engine usage percentage */
160 unsigned int gfx_usage;
161 /* guest gfx engine health percentage */
162 unsigned int gfx_health;
163 /* guest compute engine usage percentage */
164 unsigned int compute_usage;
165 /* guest compute engine health percentage */
166 unsigned int compute_health;
167 /* guest vce engine usage percentage. 0xffff means N/A. */
168 unsigned int vce_enc_usage;
169 /* guest vce engine health percentage. 0xffff means N/A. */
170 unsigned int vce_enc_health;
171 /* guest uvd engine usage percentage. 0xffff means N/A. */
172 unsigned int uvd_enc_usage;
173 /* guest uvd engine usage percentage. 0xffff means N/A. */
174 unsigned int uvd_enc_health;
175 unsigned int checksum;
176} __aligned(4);
177
178struct amdgim_vf2pf_info_v2 {
179 /* header contains size and version */
180 struct amdgim_vf2pf_info_header header;
181 uint32_t checksum;
182 /* driver version */
183 uint8_t driver_version[64];
184 /* driver certification, 1=WHQL, 0=None */
185 uint32_t driver_cert;
186 /* guest OS type and version: need a define */
187 uint32_t os_info;
188 /* in the unit of 1M */
189 uint32_t fb_usage;
190 /* guest gfx engine usage percentage */
191 uint32_t gfx_usage;
192 /* guest gfx engine health percentage */
193 uint32_t gfx_health;
194 /* guest compute engine usage percentage */
195 uint32_t compute_usage;
196 /* guest compute engine health percentage */
197 uint32_t compute_health;
198 /* guest vce engine usage percentage. 0xffff means N/A. */
199 uint32_t vce_enc_usage;
200 /* guest vce engine health percentage. 0xffff means N/A. */
201 uint32_t vce_enc_health;
202 /* guest uvd engine usage percentage. 0xffff means N/A. */
203 uint32_t uvd_enc_usage;
204 /* guest uvd engine usage percentage. 0xffff means N/A. */
205 uint32_t uvd_enc_health;
206 uint32_t reserved[AMDGIM_GET_STRUCTURE_RESERVED_SIZE(256, 64, 0, (12 + sizeof(struct amdgim_vf2pf_info_header)/sizeof(uint32_t)), 0)];
207} __aligned(4);
208
209#define AMDGPU_FW_VRAM_VF2PF_VER 2
210typedef struct amdgim_vf2pf_info_v2 amdgim_vf2pf_info ;
211
212#define AMDGPU_FW_VRAM_VF2PF_WRITE(adev, field, val) \
213 do { \
214 ((amdgim_vf2pf_info *)adev->virt.fw_reserve.p_vf2pf)->field = (val); \
215 } while (0)
216
217#define AMDGPU_FW_VRAM_VF2PF_READ(adev, field, val) \
218 do { \
219 (*val) = ((amdgim_vf2pf_info *)adev->virt.fw_reserve.p_vf2pf)->field; \
220 } while (0)
221
222#define AMDGPU_FW_VRAM_PF2VF_READ(adev, field, val) \
223 do { \
224 if (!adev->virt.fw_reserve.p_pf2vf) \
225 *(val) = 0; \
226 else { \
227 if (adev->virt.fw_reserve.p_pf2vf->version == 1) \
228 *(val) = ((struct amdgim_pf2vf_info_v1 *)adev->virt.fw_reserve.p_pf2vf)->field; \
229 if (adev->virt.fw_reserve.p_pf2vf->version == 2) \
230 *(val) = ((struct amdgim_pf2vf_info_v2 *)adev->virt.fw_reserve.p_pf2vf)->field; \
231 } \
232 } while (0)
233
234/* GPU virtualization */
235struct amdgpu_virt {
236 uint32_t caps;
237 struct amdgpu_bo *csa_obj;
238 uint64_t csa_vmid0_addr;
239 bool chained_ib_support;
240 uint32_t reg_val_offs;
241 struct mutex lock_reset;
242 struct amdgpu_irq_src ack_irq;
243 struct amdgpu_irq_src rcv_irq;
244 struct work_struct flr_work;
245 struct amdgpu_mm_table mm_table;
246 const struct amdgpu_virt_ops *ops;
247 struct amdgpu_vf_error_buffer vf_errors;
248 struct amdgpu_virt_fw_reserve fw_reserve;
249};
250
251#define AMDGPU_CSA_SIZE (8 * 1024)
252#define AMDGPU_CSA_VADDR (AMDGPU_VA_RESERVED_SIZE - AMDGPU_CSA_SIZE)
253
254#define amdgpu_sriov_enabled(adev) \
255((adev)->virt.caps & AMDGPU_SRIOV_CAPS_ENABLE_IOV)
256
257#define amdgpu_sriov_vf(adev) \
258((adev)->virt.caps & AMDGPU_SRIOV_CAPS_IS_VF)
259
260#define amdgpu_sriov_bios(adev) \
261((adev)->virt.caps & AMDGPU_SRIOV_CAPS_SRIOV_VBIOS)
262
263#define amdgpu_sriov_runtime(adev) \
264((adev)->virt.caps & AMDGPU_SRIOV_CAPS_RUNTIME)
265
266#define amdgpu_passthrough(adev) \
267((adev)->virt.caps & AMDGPU_PASSTHROUGH_MODE)
268
269static inline bool is_virtual_machine(void)
270{
271#ifdef CONFIG_X86
272 return boot_cpu_has(X86_FEATURE_HYPERVISOR);
273#else
274 return false;
275#endif
276}
277
278struct amdgpu_vm;
279int amdgpu_allocate_static_csa(struct amdgpu_device *adev);
280int amdgpu_map_static_csa(struct amdgpu_device *adev, struct amdgpu_vm *vm,
281 struct amdgpu_bo_va **bo_va);
282void amdgpu_virt_init_setting(struct amdgpu_device *adev);
283uint32_t amdgpu_virt_kiq_rreg(struct amdgpu_device *adev, uint32_t reg);
284void amdgpu_virt_kiq_wreg(struct amdgpu_device *adev, uint32_t reg, uint32_t v);
285int amdgpu_virt_request_full_gpu(struct amdgpu_device *adev, bool init);
286int amdgpu_virt_release_full_gpu(struct amdgpu_device *adev, bool init);
287int amdgpu_virt_reset_gpu(struct amdgpu_device *adev);
288int amdgpu_sriov_gpu_reset(struct amdgpu_device *adev, struct amdgpu_job *job);
289int amdgpu_virt_alloc_mm_table(struct amdgpu_device *adev);
290void amdgpu_virt_free_mm_table(struct amdgpu_device *adev);
291int amdgpu_virt_fw_reserve_get_checksum(void *obj, unsigned long obj_size,
292 unsigned int key,
293 unsigned int chksum);
294void amdgpu_virt_init_data_exchange(struct amdgpu_device *adev);
295
296#endif