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1Amlogic meson GPIO interrupt controller
2
3Meson SoCs contains an interrupt controller which is able to watch the SoC
4pads and generate an interrupt on edge or level. The controller is essentially
5a 256 pads to 8 GIC interrupt multiplexer, with a filter block to select edge
6or level and polarity. It does not expose all 256 mux inputs because the
7documentation shows that the upper part is not mapped to any pad. The actual
8number of interrupt exposed depends on the SoC.
9
10Required properties:
11
12- compatible : must have "amlogic,meson8-gpio-intc” and either
13 “amlogic,meson8-gpio-intc” for meson8 SoCs (S802) or
14 “amlogic,meson8b-gpio-intc” for meson8b SoCs (S805) or
15 “amlogic,meson-gxbb-gpio-intc” for GXBB SoCs (S905) or
16 “amlogic,meson-gxl-gpio-intc” for GXL SoCs (S905X, S912)
17- interrupt-parent : a phandle to the GIC the interrupts are routed to.
18 Usually this is provided at the root level of the device tree as it is
19 common to most of the SoC.
20- reg : Specifies base physical address and size of the registers.
21- interrupt-controller : Identifies the node as an interrupt controller.
22- #interrupt-cells : Specifies the number of cells needed to encode an
23 interrupt source. The value must be 2.
24- meson,channel-interrupts: Array with the 8 upstream hwirq numbers. These
25 are the hwirqs used on the parent interrupt controller.
26
27Example:
28
29gpio_interrupt: interrupt-controller@9880 {
30 compatible = "amlogic,meson-gxbb-gpio-intc",
31 "amlogic,meson-gpio-intc";
32 reg = <0x0 0x9880 0x0 0x10>;
33 interrupt-controller;
34 #interrupt-cells = <2>;
35 meson,channel-interrupts = <64 65 66 67 68 69 70 71>;
36};