tjh.dev
Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
1/* SPDX-License-Identifier: GPL-2.0 */
2#ifndef SPI_BCM53XX_H
3#define SPI_BCM53XX_H
4
5#define B53SPI_BSPI_REVISION_ID 0x000
6#define B53SPI_BSPI_SCRATCH 0x004
7#define B53SPI_BSPI_MAST_N_BOOT_CTRL 0x008
8#define B53SPI_BSPI_BUSY_STATUS 0x00c
9#define B53SPI_BSPI_INTR_STATUS 0x010
10#define B53SPI_BSPI_B0_STATUS 0x014
11#define B53SPI_BSPI_B0_CTRL 0x018
12#define B53SPI_BSPI_B1_STATUS 0x01c
13#define B53SPI_BSPI_B1_CTRL 0x020
14#define B53SPI_BSPI_STRAP_OVERRIDE_CTRL 0x024
15#define B53SPI_BSPI_FLEX_MODE_ENABLE 0x028
16#define B53SPI_BSPI_BITS_PER_CYCLE 0x02c
17#define B53SPI_BSPI_BITS_PER_PHASE 0x030
18#define B53SPI_BSPI_CMD_AND_MODE_BYTE 0x034
19#define B53SPI_BSPI_BSPI_FLASH_UPPER_ADDR_BYTE 0x038
20#define B53SPI_BSPI_BSPI_XOR_VALUE 0x03c
21#define B53SPI_BSPI_BSPI_XOR_ENABLE 0x040
22#define B53SPI_BSPI_BSPI_PIO_MODE_ENABLE 0x044
23#define B53SPI_BSPI_BSPI_PIO_IODIR 0x048
24#define B53SPI_BSPI_BSPI_PIO_DATA 0x04c
25
26/* RAF */
27#define B53SPI_RAF_START_ADDR 0x100
28#define B53SPI_RAF_NUM_WORDS 0x104
29#define B53SPI_RAF_CTRL 0x108
30#define B53SPI_RAF_FULLNESS 0x10c
31#define B53SPI_RAF_WATERMARK 0x110
32#define B53SPI_RAF_STATUS 0x114
33#define B53SPI_RAF_READ_DATA 0x118
34#define B53SPI_RAF_WORD_CNT 0x11c
35#define B53SPI_RAF_CURR_ADDR 0x120
36
37/* MSPI */
38#define B53SPI_MSPI_SPCR0_LSB 0x200
39#define B53SPI_MSPI_SPCR0_MSB 0x204
40#define B53SPI_MSPI_SPCR1_LSB 0x208
41#define B53SPI_MSPI_SPCR1_MSB 0x20c
42#define B53SPI_MSPI_NEWQP 0x210
43#define B53SPI_MSPI_ENDQP 0x214
44#define B53SPI_MSPI_SPCR2 0x218
45#define B53SPI_MSPI_SPCR2_SPE 0x00000040
46#define B53SPI_MSPI_SPCR2_CONT_AFTER_CMD 0x00000080
47#define B53SPI_MSPI_MSPI_STATUS 0x220
48#define B53SPI_MSPI_MSPI_STATUS_SPIF 0x00000001
49#define B53SPI_MSPI_CPTQP 0x224
50#define B53SPI_MSPI_TXRAM 0x240 /* 32 registers, up to 0x2b8 */
51#define B53SPI_MSPI_RXRAM 0x2c0 /* 32 registers, up to 0x33c */
52#define B53SPI_MSPI_CDRAM 0x340 /* 16 registers, up to 0x37c */
53#define B53SPI_CDRAM_PCS_PCS0 0x00000001
54#define B53SPI_CDRAM_PCS_PCS1 0x00000002
55#define B53SPI_CDRAM_PCS_PCS2 0x00000004
56#define B53SPI_CDRAM_PCS_PCS3 0x00000008
57#define B53SPI_CDRAM_PCS_DISABLE_ALL 0x0000000f
58#define B53SPI_CDRAM_PCS_DSCK 0x00000010
59#define B53SPI_CDRAM_BITSE 0x00000040
60#define B53SPI_CDRAM_CONT 0x00000080
61#define B53SPI_MSPI_WRITE_LOCK 0x380
62#define B53SPI_MSPI_DISABLE_FLUSH_GEN 0x384
63
64/* Interrupt */
65#define B53SPI_INTR_RAF_LR_FULLNESS_REACHED 0x3a0
66#define B53SPI_INTR_RAF_LR_TRUNCATED 0x3a4
67#define B53SPI_INTR_RAF_LR_IMPATIENT 0x3a8
68#define B53SPI_INTR_RAF_LR_SESSION_DONE 0x3ac
69#define B53SPI_INTR_RAF_LR_OVERREAD 0x3b0
70#define B53SPI_INTR_MSPI_DONE 0x3b4
71#define B53SPI_INTR_MSPI_HALT_SET_TRANSACTION_DONE 0x3b8
72
73#endif /* SPI_BCM53XX_H */