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Linux kernel mirror (for testing)
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1/*
2 * Copyright 2017 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: AMD
23 *
24 */
25
26#ifndef __DML2_DISPLAY_MODE_VBA_H__
27#define __DML2_DISPLAY_MODE_VBA_H__
28
29#include "dml_common_defs.h"
30
31struct display_mode_lib;
32
33void set_prefetch_mode(struct display_mode_lib *mode_lib,
34 bool cstate_en,
35 bool pstate_en,
36 bool ignore_viewport_pos,
37 bool immediate_flip_support);
38
39#define dml_get_attr_decl(attr) double get_##attr(struct display_mode_lib *mode_lib, const display_e2e_pipe_params_st *pipes, unsigned int num_pipes)
40
41dml_get_attr_decl(clk_dcf_deepsleep);
42dml_get_attr_decl(wm_urgent);
43dml_get_attr_decl(wm_memory_trip);
44dml_get_attr_decl(wm_writeback_urgent);
45dml_get_attr_decl(wm_stutter_exit);
46dml_get_attr_decl(wm_stutter_enter_exit);
47dml_get_attr_decl(wm_dram_clock_change);
48dml_get_attr_decl(wm_writeback_dram_clock_change);
49dml_get_attr_decl(wm_xfc_underflow);
50dml_get_attr_decl(stutter_efficiency_no_vblank);
51dml_get_attr_decl(stutter_efficiency);
52dml_get_attr_decl(urgent_latency);
53dml_get_attr_decl(urgent_extra_latency);
54dml_get_attr_decl(nonurgent_latency);
55dml_get_attr_decl(dram_clock_change_latency);
56dml_get_attr_decl(dispclk_calculated);
57dml_get_attr_decl(total_data_read_bw);
58dml_get_attr_decl(return_bw);
59dml_get_attr_decl(tcalc);
60
61#define dml_get_pipe_attr_decl(attr) double get_##attr(struct display_mode_lib *mode_lib, const display_e2e_pipe_params_st *pipes, unsigned int num_pipes, unsigned int which_pipe)
62
63dml_get_pipe_attr_decl(dsc_delay);
64dml_get_pipe_attr_decl(dppclk_calculated);
65dml_get_pipe_attr_decl(dscclk_calculated);
66dml_get_pipe_attr_decl(min_ttu_vblank);
67dml_get_pipe_attr_decl(vratio_prefetch_l);
68dml_get_pipe_attr_decl(vratio_prefetch_c);
69dml_get_pipe_attr_decl(dst_x_after_scaler);
70dml_get_pipe_attr_decl(dst_y_after_scaler);
71dml_get_pipe_attr_decl(dst_y_per_vm_vblank);
72dml_get_pipe_attr_decl(dst_y_per_row_vblank);
73dml_get_pipe_attr_decl(dst_y_prefetch);
74dml_get_pipe_attr_decl(dst_y_per_vm_flip);
75dml_get_pipe_attr_decl(dst_y_per_row_flip);
76dml_get_pipe_attr_decl(xfc_transfer_delay);
77dml_get_pipe_attr_decl(xfc_precharge_delay);
78dml_get_pipe_attr_decl(xfc_remote_surface_flip_latency);
79dml_get_pipe_attr_decl(xfc_prefetch_margin);
80
81unsigned int get_vstartup_calculated(
82 struct display_mode_lib *mode_lib,
83 const display_e2e_pipe_params_st *pipes,
84 unsigned int num_pipes,
85 unsigned int which_pipe);
86
87double get_total_immediate_flip_bytes(
88 struct display_mode_lib *mode_lib,
89 const display_e2e_pipe_params_st *pipes,
90 unsigned int num_pipes);
91double get_total_immediate_flip_bw(
92 struct display_mode_lib *mode_lib,
93 const display_e2e_pipe_params_st *pipes,
94 unsigned int num_pipes);
95double get_total_prefetch_bw(
96 struct display_mode_lib *mode_lib,
97 const display_e2e_pipe_params_st *pipes,
98 unsigned int num_pipes);
99
100unsigned int dml_get_voltage_level(
101 struct display_mode_lib *mode_lib,
102 const display_e2e_pipe_params_st *pipes,
103 unsigned int num_pipes);
104
105bool Calculate256BBlockSizes(
106 enum source_format_class SourcePixelFormat,
107 enum dm_swizzle_mode SurfaceTiling,
108 unsigned int BytePerPixelY,
109 unsigned int BytePerPixelC,
110 unsigned int *BlockHeight256BytesY,
111 unsigned int *BlockHeight256BytesC,
112 unsigned int *BlockWidth256BytesY,
113 unsigned int *BlockWidth256BytesC);
114
115
116struct vba_vars_st {
117 ip_params_st ip;
118 soc_bounding_box_st soc;
119
120 unsigned int MaximumMaxVStartupLines;
121 double cursor_bw[DC__NUM_DPP__MAX];
122 double meta_row_bw[DC__NUM_DPP__MAX];
123 double dpte_row_bw[DC__NUM_DPP__MAX];
124 double qual_row_bw[DC__NUM_DPP__MAX];
125 double WritebackDISPCLK;
126 double PSCL_THROUGHPUT_LUMA[DC__NUM_DPP__MAX];
127 double PSCL_THROUGHPUT_CHROMA[DC__NUM_DPP__MAX];
128 double DPPCLKUsingSingleDPPLuma;
129 double DPPCLKUsingSingleDPPChroma;
130 double DPPCLKUsingSingleDPP[DC__NUM_DPP__MAX];
131 double DISPCLKWithRamping;
132 double DISPCLKWithoutRamping;
133 double GlobalDPPCLK;
134 double DISPCLKWithRampingRoundedToDFSGranularity;
135 double DISPCLKWithoutRampingRoundedToDFSGranularity;
136 double MaxDispclkRoundedToDFSGranularity;
137 bool DCCEnabledAnyPlane;
138 double ReturnBandwidthToDCN;
139 unsigned int SwathWidthY[DC__NUM_DPP__MAX];
140 unsigned int SwathWidthSingleDPPY[DC__NUM_DPP__MAX];
141 double BytePerPixelDETY[DC__NUM_DPP__MAX];
142 double BytePerPixelDETC[DC__NUM_DPP__MAX];
143 double ReadBandwidthPlaneLuma[DC__NUM_DPP__MAX];
144 double ReadBandwidthPlaneChroma[DC__NUM_DPP__MAX];
145 unsigned int TotalActiveDPP;
146 unsigned int TotalDCCActiveDPP;
147 double UrgentRoundTripAndOutOfOrderLatency;
148 double DisplayPipeLineDeliveryTimeLuma[DC__NUM_DPP__MAX]; // WM
149 double DisplayPipeLineDeliveryTimeChroma[DC__NUM_DPP__MAX]; // WM
150 double LinesInDETY[DC__NUM_DPP__MAX]; // WM
151 double LinesInDETC[DC__NUM_DPP__MAX]; // WM
152 unsigned int LinesInDETYRoundedDownToSwath[DC__NUM_DPP__MAX]; // WM
153 unsigned int LinesInDETCRoundedDownToSwath[DC__NUM_DPP__MAX]; // WM
154 double FullDETBufferingTimeY[DC__NUM_DPP__MAX]; // WM
155 double FullDETBufferingTimeC[DC__NUM_DPP__MAX]; // WM
156 double MinFullDETBufferingTime;
157 double FrameTimeForMinFullDETBufferingTime;
158 double AverageReadBandwidthGBytePerSecond;
159 double PartOfBurstThatFitsInROB;
160 double StutterBurstTime;
161 //unsigned int NextPrefetchMode;
162 double VBlankTime;
163 double SmallestVBlank;
164 double DCFCLKDeepSleepPerPlane;
165 double EffectiveDETPlusLBLinesLuma;
166 double EffectiveDETPlusLBLinesChroma;
167 double UrgentLatencySupportUsLuma;
168 double UrgentLatencySupportUsChroma;
169 double UrgentLatencySupportUs[DC__NUM_DPP__MAX];
170 unsigned int DSCFormatFactor;
171 unsigned int BlockHeight256BytesY[DC__NUM_DPP__MAX];
172 unsigned int BlockHeight256BytesC[DC__NUM_DPP__MAX];
173 unsigned int BlockWidth256BytesY[DC__NUM_DPP__MAX];
174 unsigned int BlockWidth256BytesC[DC__NUM_DPP__MAX];
175 double VInitPreFillY[DC__NUM_DPP__MAX];
176 double VInitPreFillC[DC__NUM_DPP__MAX];
177 unsigned int MaxNumSwathY[DC__NUM_DPP__MAX];
178 unsigned int MaxNumSwathC[DC__NUM_DPP__MAX];
179 double PrefetchSourceLinesY[DC__NUM_DPP__MAX];
180 double PrefetchSourceLinesC[DC__NUM_DPP__MAX];
181 double PixelPTEBytesPerRow[DC__NUM_DPP__MAX];
182 double MetaRowByte[DC__NUM_DPP__MAX];
183 unsigned int dpte_row_height[DC__NUM_DPP__MAX];
184 unsigned int dpte_row_height_chroma[DC__NUM_DPP__MAX];
185 unsigned int meta_row_height[DC__NUM_DPP__MAX];
186 unsigned int meta_row_height_chroma[DC__NUM_DPP__MAX];
187
188 unsigned int MacroTileWidthY[DC__NUM_DPP__MAX];
189 unsigned int MacroTileWidthC[DC__NUM_DPP__MAX];
190 unsigned int MaxVStartupLines[DC__NUM_DPP__MAX];
191 double WritebackDelay[DC__VOLTAGE_STATES + 1][DC__NUM_DPP__MAX];
192 bool PrefetchModeSupported;
193 bool AllowDRAMClockChangeDuringVBlank[DC__NUM_DPP__MAX];
194 bool AllowDRAMSelfRefreshDuringVBlank[DC__NUM_DPP__MAX];
195 double RequiredPrefetchPixDataBW[DC__NUM_DPP__MAX];
196 double XFCRemoteSurfaceFlipDelay;
197 double TInitXFill;
198 double TslvChk;
199 double SrcActiveDrainRate;
200 double Tno_bw[DC__NUM_DPP__MAX];
201 bool ImmediateFlipSupported;
202
203 double prefetch_vm_bw[DC__NUM_DPP__MAX];
204 double prefetch_row_bw[DC__NUM_DPP__MAX];
205 bool ImmediateFlipSupportedForPipe[DC__NUM_DPP__MAX];
206 unsigned int VStartupLines;
207 double DisplayPipeLineDeliveryTimeLumaPrefetch[DC__NUM_DPP__MAX];
208 double DisplayPipeLineDeliveryTimeChromaPrefetch[DC__NUM_DPP__MAX];
209 unsigned int ActiveDPPs;
210 unsigned int LBLatencyHidingSourceLinesY;
211 unsigned int LBLatencyHidingSourceLinesC;
212 double ActiveDRAMClockChangeLatencyMargin[DC__NUM_DPP__MAX];
213 double MinActiveDRAMClockChangeMargin;
214 double XFCSlaveVUpdateOffset[DC__NUM_DPP__MAX];
215 double XFCSlaveVupdateWidth[DC__NUM_DPP__MAX];
216 double XFCSlaveVReadyOffset[DC__NUM_DPP__MAX];
217 double InitFillLevel;
218 double FinalFillMargin;
219 double FinalFillLevel;
220 double RemainingFillLevel;
221 double TFinalxFill;
222
223
224 //
225 // SOC Bounding Box Parameters
226 //
227 double SRExitTime;
228 double SREnterPlusExitTime;
229 double UrgentLatency;
230 double WritebackLatency;
231 double PercentOfIdealDRAMAndFabricBWReceivedAfterUrgLatency;
232 double NumberOfChannels;
233 double DRAMChannelWidth;
234 double FabricDatapathToDCNDataReturn;
235 double ReturnBusWidth;
236 double Downspreading;
237 double DISPCLKDPPCLKDSCCLKDownSpreading;
238 double DISPCLKDPPCLKVCOSpeed;
239 double RoundTripPingLatencyCycles;
240 double UrgentOutOfOrderReturnPerChannel;
241 unsigned int VMMPageSize;
242 double DRAMClockChangeLatency;
243 double XFCBusTransportTime;
244 double XFCXBUFLatencyTolerance;
245
246 //
247 // IP Parameters
248 //
249 unsigned int ROBBufferSizeInKByte;
250 double DETBufferSizeInKByte;
251 unsigned int DPPOutputBufferPixels;
252 unsigned int OPPOutputBufferLines;
253 unsigned int PixelChunkSizeInKByte;
254 double ReturnBW;
255 bool VirtualMemoryEnable;
256 unsigned int MaxPageTableLevels;
257 unsigned int OverridePageTableLevels;
258 unsigned int PTEChunkSize;
259 unsigned int MetaChunkSize;
260 unsigned int WritebackChunkSize;
261 bool ODMCapability;
262 unsigned int NumberOfDSC;
263 unsigned int LineBufferSize;
264 unsigned int MaxLineBufferLines;
265 unsigned int WritebackInterfaceLumaBufferSize;
266 unsigned int WritebackInterfaceChromaBufferSize;
267 unsigned int WritebackChromaLineBufferWidth;
268 double MaxDCHUBToPSCLThroughput;
269 double MaxPSCLToLBThroughput;
270 unsigned int PTEBufferSizeInRequests;
271 double DISPCLKRampingMargin;
272 unsigned int MaxInterDCNTileRepeaters;
273 bool XFCSupported;
274 double XFCSlvChunkSize;
275 double XFCFillBWOverhead;
276 double XFCFillConstant;
277 double XFCTSlvVupdateOffset;
278 double XFCTSlvVupdateWidth;
279 double XFCTSlvVreadyOffset;
280 double DPPCLKDelaySubtotal;
281 double DPPCLKDelaySCL;
282 double DPPCLKDelaySCLLBOnly;
283 double DPPCLKDelayCNVCFormater;
284 double DPPCLKDelayCNVCCursor;
285 double DISPCLKDelaySubtotal;
286 bool ProgressiveToInterlaceUnitInOPP;
287 unsigned int PDEProcessingBufIn64KBReqs;
288
289 // Pipe/Plane Parameters
290 int VoltageLevel;
291 double FabricAndDRAMBandwidth;
292 double FabricClock;
293 double DRAMSpeed;
294 double DISPCLK;
295 double SOCCLK;
296 double DCFCLK;
297
298 unsigned int NumberOfActivePlanes;
299 unsigned int ViewportWidth[DC__NUM_DPP__MAX];
300 unsigned int ViewportHeight[DC__NUM_DPP__MAX];
301 unsigned int ViewportYStartY[DC__NUM_DPP__MAX];
302 unsigned int ViewportYStartC[DC__NUM_DPP__MAX];
303 unsigned int PitchY[DC__NUM_DPP__MAX];
304 unsigned int PitchC[DC__NUM_DPP__MAX];
305 double HRatio[DC__NUM_DPP__MAX];
306 double VRatio[DC__NUM_DPP__MAX];
307 unsigned int htaps[DC__NUM_DPP__MAX];
308 unsigned int vtaps[DC__NUM_DPP__MAX];
309 unsigned int HTAPsChroma[DC__NUM_DPP__MAX];
310 unsigned int VTAPsChroma[DC__NUM_DPP__MAX];
311 unsigned int HTotal[DC__NUM_DPP__MAX];
312 unsigned int VTotal[DC__NUM_DPP__MAX];
313 unsigned int DPPPerPlane[DC__NUM_DPP__MAX];
314 double PixelClock[DC__NUM_DPP__MAX];
315 double PixelClockBackEnd[DC__NUM_DPP__MAX];
316 double DPPCLK[DC__NUM_DPP__MAX];
317 bool DCCEnable[DC__NUM_DPP__MAX];
318 unsigned int DCCMetaPitchY[DC__NUM_DPP__MAX];
319 enum scan_direction_class SourceScan[DC__NUM_DPP__MAX];
320 enum source_format_class SourcePixelFormat[DC__NUM_DPP__MAX];
321 bool WritebackEnable[DC__NUM_DPP__MAX];
322 double WritebackDestinationWidth[DC__NUM_DPP__MAX];
323 double WritebackDestinationHeight[DC__NUM_DPP__MAX];
324 double WritebackSourceHeight[DC__NUM_DPP__MAX];
325 enum source_format_class WritebackPixelFormat[DC__NUM_DPP__MAX];
326 unsigned int WritebackLumaHTaps[DC__NUM_DPP__MAX];
327 unsigned int WritebackLumaVTaps[DC__NUM_DPP__MAX];
328 unsigned int WritebackChromaHTaps[DC__NUM_DPP__MAX];
329 unsigned int WritebackChromaVTaps[DC__NUM_DPP__MAX];
330 double WritebackHRatio[DC__NUM_DPP__MAX];
331 double WritebackVRatio[DC__NUM_DPP__MAX];
332 unsigned int HActive[DC__NUM_DPP__MAX];
333 unsigned int VActive[DC__NUM_DPP__MAX];
334 bool Interlace[DC__NUM_DPP__MAX];
335 enum dm_swizzle_mode SurfaceTiling[DC__NUM_DPP__MAX];
336 unsigned int ScalerRecoutWidth[DC__NUM_DPP__MAX];
337 bool DynamicMetadataEnable[DC__NUM_DPP__MAX];
338 unsigned int DynamicMetadataLinesBeforeActiveRequired[DC__NUM_DPP__MAX];
339 unsigned int DynamicMetadataTransmittedBytes[DC__NUM_DPP__MAX];
340 double DCCRate[DC__NUM_DPP__MAX];
341 bool ODMCombineEnabled[DC__NUM_DPP__MAX];
342 double OutputBpp[DC__NUM_DPP__MAX];
343 unsigned int NumberOfDSCSlices[DC__NUM_DPP__MAX];
344 bool DSCEnabled[DC__NUM_DPP__MAX];
345 unsigned int DSCDelay[DC__NUM_DPP__MAX];
346 unsigned int DSCInputBitPerComponent[DC__NUM_DPP__MAX];
347 enum output_format_class OutputFormat[DC__NUM_DPP__MAX];
348 enum output_encoder_class Output[DC__NUM_DPP__MAX];
349 unsigned int BlendingAndTiming[DC__NUM_DPP__MAX];
350 bool SynchronizedVBlank;
351 unsigned int NumberOfCursors[DC__NUM_DPP__MAX];
352 unsigned int CursorWidth[DC__NUM_DPP__MAX][DC__NUM_CURSOR__MAX];
353 unsigned int CursorBPP[DC__NUM_DPP__MAX][DC__NUM_CURSOR__MAX];
354 bool XFCEnabled[DC__NUM_DPP__MAX];
355 bool ScalerEnabled[DC__NUM_DPP__MAX];
356
357 // Intermediates/Informational
358 bool ImmediateFlipSupport;
359 unsigned int SwathHeightY[DC__NUM_DPP__MAX];
360 unsigned int SwathHeightC[DC__NUM_DPP__MAX];
361 unsigned int DETBufferSizeY[DC__NUM_DPP__MAX];
362 unsigned int DETBufferSizeC[DC__NUM_DPP__MAX];
363 unsigned int LBBitPerPixel[DC__NUM_DPP__MAX];
364 double LastPixelOfLineExtraWatermark;
365 double TotalDataReadBandwidth;
366 unsigned int TotalActiveWriteback;
367 unsigned int EffectiveLBLatencyHidingSourceLinesLuma;
368 unsigned int EffectiveLBLatencyHidingSourceLinesChroma;
369 double BandwidthAvailableForImmediateFlip;
370 unsigned int PrefetchMode;
371 bool IgnoreViewportPositioning;
372 double PrefetchBandwidth[DC__NUM_DPP__MAX];
373 bool ErrorResult[DC__NUM_DPP__MAX];
374 double PDEAndMetaPTEBytesFrame[DC__NUM_DPP__MAX];
375
376 //
377 // Calculated dml_ml->vba.Outputs
378 //
379 double DCFClkDeepSleep;
380 double UrgentWatermark;
381 double UrgentExtraLatency;
382 double MemoryTripWatermark;
383 double WritebackUrgentWatermark;
384 double StutterExitWatermark;
385 double StutterEnterPlusExitWatermark;
386 double DRAMClockChangeWatermark;
387 double WritebackDRAMClockChangeWatermark;
388 double StutterEfficiency;
389 double StutterEfficiencyNotIncludingVBlank;
390 double MinUrgentLatencySupportUs;
391 double NonUrgentLatencyTolerance;
392 double MinActiveDRAMClockChangeLatencySupported;
393 enum clock_change_support DRAMClockChangeSupport;
394
395 // These are the clocks calcuated by the library but they are not actually
396 // used explicitly. They are fetched by tests and then possibly used. The
397 // ultimate values to use are the ones specified by the parameters to DML
398 double DISPCLK_calculated;
399 double DSCCLK_calculated[DC__NUM_DPP__MAX];
400 double DPPCLK_calculated[DC__NUM_DPP__MAX];
401
402 unsigned int VStartup[DC__NUM_DPP__MAX];
403 unsigned int VUpdateOffsetPix[DC__NUM_DPP__MAX];
404 unsigned int VUpdateWidthPix[DC__NUM_DPP__MAX];
405 unsigned int VReadyOffsetPix[DC__NUM_DPP__MAX];
406 unsigned int VStartupRequiredWhenNotEnoughTimeForDynamicMetadata;
407
408 double ImmediateFlipBW;
409 unsigned int TotImmediateFlipBytes;
410 double TCalc;
411 double MinTTUVBlank[DC__NUM_DPP__MAX];
412 double VRatioPrefetchY[DC__NUM_DPP__MAX];
413 double VRatioPrefetchC[DC__NUM_DPP__MAX];
414 double DSTXAfterScaler[DC__NUM_DPP__MAX];
415 double DSTYAfterScaler[DC__NUM_DPP__MAX];
416
417 double DestinationLinesToRequestVMInVBlank[DC__NUM_DPP__MAX];
418 double DestinationLinesToRequestRowInVBlank[DC__NUM_DPP__MAX];
419 double DestinationLinesForPrefetch[DC__NUM_DPP__MAX];
420 double DestinationLinesToRequestRowInImmediateFlip[DC__NUM_DPP__MAX];
421 double DestinationLinesToRequestVMInImmediateFlip[DC__NUM_DPP__MAX];
422
423 double XFCTransferDelay[DC__NUM_DPP__MAX];
424 double XFCPrechargeDelay[DC__NUM_DPP__MAX];
425 double XFCRemoteSurfaceFlipLatency[DC__NUM_DPP__MAX];
426 double XFCPrefetchMargin[DC__NUM_DPP__MAX];
427
428 display_e2e_pipe_params_st cache_pipes[DC__NUM_DPP__MAX];
429 unsigned int cache_num_pipes;
430 unsigned int pipe_plane[DC__NUM_DPP__MAX];
431
432 /* vba mode support */
433 /*inputs*/
434 bool SupportGFX7CompatibleTilingIn32bppAnd64bpp;
435 double MaxHSCLRatio;
436 double MaxVSCLRatio;
437 unsigned int MaxNumWriteback;
438 bool WritebackLumaAndChromaScalingSupported;
439 bool Cursor64BppSupport;
440 double DCFCLKPerState[DC__VOLTAGE_STATES + 1];
441 double FabricClockPerState[DC__VOLTAGE_STATES + 1];
442 double SOCCLKPerState[DC__VOLTAGE_STATES + 1];
443 double PHYCLKPerState[DC__VOLTAGE_STATES + 1];
444 double MaxDppclk[DC__VOLTAGE_STATES + 1];
445 double MaxDSCCLK[DC__VOLTAGE_STATES + 1];
446 double DRAMSpeedPerState[DC__VOLTAGE_STATES + 1];
447 double MaxDispclk[DC__VOLTAGE_STATES + 1];
448
449 /*outputs*/
450 bool ScaleRatioAndTapsSupport;
451 bool SourceFormatPixelAndScanSupport;
452 unsigned int SwathWidthYSingleDPP[DC__NUM_DPP__MAX];
453 double BytePerPixelInDETY[DC__NUM_DPP__MAX];
454 double BytePerPixelInDETC[DC__NUM_DPP__MAX];
455 double TotalReadBandwidthConsumedGBytePerSecond;
456 double ReadBandwidth[DC__NUM_DPP__MAX];
457 double TotalWriteBandwidthConsumedGBytePerSecond;
458 double WriteBandwidth[DC__NUM_DPP__MAX];
459 double TotalBandwidthConsumedGBytePerSecond;
460 bool DCCEnabledInAnyPlane;
461 bool WritebackLatencySupport;
462 bool WritebackModeSupport;
463 bool Writeback10bpc420Supported;
464 bool BandwidthSupport[DC__VOLTAGE_STATES + 1];
465 unsigned int TotalNumberOfActiveWriteback;
466 double CriticalPoint;
467 double ReturnBWToDCNPerState;
468 double FabricAndDRAMBandwidthPerState[DC__VOLTAGE_STATES + 1];
469 double ReturnBWPerState[DC__VOLTAGE_STATES + 1];
470 double UrgentRoundTripAndOutOfOrderLatencyPerState[DC__VOLTAGE_STATES + 1];
471 bool ODMCombineEnablePerState[DC__VOLTAGE_STATES + 1][DC__NUM_DPP__MAX];
472 bool PTEBufferSizeNotExceededY[DC__VOLTAGE_STATES + 1][DC__NUM_DPP__MAX];
473 bool PTEBufferSizeNotExceededC[DC__VOLTAGE_STATES + 1][DC__NUM_DPP__MAX];
474 bool PrefetchSupported[DC__VOLTAGE_STATES + 1];
475 bool VRatioInPrefetchSupported[DC__VOLTAGE_STATES + 1];
476 bool DISPCLK_DPPCLK_Support[DC__VOLTAGE_STATES + 1];
477 bool TotalAvailablePipesSupport[DC__VOLTAGE_STATES + 1];
478 bool UrgentLatencySupport[DC__VOLTAGE_STATES + 1];
479 bool ModeSupport[DC__VOLTAGE_STATES + 1];
480 bool DIOSupport[DC__VOLTAGE_STATES + 1];
481 bool NotEnoughDSCUnits[DC__VOLTAGE_STATES + 1];
482 bool DSCCLKRequiredMoreThanSupported[DC__VOLTAGE_STATES + 1];
483 bool ROBSupport[DC__VOLTAGE_STATES + 1];
484 bool PTEBufferSizeNotExceeded[DC__VOLTAGE_STATES + 1];
485 bool RequiresDSC[DC__VOLTAGE_STATES + 1][DC__NUM_DPP__MAX];
486 bool IsErrorResult[DC__VOLTAGE_STATES + 1][DC__NUM_DPP__MAX];
487 bool ViewportSizeSupport[DC__VOLTAGE_STATES + 1];
488 bool prefetch_vm_bw_valid;
489 bool prefetch_row_bw_valid;
490 bool NumberOfOTGSupport;
491 bool NonsupportedDSCInputBPC;
492 bool WritebackScaleRatioAndTapsSupport;
493 bool CursorSupport;
494 bool PitchSupport;
495
496 double WritebackLineBufferLumaBufferSize;
497 double WritebackLineBufferChromaBufferSize;
498 double WritebackMinHSCLRatio;
499 double WritebackMinVSCLRatio;
500 double WritebackMaxHSCLRatio;
501 double WritebackMaxVSCLRatio;
502 double WritebackMaxHSCLTaps;
503 double WritebackMaxVSCLTaps;
504 unsigned int MaxNumDPP;
505 unsigned int MaxNumOTG;
506 double CursorBufferSize;
507 double CursorChunkSize;
508 unsigned int Mode;
509 unsigned int NoOfDPP[DC__VOLTAGE_STATES + 1][DC__NUM_DPP__MAX];
510 double OutputLinkDPLanes[DC__NUM_DPP__MAX];
511 double SwathWidthYPerState[DC__VOLTAGE_STATES + 1][DC__NUM_DPP__MAX];
512 double SwathHeightYPerState[DC__VOLTAGE_STATES + 1][DC__NUM_DPP__MAX];
513 double SwathHeightCPerState[DC__VOLTAGE_STATES + 1][DC__NUM_DPP__MAX];
514 double UrgentLatencySupportUsPerState[DC__VOLTAGE_STATES + 1][DC__NUM_DPP__MAX];
515 double VRatioPreY[DC__VOLTAGE_STATES + 1][DC__NUM_DPP__MAX];
516 double VRatioPreC[DC__VOLTAGE_STATES + 1][DC__NUM_DPP__MAX];
517 double RequiredPrefetchPixelDataBW[DC__VOLTAGE_STATES + 1][DC__NUM_DPP__MAX];
518 double RequiredDPPCLK[DC__VOLTAGE_STATES + 1][DC__NUM_DPP__MAX];
519 double RequiredDISPCLK[DC__VOLTAGE_STATES + 1];
520 double TotalNumberOfActiveDPP[DC__VOLTAGE_STATES + 1];
521 double TotalNumberOfDCCActiveDPP[DC__VOLTAGE_STATES + 1];
522 double PrefetchBW[DC__NUM_DPP__MAX];
523 double PDEAndMetaPTEBytesPerFrame[DC__NUM_DPP__MAX];
524 double MetaRowBytes[DC__NUM_DPP__MAX];
525 double DPTEBytesPerRow[DC__NUM_DPP__MAX];
526 double PrefetchLinesY[DC__NUM_DPP__MAX];
527 double PrefetchLinesC[DC__NUM_DPP__MAX];
528 unsigned int MaxNumSwY[DC__NUM_DPP__MAX];
529 unsigned int MaxNumSwC[DC__NUM_DPP__MAX];
530 double PrefillY[DC__NUM_DPP__MAX];
531 double PrefillC[DC__NUM_DPP__MAX];
532 double LineTimesForPrefetch[DC__NUM_DPP__MAX];
533 double LinesForMetaPTE[DC__NUM_DPP__MAX];
534 double LinesForMetaAndDPTERow[DC__NUM_DPP__MAX];
535 double MinDPPCLKUsingSingleDPP[DC__NUM_DPP__MAX];
536 double RequiresFEC[DC__VOLTAGE_STATES + 1][DC__NUM_DPP__MAX];
537 unsigned int OutputBppPerState[DC__VOLTAGE_STATES + 1][DC__NUM_DPP__MAX];
538 double DSCDelayPerState[DC__VOLTAGE_STATES + 1][DC__NUM_DPP__MAX];
539 unsigned int Read256BlockHeightY[DC__NUM_DPP__MAX];
540 unsigned int Read256BlockWidthY[DC__NUM_DPP__MAX];
541 unsigned int Read256BlockHeightC[DC__NUM_DPP__MAX];
542 unsigned int Read256BlockWidthC[DC__NUM_DPP__MAX];
543 unsigned int ImmediateFlipBytes[DC__NUM_DPP__MAX];
544 double MaxSwathHeightY[DC__NUM_DPP__MAX];
545 double MaxSwathHeightC[DC__NUM_DPP__MAX];
546 double MinSwathHeightY[DC__NUM_DPP__MAX];
547 double MinSwathHeightC[DC__NUM_DPP__MAX];
548 double PSCL_FACTOR[DC__NUM_DPP__MAX];
549 double PSCL_FACTOR_CHROMA[DC__NUM_DPP__MAX];
550 double MaximumVStartup[DC__NUM_DPP__MAX];
551 double AlignedDCCMetaPitch[DC__NUM_DPP__MAX];
552 double AlignedYPitch[DC__NUM_DPP__MAX];
553 double AlignedCPitch[DC__NUM_DPP__MAX];
554 double MaximumSwathWidth[DC__NUM_DPP__MAX];
555 double final_flip_bw[DC__NUM_DPP__MAX];
556 double ImmediateFlipSupportedForState[DC__VOLTAGE_STATES + 1];
557
558 double WritebackLumaVExtra;
559 double WritebackChromaVExtra;
560 double WritebackRequiredDISPCLK;
561 double MaximumSwathWidthSupport;
562 double MaximumSwathWidthInDETBuffer;
563 double MaximumSwathWidthInLineBuffer;
564 double MaxDispclkRoundedDownToDFSGranularity;
565 double MaxDppclkRoundedDownToDFSGranularity;
566 double PlaneRequiredDISPCLKWithoutODMCombine;
567 double PlaneRequiredDISPCLK;
568 double TotalNumberOfActiveOTG;
569 double FECOverhead;
570 double EffectiveFECOverhead;
571 unsigned int Outbpp;
572 unsigned int OutbppDSC;
573 double TotalDSCUnitsRequired;
574 double bpp;
575 unsigned int slices;
576 double SwathWidthGranularityY;
577 double RoundedUpMaxSwathSizeBytesY;
578 double SwathWidthGranularityC;
579 double RoundedUpMaxSwathSizeBytesC;
580 double LinesInDETLuma;
581 double LinesInDETChroma;
582 double EffectiveDETLBLinesLuma;
583 double EffectiveDETLBLinesChroma;
584 double ProjectedDCFCLKDeepSleep;
585 double PDEAndMetaPTEBytesPerFrameY;
586 double PDEAndMetaPTEBytesPerFrameC;
587 unsigned int MetaRowBytesY;
588 unsigned int MetaRowBytesC;
589 unsigned int DPTEBytesPerRowC;
590 unsigned int DPTEBytesPerRowY;
591 double ExtraLatency;
592 double TimeCalc;
593 double TWait;
594 double MaximumReadBandwidthWithPrefetch;
595 double total_dcn_read_bw_with_flip;
596};
597
598#endif /* _DML2_DISPLAY_MODE_VBA_H_ */