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1* Qualcomm NAND controller
2
3Required properties:
4- compatible: must be one of the following:
5 * "qcom,ipq806x-nand" - for EBI2 NAND controller being used in IPQ806x
6 SoC and it uses ADM DMA
7 * "qcom,ipq4019-nand" - for QPIC NAND controller v1.4.0 being used in
8 IPQ4019 SoC and it uses BAM DMA
9 * "qcom,ipq8074-nand" - for QPIC NAND controller v1.5.0 being used in
10 IPQ8074 SoC and it uses BAM DMA
11
12- reg: MMIO address range
13- clocks: must contain core clock and always on clock
14- clock-names: must contain "core" for the core clock and "aon" for the
15 always on clock
16
17EBI2 specific properties:
18- dmas: DMA specifier, consisting of a phandle to the ADM DMA
19 controller node and the channel number to be used for
20 NAND. Refer to dma.txt and qcom_adm.txt for more details
21- dma-names: must be "rxtx"
22- qcom,cmd-crci: must contain the ADM command type CRCI block instance
23 number specified for the NAND controller on the given
24 platform
25- qcom,data-crci: must contain the ADM data type CRCI block instance
26 number specified for the NAND controller on the given
27 platform
28
29QPIC specific properties:
30- dmas: DMA specifier, consisting of a phandle to the BAM DMA
31 and the channel number to be used for NAND. Refer to
32 dma.txt, qcom_bam_dma.txt for more details
33- dma-names: must contain all 3 channel names : "tx", "rx", "cmd"
34- #address-cells: <1> - subnodes give the chip-select number
35- #size-cells: <0>
36
37* NAND chip-select
38
39Each controller may contain one or more subnodes to represent enabled
40chip-selects which (may) contain NAND flash chips. Their properties are as
41follows.
42
43Required properties:
44- reg: a single integer representing the chip-select
45 number (e.g., 0, 1, 2, etc.)
46- #address-cells: see partition.txt
47- #size-cells: see partition.txt
48- nand-ecc-strength: see nand.txt
49- nand-ecc-step-size: must be 512. see nand.txt for more details.
50
51Optional properties:
52- nand-bus-width: see nand.txt
53
54Each nandcs device node may optionally contain a 'partitions' sub-node, which
55further contains sub-nodes describing the flash partition mapping. See
56partition.txt for more detail.
57
58Example:
59
60nand-controller@1ac00000 {
61 compatible = "qcom,ipq806x-nand";
62 reg = <0x1ac00000 0x800>;
63
64 clocks = <&gcc EBI2_CLK>,
65 <&gcc EBI2_AON_CLK>;
66 clock-names = "core", "aon";
67
68 dmas = <&adm_dma 3>;
69 dma-names = "rxtx";
70 qcom,cmd-crci = <15>;
71 qcom,data-crci = <3>;
72
73 #address-cells = <1>;
74 #size-cells = <0>;
75
76 nand@0 {
77 reg = <0>;
78
79 nand-ecc-strength = <4>;
80 nand-ecc-step-size = <512>;
81 nand-bus-width = <8>;
82
83 partitions {
84 compatible = "fixed-partitions";
85 #address-cells = <1>;
86 #size-cells = <1>;
87
88 partition@0 {
89 label = "boot-nand";
90 reg = <0 0x58a0000>;
91 };
92
93 partition@58a0000 {
94 label = "fs-nand";
95 reg = <0x58a0000 0x4000000>;
96 };
97 };
98 };
99};
100
101nand-controller@79b0000 {
102 compatible = "qcom,ipq4019-nand";
103 reg = <0x79b0000 0x1000>;
104
105 clocks = <&gcc GCC_QPIC_CLK>,
106 <&gcc GCC_QPIC_AHB_CLK>;
107 clock-names = "core", "aon";
108
109 dmas = <&qpicbam 0>,
110 <&qpicbam 1>,
111 <&qpicbam 2>;
112 dma-names = "tx", "rx", "cmd";
113
114 #address-cells = <1>;
115 #size-cells = <0>;
116
117 nand@0 {
118 reg = <0>;
119 nand-ecc-strength = <4>;
120 nand-ecc-step-size = <512>;
121 nand-bus-width = <8>;
122
123 partitions {
124 compatible = "fixed-partitions";
125 #address-cells = <1>;
126 #size-cells = <1>;
127
128 partition@0 {
129 label = "boot-nand";
130 reg = <0 0x58a0000>;
131 };
132
133 partition@58a0000 {
134 label = "fs-nand";
135 reg = <0x58a0000 0x4000000>;
136 };
137 };
138 };
139};