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1/* include/linux/amba/pl080.h
2 *
3 * Copyright 2008 Openmoko, Inc.
4 * Copyright 2008 Simtec Electronics
5 * http://armlinux.simtec.co.uk/
6 * Ben Dooks <ben@simtec.co.uk>
7 *
8 * ARM PrimeCell PL080 DMA controller
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
13*/
14
15/* Note, there are some Samsung updates to this controller block which
16 * make it not entierly compatible with the PL080 specification from
17 * ARM. When in doubt, check the Samsung documentation first.
18 *
19 * The Samsung defines are PL080S, and add an extra control register,
20 * the ability to move more than 2^11 counts of data and some extra
21 * OneNAND features.
22*/
23
24#ifndef ASM_PL080_H
25#define ASM_PL080_H
26
27#define PL080_INT_STATUS (0x00)
28#define PL080_TC_STATUS (0x04)
29#define PL080_TC_CLEAR (0x08)
30#define PL080_ERR_STATUS (0x0C)
31#define PL080_ERR_CLEAR (0x10)
32#define PL080_RAW_TC_STATUS (0x14)
33#define PL080_RAW_ERR_STATUS (0x18)
34#define PL080_EN_CHAN (0x1c)
35#define PL080_SOFT_BREQ (0x20)
36#define PL080_SOFT_SREQ (0x24)
37#define PL080_SOFT_LBREQ (0x28)
38#define PL080_SOFT_LSREQ (0x2C)
39
40#define PL080_CONFIG (0x30)
41#define PL080_CONFIG_M2_BE BIT(2)
42#define PL080_CONFIG_M1_BE BIT(1)
43#define PL080_CONFIG_ENABLE BIT(0)
44
45#define PL080_SYNC (0x34)
46
47/* The Faraday Technology FTDMAC020 variant registers */
48#define FTDMAC020_CH_BUSY (0x20)
49/* Identical to PL080_CONFIG */
50#define FTDMAC020_CSR (0x24)
51/* Identical to PL080_SYNC */
52#define FTDMAC020_SYNC (0x2C)
53#define FTDMAC020_REVISION (0x30)
54#define FTDMAC020_FEATURE (0x34)
55
56/* Per channel configuration registers */
57#define PL080_Cx_BASE(x) ((0x100 + (x * 0x20)))
58#define PL080_CH_SRC_ADDR (0x00)
59#define PL080_CH_DST_ADDR (0x04)
60#define PL080_CH_LLI (0x08)
61#define PL080_CH_CONTROL (0x0C)
62#define PL080_CH_CONFIG (0x10)
63#define PL080S_CH_CONTROL2 (0x10)
64#define PL080S_CH_CONFIG (0x14)
65/* The Faraday FTDMAC020 derivative shuffles the registers around */
66#define FTDMAC020_CH_CSR (0x00)
67#define FTDMAC020_CH_CFG (0x04)
68#define FTDMAC020_CH_SRC_ADDR (0x08)
69#define FTDMAC020_CH_DST_ADDR (0x0C)
70#define FTDMAC020_CH_LLP (0x10)
71#define FTDMAC020_CH_SIZE (0x14)
72
73#define PL080_LLI_ADDR_MASK GENMASK(31, 2)
74#define PL080_LLI_ADDR_SHIFT (2)
75#define PL080_LLI_LM_AHB2 BIT(0)
76
77#define PL080_CONTROL_TC_IRQ_EN BIT(31)
78#define PL080_CONTROL_PROT_MASK GENMASK(30, 28)
79#define PL080_CONTROL_PROT_SHIFT (28)
80#define PL080_CONTROL_PROT_CACHE BIT(30)
81#define PL080_CONTROL_PROT_BUFF BIT(29)
82#define PL080_CONTROL_PROT_SYS BIT(28)
83#define PL080_CONTROL_DST_INCR BIT(27)
84#define PL080_CONTROL_SRC_INCR BIT(26)
85#define PL080_CONTROL_DST_AHB2 BIT(25)
86#define PL080_CONTROL_SRC_AHB2 BIT(24)
87#define PL080_CONTROL_DWIDTH_MASK GENMASK(23, 21)
88#define PL080_CONTROL_DWIDTH_SHIFT (21)
89#define PL080_CONTROL_SWIDTH_MASK GENMASK(20, 18)
90#define PL080_CONTROL_SWIDTH_SHIFT (18)
91#define PL080_CONTROL_DB_SIZE_MASK GENMASK(17, 15)
92#define PL080_CONTROL_DB_SIZE_SHIFT (15)
93#define PL080_CONTROL_SB_SIZE_MASK GENMASK(14, 12)
94#define PL080_CONTROL_SB_SIZE_SHIFT (12)
95#define PL080_CONTROL_TRANSFER_SIZE_MASK GENMASK(11, 0)
96#define PL080S_CONTROL_TRANSFER_SIZE_MASK GENMASK(24, 0)
97#define PL080_CONTROL_TRANSFER_SIZE_SHIFT (0)
98
99#define PL080_BSIZE_1 (0x0)
100#define PL080_BSIZE_4 (0x1)
101#define PL080_BSIZE_8 (0x2)
102#define PL080_BSIZE_16 (0x3)
103#define PL080_BSIZE_32 (0x4)
104#define PL080_BSIZE_64 (0x5)
105#define PL080_BSIZE_128 (0x6)
106#define PL080_BSIZE_256 (0x7)
107
108#define PL080_WIDTH_8BIT (0x0)
109#define PL080_WIDTH_16BIT (0x1)
110#define PL080_WIDTH_32BIT (0x2)
111
112#define PL080N_CONFIG_ITPROT BIT(20)
113#define PL080N_CONFIG_SECPROT BIT(19)
114#define PL080_CONFIG_HALT BIT(18)
115#define PL080_CONFIG_ACTIVE BIT(17) /* RO */
116#define PL080_CONFIG_LOCK BIT(16)
117#define PL080_CONFIG_TC_IRQ_MASK BIT(15)
118#define PL080_CONFIG_ERR_IRQ_MASK BIT(14)
119#define PL080_CONFIG_FLOW_CONTROL_MASK GENMASK(13, 11)
120#define PL080_CONFIG_FLOW_CONTROL_SHIFT (11)
121#define PL080_CONFIG_DST_SEL_MASK GENMASK(9, 6)
122#define PL080_CONFIG_DST_SEL_SHIFT (6)
123#define PL080_CONFIG_SRC_SEL_MASK GENMASK(4, 1)
124#define PL080_CONFIG_SRC_SEL_SHIFT (1)
125#define PL080_CONFIG_ENABLE BIT(0)
126
127#define PL080_FLOW_MEM2MEM (0x0)
128#define PL080_FLOW_MEM2PER (0x1)
129#define PL080_FLOW_PER2MEM (0x2)
130#define PL080_FLOW_SRC2DST (0x3)
131#define PL080_FLOW_SRC2DST_DST (0x4)
132#define PL080_FLOW_MEM2PER_PER (0x5)
133#define PL080_FLOW_PER2MEM_PER (0x6)
134#define PL080_FLOW_SRC2DST_SRC (0x7)
135
136#define FTDMAC020_CH_CSR_TC_MSK BIT(31)
137/* Later versions have a threshold in bits 24..26, */
138#define FTDMAC020_CH_CSR_FIFOTH_MSK GENMASK(26, 24)
139#define FTDMAC020_CH_CSR_FIFOTH_SHIFT (24)
140#define FTDMAC020_CH_CSR_CHPR1_MSK GENMASK(23, 22)
141#define FTDMAC020_CH_CSR_PROT3 BIT(21)
142#define FTDMAC020_CH_CSR_PROT2 BIT(20)
143#define FTDMAC020_CH_CSR_PROT1 BIT(19)
144#define FTDMAC020_CH_CSR_SRC_SIZE_MSK GENMASK(18, 16)
145#define FTDMAC020_CH_CSR_SRC_SIZE_SHIFT (16)
146#define FTDMAC020_CH_CSR_ABT BIT(15)
147#define FTDMAC020_CH_CSR_SRC_WIDTH_MSK GENMASK(13, 11)
148#define FTDMAC020_CH_CSR_SRC_WIDTH_SHIFT (11)
149#define FTDMAC020_CH_CSR_DST_WIDTH_MSK GENMASK(10, 8)
150#define FTDMAC020_CH_CSR_DST_WIDTH_SHIFT (8)
151#define FTDMAC020_CH_CSR_MODE BIT(7)
152/* 00 = increase, 01 = decrease, 10 = fix */
153#define FTDMAC020_CH_CSR_SRCAD_CTL_MSK GENMASK(6, 5)
154#define FTDMAC020_CH_CSR_SRCAD_CTL_SHIFT (5)
155#define FTDMAC020_CH_CSR_DSTAD_CTL_MSK GENMASK(4, 3)
156#define FTDMAC020_CH_CSR_DSTAD_CTL_SHIFT (3)
157#define FTDMAC020_CH_CSR_SRC_SEL BIT(2)
158#define FTDMAC020_CH_CSR_DST_SEL BIT(1)
159#define FTDMAC020_CH_CSR_EN BIT(0)
160
161/* FIFO threshold setting */
162#define FTDMAC020_CH_CSR_FIFOTH_1 (0x0)
163#define FTDMAC020_CH_CSR_FIFOTH_2 (0x1)
164#define FTDMAC020_CH_CSR_FIFOTH_4 (0x2)
165#define FTDMAC020_CH_CSR_FIFOTH_8 (0x3)
166#define FTDMAC020_CH_CSR_FIFOTH_16 (0x4)
167/* The FTDMAC020 supports 64bit wide transfers */
168#define FTDMAC020_WIDTH_64BIT (0x3)
169/* Address can be increased, decreased or fixed */
170#define FTDMAC020_CH_CSR_SRCAD_CTL_INC (0x0)
171#define FTDMAC020_CH_CSR_SRCAD_CTL_DEC (0x1)
172#define FTDMAC020_CH_CSR_SRCAD_CTL_FIXED (0x2)
173
174#define FTDMAC020_CH_CFG_LLP_CNT_MASK GENMASK(19, 16)
175#define FTDMAC020_CH_CFG_LLP_CNT_SHIFT (16)
176#define FTDMAC020_CH_CFG_BUSY BIT(8)
177#define FTDMAC020_CH_CFG_INT_ABT_MASK BIT(2)
178#define FTDMAC020_CH_CFG_INT_ERR_MASK BIT(1)
179#define FTDMAC020_CH_CFG_INT_TC_MASK BIT(0)
180
181/* Inside the LLIs, the applicable CSR fields are mapped differently */
182#define FTDMAC020_LLI_TC_MSK BIT(28)
183#define FTDMAC020_LLI_SRC_WIDTH_MSK GENMASK(27, 25)
184#define FTDMAC020_LLI_SRC_WIDTH_SHIFT (25)
185#define FTDMAC020_LLI_DST_WIDTH_MSK GENMASK(24, 22)
186#define FTDMAC020_LLI_DST_WIDTH_SHIFT (22)
187#define FTDMAC020_LLI_SRCAD_CTL_MSK GENMASK(21, 20)
188#define FTDMAC020_LLI_SRCAD_CTL_SHIFT (20)
189#define FTDMAC020_LLI_DSTAD_CTL_MSK GENMASK(19, 18)
190#define FTDMAC020_LLI_DSTAD_CTL_SHIFT (18)
191#define FTDMAC020_LLI_SRC_SEL BIT(17)
192#define FTDMAC020_LLI_DST_SEL BIT(16)
193#define FTDMAC020_LLI_TRANSFER_SIZE_MASK GENMASK(11, 0)
194#define FTDMAC020_LLI_TRANSFER_SIZE_SHIFT (0)
195
196#define FTDMAC020_CFG_LLP_CNT_MASK GENMASK(19, 16)
197#define FTDMAC020_CFG_LLP_CNT_SHIFT (16)
198#define FTDMAC020_CFG_BUSY BIT(8)
199#define FTDMAC020_CFG_INT_ABT_MSK BIT(2)
200#define FTDMAC020_CFG_INT_ERR_MSK BIT(1)
201#define FTDMAC020_CFG_INT_TC_MSK BIT(0)
202
203/* DMA linked list chain structure */
204
205struct pl080_lli {
206 u32 src_addr;
207 u32 dst_addr;
208 u32 next_lli;
209 u32 control0;
210};
211
212struct pl080s_lli {
213 u32 src_addr;
214 u32 dst_addr;
215 u32 next_lli;
216 u32 control0;
217 u32 control1;
218};
219
220#endif /* ASM_PL080_H */