tjh.dev
Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
1/*
2 * Copyright (c) 1996, 2003 VIA Networking Technologies, Inc.
3 * All rights reserved.
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation; either version 2 of the License, or
8 * (at your option) any later version.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 * File: mac.h
16 *
17 * Purpose: MAC routines
18 *
19 * Author: Tevin Chen
20 *
21 * Date: May 21, 1996
22 *
23 * Revision History:
24 * 07-01-2003 Bryan YC Fan: Re-write codes to support VT3253 spec.
25 * 08-25-2003 Kyle Hsu: Porting MAC functions from sim53.
26 * 09-03-2003 Bryan YC Fan: Add MACvDisableProtectMD & MACvEnableProtectMD
27 */
28
29#ifndef __MAC_H__
30#define __MAC_H__
31
32#include "tmacro.h"
33#include "upc.h"
34
35/*--------------------- Export Definitions -------------------------*/
36/* Registers in the MAC */
37#define MAC_MAX_CONTEXT_SIZE_PAGE0 256
38#define MAC_MAX_CONTEXT_SIZE_PAGE1 128
39
40/* Registers not related to 802.11b */
41#define MAC_REG_BCFG0 0x00
42#define MAC_REG_BCFG1 0x01
43#define MAC_REG_FCR0 0x02
44#define MAC_REG_FCR1 0x03
45#define MAC_REG_BISTCMD 0x04
46#define MAC_REG_BISTSR0 0x05
47#define MAC_REG_BISTSR1 0x06
48#define MAC_REG_BISTSR2 0x07
49#define MAC_REG_I2MCSR 0x08
50#define MAC_REG_I2MTGID 0x09
51#define MAC_REG_I2MTGAD 0x0A
52#define MAC_REG_I2MCFG 0x0B
53#define MAC_REG_I2MDIPT 0x0C
54#define MAC_REG_I2MDOPT 0x0E
55#define MAC_REG_PMC0 0x10
56#define MAC_REG_PMC1 0x11
57#define MAC_REG_STICKHW 0x12
58#define MAC_REG_LOCALID 0x14
59#define MAC_REG_TESTCFG 0x15
60#define MAC_REG_JUMPER0 0x16
61#define MAC_REG_JUMPER1 0x17
62#define MAC_REG_TMCTL0 0x18
63#define MAC_REG_TMCTL1 0x19
64#define MAC_REG_TMDATA0 0x1C
65
66/* MAC Parameter related */
67#define MAC_REG_LRT 0x20
68#define MAC_REG_SRT 0x21
69#define MAC_REG_SIFS 0x22
70#define MAC_REG_DIFS 0x23
71#define MAC_REG_EIFS 0x24
72#define MAC_REG_SLOT 0x25
73#define MAC_REG_BI 0x26
74#define MAC_REG_CWMAXMIN0 0x28
75#define MAC_REG_LINKOFFTOTM 0x2A
76#define MAC_REG_SWTMOT 0x2B
77#define MAC_REG_MIBCNTR 0x2C
78#define MAC_REG_RTSOKCNT 0x2C
79#define MAC_REG_RTSFAILCNT 0x2D
80#define MAC_REG_ACKFAILCNT 0x2E
81#define MAC_REG_FCSERRCNT 0x2F
82
83/* TSF Related */
84#define MAC_REG_TSFCNTR 0x30
85#define MAC_REG_NEXTTBTT 0x38
86#define MAC_REG_TSFOFST 0x40
87#define MAC_REG_TFTCTL 0x48
88
89/* WMAC Control/Status Related */
90#define MAC_REG_ENCFG 0x4C
91#define MAC_REG_PAGE1SEL 0x4F
92#define MAC_REG_CFG 0x50
93#define MAC_REG_TEST 0x52
94#define MAC_REG_HOSTCR 0x54
95#define MAC_REG_MACCR 0x55
96#define MAC_REG_RCR 0x56
97#define MAC_REG_TCR 0x57
98#define MAC_REG_IMR 0x58
99#define MAC_REG_ISR 0x5C
100
101/* Power Saving Related */
102#define MAC_REG_PSCFG 0x60
103#define MAC_REG_PSCTL 0x61
104#define MAC_REG_PSPWRSIG 0x62
105#define MAC_REG_BBCR13 0x63
106#define MAC_REG_AIDATIM 0x64
107#define MAC_REG_PWBT 0x66
108#define MAC_REG_WAKEOKTMR 0x68
109#define MAC_REG_CALTMR 0x69
110#define MAC_REG_SYNSPACCNT 0x6A
111#define MAC_REG_WAKSYNOPT 0x6B
112
113/* Baseband/IF Control Group */
114#define MAC_REG_BBREGCTL 0x6C
115#define MAC_REG_CHANNEL 0x6D
116#define MAC_REG_BBREGADR 0x6E
117#define MAC_REG_BBREGDATA 0x6F
118#define MAC_REG_IFREGCTL 0x70
119#define MAC_REG_IFDATA 0x71
120#define MAC_REG_ITRTMSET 0x74
121#define MAC_REG_PAPEDELAY 0x77
122#define MAC_REG_SOFTPWRCTL 0x78
123#define MAC_REG_GPIOCTL0 0x7A
124#define MAC_REG_GPIOCTL1 0x7B
125
126/* MAC DMA Related Group */
127#define MAC_REG_TXDMACTL0 0x7C
128#define MAC_REG_TXDMAPTR0 0x80
129#define MAC_REG_AC0DMACTL 0x84
130#define MAC_REG_AC0DMAPTR 0x88
131#define MAC_REG_BCNDMACTL 0x8C
132#define MAC_REG_BCNDMAPTR 0x90
133#define MAC_REG_RXDMACTL0 0x94
134#define MAC_REG_RXDMAPTR0 0x98
135#define MAC_REG_RXDMACTL1 0x9C
136#define MAC_REG_RXDMAPTR1 0xA0
137#define MAC_REG_SYNCDMACTL 0xA4
138#define MAC_REG_SYNCDMAPTR 0xA8
139#define MAC_REG_ATIMDMACTL 0xAC
140#define MAC_REG_ATIMDMAPTR 0xB0
141
142/* MiscFF PIO related */
143#define MAC_REG_MISCFFNDEX 0xB4
144#define MAC_REG_MISCFFCTL 0xB6
145#define MAC_REG_MISCFFDATA 0xB8
146
147/* Extend SW Timer */
148#define MAC_REG_TMDATA1 0xBC
149
150/* WOW Related Group */
151#define MAC_REG_WAKEUPEN0 0xC0
152#define MAC_REG_WAKEUPEN1 0xC1
153#define MAC_REG_WAKEUPSR0 0xC2
154#define MAC_REG_WAKEUPSR1 0xC3
155#define MAC_REG_WAKE128_0 0xC4
156#define MAC_REG_WAKE128_1 0xD4
157#define MAC_REG_WAKE128_2 0xE4
158#define MAC_REG_WAKE128_3 0xF4
159
160/************** Page 1 ******************/
161#define MAC_REG_CRC_128_0 0x04
162#define MAC_REG_CRC_128_1 0x06
163#define MAC_REG_CRC_128_2 0x08
164#define MAC_REG_CRC_128_3 0x0A
165
166/* MAC Configuration Group */
167#define MAC_REG_PAR0 0x0C
168#define MAC_REG_PAR4 0x10
169#define MAC_REG_BSSID0 0x14
170#define MAC_REG_BSSID4 0x18
171#define MAC_REG_MAR0 0x1C
172#define MAC_REG_MAR4 0x20
173
174/* MAC RSPPKT INFO Group */
175#define MAC_REG_RSPINF_B_1 0x24
176#define MAC_REG_RSPINF_B_2 0x28
177#define MAC_REG_RSPINF_B_5 0x2C
178#define MAC_REG_RSPINF_B_11 0x30
179#define MAC_REG_RSPINF_A_6 0x34
180#define MAC_REG_RSPINF_A_9 0x36
181#define MAC_REG_RSPINF_A_12 0x38
182#define MAC_REG_RSPINF_A_18 0x3A
183#define MAC_REG_RSPINF_A_24 0x3C
184#define MAC_REG_RSPINF_A_36 0x3E
185#define MAC_REG_RSPINF_A_48 0x40
186#define MAC_REG_RSPINF_A_54 0x42
187#define MAC_REG_RSPINF_A_72 0x44
188
189/* 802.11h relative */
190#define MAC_REG_QUIETINIT 0x60
191#define MAC_REG_QUIETGAP 0x62
192#define MAC_REG_QUIETDUR 0x64
193#define MAC_REG_MSRCTL 0x66
194#define MAC_REG_MSRBBSTS 0x67
195#define MAC_REG_MSRSTART 0x68
196#define MAC_REG_MSRDURATION 0x70
197#define MAC_REG_CCAFRACTION 0x72
198#define MAC_REG_PWRCCK 0x73
199#define MAC_REG_PWROFDM 0x7C
200
201/* Bits in the BCFG0 register */
202#define BCFG0_PERROFF 0x40
203#define BCFG0_MRDMDIS 0x20
204#define BCFG0_MRDLDIS 0x10
205#define BCFG0_MWMEN 0x08
206#define BCFG0_VSERREN 0x02
207#define BCFG0_LATMEN 0x01
208
209/* Bits in the BCFG1 register */
210#define BCFG1_CFUNOPT 0x80
211#define BCFG1_CREQOPT 0x40
212#define BCFG1_DMA8 0x10
213#define BCFG1_ARBITOPT 0x08
214#define BCFG1_PCIMEN 0x04
215#define BCFG1_MIOEN 0x02
216#define BCFG1_CISDLYEN 0x01
217
218/* Bits in RAMBIST registers */
219#define BISTCMD_TSTPAT5 0x00
220#define BISTCMD_TSTPATA 0x80
221#define BISTCMD_TSTERR 0x20
222#define BISTCMD_TSTPATF 0x18
223#define BISTCMD_TSTPAT0 0x10
224#define BISTCMD_TSTMODE 0x04
225#define BISTCMD_TSTITTX 0x03
226#define BISTCMD_TSTATRX 0x02
227#define BISTCMD_TSTATTX 0x01
228#define BISTCMD_TSTRX 0x00
229#define BISTSR0_BISTGO 0x01
230#define BISTSR1_TSTSR 0x01
231#define BISTSR2_CMDPRTEN 0x02
232#define BISTSR2_RAMTSTEN 0x01
233
234/* Bits in the I2MCFG EEPROM register */
235#define I2MCFG_BOUNDCTL 0x80
236#define I2MCFG_WAITCTL 0x20
237#define I2MCFG_SCLOECTL 0x10
238#define I2MCFG_WBUSYCTL 0x08
239#define I2MCFG_NORETRY 0x04
240#define I2MCFG_I2MLDSEQ 0x02
241#define I2MCFG_I2CMFAST 0x01
242
243/* Bits in the I2MCSR EEPROM register */
244#define I2MCSR_EEMW 0x80
245#define I2MCSR_EEMR 0x40
246#define I2MCSR_AUTOLD 0x08
247#define I2MCSR_NACK 0x02
248#define I2MCSR_DONE 0x01
249
250/* Bits in the PMC1 register */
251#define SPS_RST 0x80
252#define PCISTIKY 0x40
253#define PME_OVR 0x02
254
255/* Bits in the STICKYHW register */
256#define STICKHW_DS1_SHADOW 0x02
257#define STICKHW_DS0_SHADOW 0x01
258
259/* Bits in the TMCTL register */
260#define TMCTL_TSUSP 0x04
261#define TMCTL_TMD 0x02
262#define TMCTL_TE 0x01
263
264/* Bits in the TFTCTL register */
265#define TFTCTL_HWUTSF 0x80
266#define TFTCTL_TBTTSYNC 0x40
267#define TFTCTL_HWUTSFEN 0x20
268#define TFTCTL_TSFCNTRRD 0x10
269#define TFTCTL_TBTTSYNCEN 0x08
270#define TFTCTL_TSFSYNCEN 0x04
271#define TFTCTL_TSFCNTRST 0x02
272#define TFTCTL_TSFCNTREN 0x01
273
274/* Bits in the EnhanceCFG register */
275#define EnCFG_BarkerPream 0x00020000
276#define EnCFG_NXTBTTCFPSTR 0x00010000
277#define EnCFG_BcnSusClr 0x00000200
278#define EnCFG_BcnSusInd 0x00000100
279#define EnCFG_CFP_ProtectEn 0x00000040
280#define EnCFG_ProtectMd 0x00000020
281#define EnCFG_HwParCFP 0x00000010
282#define EnCFG_CFNULRSP 0x00000004
283#define EnCFG_BBType_MASK 0x00000003
284#define EnCFG_BBType_g 0x00000002
285#define EnCFG_BBType_b 0x00000001
286#define EnCFG_BBType_a 0x00000000
287
288/* Bits in the Page1Sel register */
289#define PAGE1_SEL 0x01
290
291/* Bits in the CFG register */
292#define CFG_TKIPOPT 0x80
293#define CFG_RXDMAOPT 0x40
294#define CFG_TMOT_SW 0x20
295#define CFG_TMOT_HWLONG 0x10
296#define CFG_TMOT_HW 0x00
297#define CFG_CFPENDOPT 0x08
298#define CFG_BCNSUSEN 0x04
299#define CFG_NOTXTIMEOUT 0x02
300#define CFG_NOBUFOPT 0x01
301
302/* Bits in the TEST register */
303#define TEST_LBEXT 0x80
304#define TEST_LBINT 0x40
305#define TEST_LBNONE 0x00
306#define TEST_SOFTINT 0x20
307#define TEST_CONTTX 0x10
308#define TEST_TXPE 0x08
309#define TEST_NAVDIS 0x04
310#define TEST_NOCTS 0x02
311#define TEST_NOACK 0x01
312
313/* Bits in the HOSTCR register */
314#define HOSTCR_TXONST 0x80
315#define HOSTCR_RXONST 0x40
316#define HOSTCR_ADHOC 0x20 /* Network Type 1 = Ad-hoc */
317#define HOSTCR_AP 0x10 /* Port Type 1 = AP */
318#define HOSTCR_TXON 0x08 /* 0000 1000 */
319#define HOSTCR_RXON 0x04 /* 0000 0100 */
320#define HOSTCR_MACEN 0x02 /* 0000 0010 */
321#define HOSTCR_SOFTRST 0x01 /* 0000 0001 */
322
323/* Bits in the MACCR register */
324#define MACCR_SYNCFLUSHOK 0x04
325#define MACCR_SYNCFLUSH 0x02
326#define MACCR_CLRNAV 0x01
327
328/* Bits in the MAC_REG_GPIOCTL0 register */
329#define LED_ACTSET 0x01
330#define LED_RFOFF 0x02
331#define LED_NOCONNECT 0x04
332
333/* Bits in the RCR register */
334#define RCR_SSID 0x80
335#define RCR_RXALLTYPE 0x40
336#define RCR_UNICAST 0x20
337#define RCR_BROADCAST 0x10
338#define RCR_MULTICAST 0x08
339#define RCR_WPAERR 0x04
340#define RCR_ERRCRC 0x02
341#define RCR_BSSID 0x01
342
343/* Bits in the TCR register */
344#define TCR_SYNCDCFOPT 0x02
345#define TCR_AUTOBCNTX 0x01 /* Beacon automatically transmit enable */
346
347/* Bits in the IMR register */
348#define IMR_MEASURESTART 0x80000000
349#define IMR_QUIETSTART 0x20000000
350#define IMR_RADARDETECT 0x10000000
351#define IMR_MEASUREEND 0x08000000
352#define IMR_SOFTTIMER1 0x00200000
353#define IMR_RXDMA1 0x00001000 /* 0000 0000 0001 0000 0000 0000 */
354#define IMR_RXNOBUF 0x00000800
355#define IMR_MIBNEARFULL 0x00000400
356#define IMR_SOFTINT 0x00000200
357#define IMR_FETALERR 0x00000100
358#define IMR_WATCHDOG 0x00000080
359#define IMR_SOFTTIMER 0x00000040
360#define IMR_GPIO 0x00000020
361#define IMR_TBTT 0x00000010
362#define IMR_RXDMA0 0x00000008
363#define IMR_BNTX 0x00000004
364#define IMR_AC0DMA 0x00000002
365#define IMR_TXDMA0 0x00000001
366
367/* Bits in the ISR register */
368#define ISR_MEASURESTART 0x80000000
369#define ISR_QUIETSTART 0x20000000
370#define ISR_RADARDETECT 0x10000000
371#define ISR_MEASUREEND 0x08000000
372#define ISR_SOFTTIMER1 0x00200000
373#define ISR_RXDMA1 0x00001000 /* 0000 0000 0001 0000 0000 0000 */
374#define ISR_RXNOBUF 0x00000800 /* 0000 0000 0000 1000 0000 0000 */
375#define ISR_MIBNEARFULL 0x00000400 /* 0000 0000 0000 0100 0000 0000 */
376#define ISR_SOFTINT 0x00000200
377#define ISR_FETALERR 0x00000100
378#define ISR_WATCHDOG 0x00000080
379#define ISR_SOFTTIMER 0x00000040
380#define ISR_GPIO 0x00000020
381#define ISR_TBTT 0x00000010
382#define ISR_RXDMA0 0x00000008
383#define ISR_BNTX 0x00000004
384#define ISR_AC0DMA 0x00000002
385#define ISR_TXDMA0 0x00000001
386
387/* Bits in the PSCFG register */
388#define PSCFG_PHILIPMD 0x40
389#define PSCFG_WAKECALEN 0x20
390#define PSCFG_WAKETMREN 0x10
391#define PSCFG_BBPSPROG 0x08
392#define PSCFG_WAKESYN 0x04
393#define PSCFG_SLEEPSYN 0x02
394#define PSCFG_AUTOSLEEP 0x01
395
396/* Bits in the PSCTL register */
397#define PSCTL_WAKEDONE 0x20
398#define PSCTL_PS 0x10
399#define PSCTL_GO2DOZE 0x08
400#define PSCTL_LNBCN 0x04
401#define PSCTL_ALBCN 0x02
402#define PSCTL_PSEN 0x01
403
404/* Bits in the PSPWSIG register */
405#define PSSIG_WPE3 0x80
406#define PSSIG_WPE2 0x40
407#define PSSIG_WPE1 0x20
408#define PSSIG_WRADIOPE 0x10
409#define PSSIG_SPE3 0x08
410#define PSSIG_SPE2 0x04
411#define PSSIG_SPE1 0x02
412#define PSSIG_SRADIOPE 0x01
413
414/* Bits in the BBREGCTL register */
415#define BBREGCTL_DONE 0x04
416#define BBREGCTL_REGR 0x02
417#define BBREGCTL_REGW 0x01
418
419/* Bits in the IFREGCTL register */
420#define IFREGCTL_DONE 0x04
421#define IFREGCTL_IFRF 0x02
422#define IFREGCTL_REGW 0x01
423
424/* Bits in the SOFTPWRCTL register */
425#define SOFTPWRCTL_RFLEOPT 0x0800
426#define SOFTPWRCTL_TXPEINV 0x0200
427#define SOFTPWRCTL_SWPECTI 0x0100
428#define SOFTPWRCTL_SWPAPE 0x0020
429#define SOFTPWRCTL_SWCALEN 0x0010
430#define SOFTPWRCTL_SWRADIO_PE 0x0008
431#define SOFTPWRCTL_SWPE2 0x0004
432#define SOFTPWRCTL_SWPE1 0x0002
433#define SOFTPWRCTL_SWPE3 0x0001
434
435/* Bits in the GPIOCTL1 register */
436#define GPIO1_DATA1 0x20
437#define GPIO1_MD1 0x10
438#define GPIO1_DATA0 0x02
439#define GPIO1_MD0 0x01
440
441/* Bits in the DMACTL register */
442#define DMACTL_CLRRUN 0x00080000
443#define DMACTL_RUN 0x00000008
444#define DMACTL_WAKE 0x00000004
445#define DMACTL_DEAD 0x00000002
446#define DMACTL_ACTIVE 0x00000001
447
448/* Bits in the RXDMACTL0 register */
449#define RX_PERPKT 0x00000100
450#define RX_PERPKTCLR 0x01000000
451
452/* Bits in the BCNDMACTL register */
453#define BEACON_READY 0x01
454
455/* Bits in the MISCFFCTL register */
456#define MISCFFCTL_WRITE 0x0001
457
458/* Bits in WAKEUPEN0 */
459#define WAKEUPEN0_DIRPKT 0x10
460#define WAKEUPEN0_LINKOFF 0x08
461#define WAKEUPEN0_ATIMEN 0x04
462#define WAKEUPEN0_TIMEN 0x02
463#define WAKEUPEN0_MAGICEN 0x01
464
465/* Bits in WAKEUPEN1 */
466#define WAKEUPEN1_128_3 0x08
467#define WAKEUPEN1_128_2 0x04
468#define WAKEUPEN1_128_1 0x02
469#define WAKEUPEN1_128_0 0x01
470
471/* Bits in WAKEUPSR0 */
472#define WAKEUPSR0_DIRPKT 0x10
473#define WAKEUPSR0_LINKOFF 0x08
474#define WAKEUPSR0_ATIMEN 0x04
475#define WAKEUPSR0_TIMEN 0x02
476#define WAKEUPSR0_MAGICEN 0x01
477
478/* Bits in WAKEUPSR1 */
479#define WAKEUPSR1_128_3 0x08
480#define WAKEUPSR1_128_2 0x04
481#define WAKEUPSR1_128_1 0x02
482#define WAKEUPSR1_128_0 0x01
483
484/* Bits in the MAC_REG_GPIOCTL register */
485#define GPIO0_MD 0x01
486#define GPIO0_DATA 0x02
487#define GPIO0_INTMD 0x04
488#define GPIO1_MD 0x10
489#define GPIO1_DATA 0x20
490
491/* Bits in the MSRCTL register */
492#define MSRCTL_FINISH 0x80
493#define MSRCTL_READY 0x40
494#define MSRCTL_RADARDETECT 0x20
495#define MSRCTL_EN 0x10
496#define MSRCTL_QUIETTXCHK 0x08
497#define MSRCTL_QUIETRPT 0x04
498#define MSRCTL_QUIETINT 0x02
499#define MSRCTL_QUIETEN 0x01
500
501/* Bits in the MSRCTL1 register */
502#define MSRCTL1_TXPWR 0x08
503#define MSRCTL1_CSAPAREN 0x04
504#define MSRCTL1_TXPAUSE 0x01
505
506/* Loopback mode */
507#define MAC_LB_EXT 0x02
508#define MAC_LB_INTERNAL 0x01
509#define MAC_LB_NONE 0x00
510
511#define Default_BI 0x200
512
513/* MiscFIFO Offset */
514#define MISCFIFO_KEYETRY0 32
515#define MISCFIFO_KEYENTRYSIZE 22
516#define MISCFIFO_SYNINFO_IDX 10
517#define MISCFIFO_SYNDATA_IDX 11
518#define MISCFIFO_SYNDATASIZE 21
519
520/* enabled mask value of irq */
521#define IMR_MASK_VALUE (IMR_SOFTTIMER1 | \
522 IMR_RXDMA1 | \
523 IMR_RXNOBUF | \
524 IMR_MIBNEARFULL | \
525 IMR_SOFTINT | \
526 IMR_FETALERR | \
527 IMR_WATCHDOG | \
528 IMR_SOFTTIMER | \
529 IMR_GPIO | \
530 IMR_TBTT | \
531 IMR_RXDMA0 | \
532 IMR_BNTX | \
533 IMR_AC0DMA | \
534 IMR_TXDMA0)
535
536/* max time out delay time */
537#define W_MAX_TIMEOUT 0xFFF0U
538
539/* wait time within loop */
540#define CB_DELAY_LOOP_WAIT 10 /* 10ms */
541
542/* revision id */
543#define REV_ID_VT3253_A0 0x00
544#define REV_ID_VT3253_A1 0x01
545#define REV_ID_VT3253_B0 0x08
546#define REV_ID_VT3253_B1 0x09
547
548/*--------------------- Export Types ------------------------------*/
549
550/*--------------------- Export Macros ------------------------------*/
551
552#define MACvRegBitsOn(iobase, byRegOfs, byBits) \
553do { \
554 unsigned char byData; \
555 VNSvInPortB(iobase + byRegOfs, &byData); \
556 VNSvOutPortB(iobase + byRegOfs, byData | (byBits)); \
557} while (0)
558
559#define MACvWordRegBitsOn(iobase, byRegOfs, wBits) \
560do { \
561 unsigned short wData; \
562 VNSvInPortW(iobase + byRegOfs, &wData); \
563 VNSvOutPortW(iobase + byRegOfs, wData | (wBits)); \
564} while (0)
565
566#define MACvDWordRegBitsOn(iobase, byRegOfs, dwBits) \
567do { \
568 unsigned long dwData; \
569 VNSvInPortD(iobase + byRegOfs, &dwData); \
570 VNSvOutPortD(iobase + byRegOfs, dwData | (dwBits)); \
571} while (0)
572
573#define MACvRegBitsOnEx(iobase, byRegOfs, byMask, byBits) \
574do { \
575 unsigned char byData; \
576 VNSvInPortB(iobase + byRegOfs, &byData); \
577 byData &= byMask; \
578 VNSvOutPortB(iobase + byRegOfs, byData | (byBits)); \
579} while (0)
580
581#define MACvRegBitsOff(iobase, byRegOfs, byBits) \
582do { \
583 unsigned char byData; \
584 VNSvInPortB(iobase + byRegOfs, &byData); \
585 VNSvOutPortB(iobase + byRegOfs, byData & ~(byBits)); \
586} while (0)
587
588#define MACvWordRegBitsOff(iobase, byRegOfs, wBits) \
589do { \
590 unsigned short wData; \
591 VNSvInPortW(iobase + byRegOfs, &wData); \
592 VNSvOutPortW(iobase + byRegOfs, wData & ~(wBits)); \
593} while (0)
594
595#define MACvDWordRegBitsOff(iobase, byRegOfs, dwBits) \
596do { \
597 unsigned long dwData; \
598 VNSvInPortD(iobase + byRegOfs, &dwData); \
599 VNSvOutPortD(iobase + byRegOfs, dwData & ~(dwBits)); \
600} while (0)
601
602#define MACvGetCurrRx0DescAddr(iobase, pdwCurrDescAddr) \
603 VNSvInPortD(iobase + MAC_REG_RXDMAPTR0, \
604 (unsigned long *)pdwCurrDescAddr)
605
606#define MACvGetCurrRx1DescAddr(iobase, pdwCurrDescAddr) \
607 VNSvInPortD(iobase + MAC_REG_RXDMAPTR1, \
608 (unsigned long *)pdwCurrDescAddr)
609
610#define MACvGetCurrTx0DescAddr(iobase, pdwCurrDescAddr) \
611 VNSvInPortD(iobase + MAC_REG_TXDMAPTR0, \
612 (unsigned long *)pdwCurrDescAddr)
613
614#define MACvGetCurrAC0DescAddr(iobase, pdwCurrDescAddr) \
615 VNSvInPortD(iobase + MAC_REG_AC0DMAPTR, \
616 (unsigned long *)pdwCurrDescAddr)
617
618#define MACvGetCurrSyncDescAddr(iobase, pdwCurrDescAddr) \
619 VNSvInPortD(iobase + MAC_REG_SYNCDMAPTR, \
620 (unsigned long *)pdwCurrDescAddr)
621
622#define MACvGetCurrATIMDescAddr(iobase, pdwCurrDescAddr) \
623 VNSvInPortD(iobase + MAC_REG_ATIMDMAPTR, \
624 (unsigned long *)pdwCurrDescAddr)
625
626/* set the chip with current BCN tx descriptor address */
627#define MACvSetCurrBCNTxDescAddr(iobase, dwCurrDescAddr) \
628 VNSvOutPortD(iobase + MAC_REG_BCNDMAPTR, \
629 dwCurrDescAddr)
630
631/* set the chip with current BCN length */
632#define MACvSetCurrBCNLength(iobase, wCurrBCNLength) \
633 VNSvOutPortW(iobase + MAC_REG_BCNDMACTL+2, \
634 wCurrBCNLength)
635
636#define MACvReadBSSIDAddress(iobase, pbyEtherAddr) \
637do { \
638 VNSvOutPortB(iobase + MAC_REG_PAGE1SEL, 1); \
639 VNSvInPortB(iobase + MAC_REG_BSSID0, \
640 (unsigned char *)pbyEtherAddr); \
641 VNSvInPortB(iobase + MAC_REG_BSSID0 + 1, \
642 pbyEtherAddr + 1); \
643 VNSvInPortB(iobase + MAC_REG_BSSID0 + 2, \
644 pbyEtherAddr + 2); \
645 VNSvInPortB(iobase + MAC_REG_BSSID0 + 3, \
646 pbyEtherAddr + 3); \
647 VNSvInPortB(iobase + MAC_REG_BSSID0 + 4, \
648 pbyEtherAddr + 4); \
649 VNSvInPortB(iobase + MAC_REG_BSSID0 + 5, \
650 pbyEtherAddr + 5); \
651 VNSvOutPortB(iobase + MAC_REG_PAGE1SEL, 0); \
652} while (0)
653
654#define MACvWriteBSSIDAddress(iobase, pbyEtherAddr) \
655do { \
656 VNSvOutPortB(iobase + MAC_REG_PAGE1SEL, 1); \
657 VNSvOutPortB(iobase + MAC_REG_BSSID0, \
658 *(pbyEtherAddr)); \
659 VNSvOutPortB(iobase + MAC_REG_BSSID0 + 1, \
660 *(pbyEtherAddr + 1)); \
661 VNSvOutPortB(iobase + MAC_REG_BSSID0 + 2, \
662 *(pbyEtherAddr + 2)); \
663 VNSvOutPortB(iobase + MAC_REG_BSSID0 + 3, \
664 *(pbyEtherAddr + 3)); \
665 VNSvOutPortB(iobase + MAC_REG_BSSID0 + 4, \
666 *(pbyEtherAddr + 4)); \
667 VNSvOutPortB(iobase + MAC_REG_BSSID0 + 5, \
668 *(pbyEtherAddr + 5)); \
669 VNSvOutPortB(iobase + MAC_REG_PAGE1SEL, 0); \
670} while (0)
671
672#define MACvReadEtherAddress(iobase, pbyEtherAddr) \
673do { \
674 VNSvOutPortB(iobase + MAC_REG_PAGE1SEL, 1); \
675 VNSvInPortB(iobase + MAC_REG_PAR0, \
676 (unsigned char *)pbyEtherAddr); \
677 VNSvInPortB(iobase + MAC_REG_PAR0 + 1, \
678 pbyEtherAddr + 1); \
679 VNSvInPortB(iobase + MAC_REG_PAR0 + 2, \
680 pbyEtherAddr + 2); \
681 VNSvInPortB(iobase + MAC_REG_PAR0 + 3, \
682 pbyEtherAddr + 3); \
683 VNSvInPortB(iobase + MAC_REG_PAR0 + 4, \
684 pbyEtherAddr + 4); \
685 VNSvInPortB(iobase + MAC_REG_PAR0 + 5, \
686 pbyEtherAddr + 5); \
687 VNSvOutPortB(iobase + MAC_REG_PAGE1SEL, 0); \
688} while (0)
689
690#define MACvWriteEtherAddress(iobase, pbyEtherAddr) \
691do { \
692 VNSvOutPortB(iobase + MAC_REG_PAGE1SEL, 1); \
693 VNSvOutPortB(iobase + MAC_REG_PAR0, \
694 *pbyEtherAddr); \
695 VNSvOutPortB(iobase + MAC_REG_PAR0 + 1, \
696 *(pbyEtherAddr + 1)); \
697 VNSvOutPortB(iobase + MAC_REG_PAR0 + 2, \
698 *(pbyEtherAddr + 2)); \
699 VNSvOutPortB(iobase + MAC_REG_PAR0 + 3, \
700 *(pbyEtherAddr + 3)); \
701 VNSvOutPortB(iobase + MAC_REG_PAR0 + 4, \
702 *(pbyEtherAddr + 4)); \
703 VNSvOutPortB(iobase + MAC_REG_PAR0 + 5, \
704 *(pbyEtherAddr + 5)); \
705 VNSvOutPortB(iobase + MAC_REG_PAGE1SEL, 0); \
706} while (0)
707
708#define MACvClearISR(iobase) \
709 VNSvOutPortD(iobase + MAC_REG_ISR, IMR_MASK_VALUE)
710
711#define MACvStart(iobase) \
712 VNSvOutPortB(iobase + MAC_REG_HOSTCR, \
713 (HOSTCR_MACEN | HOSTCR_RXON | HOSTCR_TXON))
714
715#define MACvRx0PerPktMode(iobase) \
716 VNSvOutPortD(iobase + MAC_REG_RXDMACTL0, RX_PERPKT)
717
718#define MACvRx0BufferFillMode(iobase) \
719 VNSvOutPortD(iobase + MAC_REG_RXDMACTL0, RX_PERPKTCLR)
720
721#define MACvRx1PerPktMode(iobase) \
722 VNSvOutPortD(iobase + MAC_REG_RXDMACTL1, RX_PERPKT)
723
724#define MACvRx1BufferFillMode(iobase) \
725 VNSvOutPortD(iobase + MAC_REG_RXDMACTL1, RX_PERPKTCLR)
726
727#define MACvRxOn(iobase) \
728 MACvRegBitsOn(iobase, MAC_REG_HOSTCR, HOSTCR_RXON)
729
730#define MACvReceive0(iobase) \
731do { \
732 unsigned long dwData; \
733 VNSvInPortD(iobase + MAC_REG_RXDMACTL0, &dwData); \
734 if (dwData & DMACTL_RUN) \
735 VNSvOutPortD(iobase + MAC_REG_RXDMACTL0, DMACTL_WAKE); \
736 else \
737 VNSvOutPortD(iobase + MAC_REG_RXDMACTL0, DMACTL_RUN); \
738} while (0)
739
740#define MACvReceive1(iobase) \
741do { \
742 unsigned long dwData; \
743 VNSvInPortD(iobase + MAC_REG_RXDMACTL1, &dwData); \
744 if (dwData & DMACTL_RUN) \
745 VNSvOutPortD(iobase + MAC_REG_RXDMACTL1, DMACTL_WAKE); \
746 else \
747 VNSvOutPortD(iobase + MAC_REG_RXDMACTL1, DMACTL_RUN); \
748} while (0)
749
750#define MACvTxOn(iobase) \
751 MACvRegBitsOn(iobase, MAC_REG_HOSTCR, HOSTCR_TXON)
752
753#define MACvTransmit0(iobase) \
754do { \
755 unsigned long dwData; \
756 VNSvInPortD(iobase + MAC_REG_TXDMACTL0, &dwData); \
757 if (dwData & DMACTL_RUN) \
758 VNSvOutPortD(iobase + MAC_REG_TXDMACTL0, DMACTL_WAKE); \
759 else \
760 VNSvOutPortD(iobase + MAC_REG_TXDMACTL0, DMACTL_RUN); \
761} while (0)
762
763#define MACvTransmitAC0(iobase) \
764do { \
765 unsigned long dwData; \
766 VNSvInPortD(iobase + MAC_REG_AC0DMACTL, &dwData); \
767 if (dwData & DMACTL_RUN) \
768 VNSvOutPortD(iobase + MAC_REG_AC0DMACTL, DMACTL_WAKE); \
769 else \
770 VNSvOutPortD(iobase + MAC_REG_AC0DMACTL, DMACTL_RUN); \
771} while (0)
772
773#define MACvTransmitSYNC(iobase) \
774do { \
775 unsigned long dwData; \
776 VNSvInPortD(iobase + MAC_REG_SYNCDMACTL, &dwData); \
777 if (dwData & DMACTL_RUN) \
778 VNSvOutPortD(iobase + MAC_REG_SYNCDMACTL, DMACTL_WAKE); \
779 else \
780 VNSvOutPortD(iobase + MAC_REG_SYNCDMACTL, DMACTL_RUN); \
781} while (0)
782
783#define MACvTransmitATIM(iobase) \
784do { \
785 unsigned long dwData; \
786 VNSvInPortD(iobase + MAC_REG_ATIMDMACTL, &dwData); \
787 if (dwData & DMACTL_RUN) \
788 VNSvOutPortD(iobase + MAC_REG_ATIMDMACTL, DMACTL_WAKE); \
789 else \
790 VNSvOutPortD(iobase + MAC_REG_ATIMDMACTL, DMACTL_RUN); \
791} while (0)
792
793#define MACvTransmitBCN(iobase) \
794 VNSvOutPortB(iobase + MAC_REG_BCNDMACTL, BEACON_READY)
795
796#define MACvClearStckDS(iobase) \
797do { \
798 unsigned char byOrgValue; \
799 VNSvInPortB(iobase + MAC_REG_STICKHW, &byOrgValue); \
800 byOrgValue = byOrgValue & 0xFC; \
801 VNSvOutPortB(iobase + MAC_REG_STICKHW, byOrgValue); \
802} while (0)
803
804#define MACvReadISR(iobase, pdwValue) \
805 VNSvInPortD(iobase + MAC_REG_ISR, pdwValue)
806
807#define MACvWriteISR(iobase, dwValue) \
808 VNSvOutPortD(iobase + MAC_REG_ISR, dwValue)
809
810#define MACvIntEnable(iobase, dwMask) \
811 VNSvOutPortD(iobase + MAC_REG_IMR, dwMask)
812
813#define MACvIntDisable(iobase) \
814 VNSvOutPortD(iobase + MAC_REG_IMR, 0)
815
816#define MACvSelectPage0(iobase) \
817 VNSvOutPortB(iobase + MAC_REG_PAGE1SEL, 0)
818
819#define MACvSelectPage1(iobase) \
820 VNSvOutPortB(iobase + MAC_REG_PAGE1SEL, 1)
821
822#define MACvReadMIBCounter(iobase, pdwCounter) \
823 VNSvInPortD(iobase + MAC_REG_MIBCNTR, pdwCounter)
824
825#define MACvPwrEvntDisable(iobase) \
826 VNSvOutPortW(iobase + MAC_REG_WAKEUPEN0, 0x0000)
827
828#define MACvEnableProtectMD(iobase) \
829do { \
830 unsigned long dwOrgValue; \
831 VNSvInPortD(iobase + MAC_REG_ENCFG, &dwOrgValue); \
832 dwOrgValue = dwOrgValue | EnCFG_ProtectMd; \
833 VNSvOutPortD(iobase + MAC_REG_ENCFG, dwOrgValue); \
834} while (0)
835
836#define MACvDisableProtectMD(iobase) \
837do { \
838 unsigned long dwOrgValue; \
839 VNSvInPortD(iobase + MAC_REG_ENCFG, &dwOrgValue); \
840 dwOrgValue = dwOrgValue & ~EnCFG_ProtectMd; \
841 VNSvOutPortD(iobase + MAC_REG_ENCFG, dwOrgValue); \
842} while (0)
843
844#define MACvEnableBarkerPreambleMd(iobase) \
845do { \
846 unsigned long dwOrgValue; \
847 VNSvInPortD(iobase + MAC_REG_ENCFG, &dwOrgValue); \
848 dwOrgValue = dwOrgValue | EnCFG_BarkerPream; \
849 VNSvOutPortD(iobase + MAC_REG_ENCFG, dwOrgValue); \
850} while (0)
851
852#define MACvDisableBarkerPreambleMd(iobase) \
853do { \
854 unsigned long dwOrgValue; \
855 VNSvInPortD(iobase + MAC_REG_ENCFG, &dwOrgValue); \
856 dwOrgValue = dwOrgValue & ~EnCFG_BarkerPream; \
857 VNSvOutPortD(iobase + MAC_REG_ENCFG, dwOrgValue); \
858} while (0)
859
860#define MACvSetBBType(iobase, byTyp) \
861do { \
862 unsigned long dwOrgValue; \
863 VNSvInPortD(iobase + MAC_REG_ENCFG, &dwOrgValue); \
864 dwOrgValue = dwOrgValue & ~EnCFG_BBType_MASK; \
865 dwOrgValue = dwOrgValue | (unsigned long)byTyp; \
866 VNSvOutPortD(iobase + MAC_REG_ENCFG, dwOrgValue); \
867} while (0)
868
869#define MACvReadATIMW(iobase, pwCounter) \
870 VNSvInPortW(iobase + MAC_REG_AIDATIM, pwCounter)
871
872#define MACvWriteATIMW(iobase, wCounter) \
873 VNSvOutPortW(iobase + MAC_REG_AIDATIM, wCounter)
874
875#define MACvWriteCRC16_128(iobase, byRegOfs, wCRC) \
876do { \
877 VNSvOutPortB(iobase + MAC_REG_PAGE1SEL, 1); \
878 VNSvOutPortW(iobase + byRegOfs, wCRC); \
879 VNSvOutPortB(iobase + MAC_REG_PAGE1SEL, 0); \
880} while (0)
881
882#define MACvGPIOIn(iobase, pbyValue) \
883 VNSvInPortB(iobase + MAC_REG_GPIOCTL1, pbyValue)
884
885#define MACvSetRFLE_LatchBase(iobase) \
886 MACvWordRegBitsOn(iobase, MAC_REG_SOFTPWRCTL, SOFTPWRCTL_RFLEOPT)
887
888bool MACbIsRegBitsOn(struct vnt_private *priv, unsigned char byRegOfs,
889 unsigned char byTestBits);
890bool MACbIsRegBitsOff(struct vnt_private *priv, unsigned char byRegOfs,
891 unsigned char byTestBits);
892
893bool MACbIsIntDisable(struct vnt_private *priv);
894
895void MACvSetShortRetryLimit(struct vnt_private *priv, unsigned char byRetryLimit);
896
897void MACvSetLongRetryLimit(struct vnt_private *priv, unsigned char byRetryLimit);
898void MACvGetLongRetryLimit(struct vnt_private *priv,
899 unsigned char *pbyRetryLimit);
900
901void MACvSetLoopbackMode(struct vnt_private *priv, unsigned char byLoopbackMode);
902
903void MACvSaveContext(struct vnt_private *priv, unsigned char *pbyCxtBuf);
904void MACvRestoreContext(struct vnt_private *priv, unsigned char *pbyCxtBuf);
905
906bool MACbSoftwareReset(struct vnt_private *priv);
907bool MACbSafeSoftwareReset(struct vnt_private *priv);
908bool MACbSafeRxOff(struct vnt_private *priv);
909bool MACbSafeTxOff(struct vnt_private *priv);
910bool MACbSafeStop(struct vnt_private *priv);
911bool MACbShutdown(struct vnt_private *priv);
912void MACvInitialize(struct vnt_private *priv);
913void MACvSetCurrRx0DescAddr(struct vnt_private *priv,
914 u32 curr_desc_addr);
915void MACvSetCurrRx1DescAddr(struct vnt_private *priv,
916 u32 curr_desc_addr);
917void MACvSetCurrTXDescAddr(int iTxType, struct vnt_private *priv,
918 u32 curr_desc_addr);
919void MACvSetCurrTx0DescAddrEx(struct vnt_private *priv,
920 u32 curr_desc_addr);
921void MACvSetCurrAC0DescAddrEx(struct vnt_private *priv,
922 u32 curr_desc_addr);
923void MACvSetCurrSyncDescAddrEx(struct vnt_private *priv,
924 u32 curr_desc_addr);
925void MACvSetCurrATIMDescAddrEx(struct vnt_private *priv,
926 u32 curr_desc_addr);
927void MACvTimer0MicroSDelay(struct vnt_private *priv, unsigned int uDelay);
928void MACvOneShotTimer1MicroSec(struct vnt_private *priv, unsigned int uDelayTime);
929
930void MACvSetMISCFifo(struct vnt_private *priv, unsigned short wOffset,
931 u32 dwData);
932
933bool MACbPSWakeup(struct vnt_private *priv);
934
935void MACvSetKeyEntry(struct vnt_private *priv, unsigned short wKeyCtl,
936 unsigned int uEntryIdx, unsigned int uKeyIdx,
937 unsigned char *pbyAddr, u32 *pdwKey,
938 unsigned char byLocalID);
939void MACvDisableKeyEntry(struct vnt_private *priv, unsigned int uEntryIdx);
940
941#endif /* __MAC_H__ */