tjh.dev
Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
1/*
2 * Driver for NEC VR4100 series Real Time Clock unit.
3 *
4 * Copyright (C) 2003-2008 Yoichi Yuasa <yuasa@linux-mips.org>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
19 */
20#include <linux/err.h>
21#include <linux/fs.h>
22#include <linux/init.h>
23#include <linux/io.h>
24#include <linux/ioport.h>
25#include <linux/interrupt.h>
26#include <linux/module.h>
27#include <linux/platform_device.h>
28#include <linux/rtc.h>
29#include <linux/spinlock.h>
30#include <linux/types.h>
31#include <linux/uaccess.h>
32#include <linux/log2.h>
33
34#include <asm/div64.h>
35
36MODULE_AUTHOR("Yoichi Yuasa <yuasa@linux-mips.org>");
37MODULE_DESCRIPTION("NEC VR4100 series RTC driver");
38MODULE_LICENSE("GPL v2");
39
40/* RTC 1 registers */
41#define ETIMELREG 0x00
42#define ETIMEMREG 0x02
43#define ETIMEHREG 0x04
44/* RFU */
45#define ECMPLREG 0x08
46#define ECMPMREG 0x0a
47#define ECMPHREG 0x0c
48/* RFU */
49#define RTCL1LREG 0x10
50#define RTCL1HREG 0x12
51#define RTCL1CNTLREG 0x14
52#define RTCL1CNTHREG 0x16
53#define RTCL2LREG 0x18
54#define RTCL2HREG 0x1a
55#define RTCL2CNTLREG 0x1c
56#define RTCL2CNTHREG 0x1e
57
58/* RTC 2 registers */
59#define TCLKLREG 0x00
60#define TCLKHREG 0x02
61#define TCLKCNTLREG 0x04
62#define TCLKCNTHREG 0x06
63/* RFU */
64#define RTCINTREG 0x1e
65 #define TCLOCK_INT 0x08
66 #define RTCLONG2_INT 0x04
67 #define RTCLONG1_INT 0x02
68 #define ELAPSEDTIME_INT 0x01
69
70#define RTC_FREQUENCY 32768
71#define MAX_PERIODIC_RATE 6553
72
73static void __iomem *rtc1_base;
74static void __iomem *rtc2_base;
75
76#define rtc1_read(offset) readw(rtc1_base + (offset))
77#define rtc1_write(offset, value) writew((value), rtc1_base + (offset))
78
79#define rtc2_read(offset) readw(rtc2_base + (offset))
80#define rtc2_write(offset, value) writew((value), rtc2_base + (offset))
81
82static unsigned long epoch = 1970; /* Jan 1 1970 00:00:00 */
83
84static DEFINE_SPINLOCK(rtc_lock);
85static char rtc_name[] = "RTC";
86static unsigned long periodic_count;
87static unsigned int alarm_enabled;
88static int aie_irq;
89static int pie_irq;
90
91static inline unsigned long read_elapsed_second(void)
92{
93
94 unsigned long first_low, first_mid, first_high;
95
96 unsigned long second_low, second_mid, second_high;
97
98 do {
99 first_low = rtc1_read(ETIMELREG);
100 first_mid = rtc1_read(ETIMEMREG);
101 first_high = rtc1_read(ETIMEHREG);
102 second_low = rtc1_read(ETIMELREG);
103 second_mid = rtc1_read(ETIMEMREG);
104 second_high = rtc1_read(ETIMEHREG);
105 } while (first_low != second_low || first_mid != second_mid ||
106 first_high != second_high);
107
108 return (first_high << 17) | (first_mid << 1) | (first_low >> 15);
109}
110
111static inline void write_elapsed_second(unsigned long sec)
112{
113 spin_lock_irq(&rtc_lock);
114
115 rtc1_write(ETIMELREG, (uint16_t)(sec << 15));
116 rtc1_write(ETIMEMREG, (uint16_t)(sec >> 1));
117 rtc1_write(ETIMEHREG, (uint16_t)(sec >> 17));
118
119 spin_unlock_irq(&rtc_lock);
120}
121
122static int vr41xx_rtc_read_time(struct device *dev, struct rtc_time *time)
123{
124 unsigned long epoch_sec, elapsed_sec;
125
126 epoch_sec = mktime(epoch, 1, 1, 0, 0, 0);
127 elapsed_sec = read_elapsed_second();
128
129 rtc_time_to_tm(epoch_sec + elapsed_sec, time);
130
131 return 0;
132}
133
134static int vr41xx_rtc_set_time(struct device *dev, struct rtc_time *time)
135{
136 unsigned long epoch_sec, current_sec;
137
138 epoch_sec = mktime(epoch, 1, 1, 0, 0, 0);
139 current_sec = mktime(time->tm_year + 1900, time->tm_mon + 1, time->tm_mday,
140 time->tm_hour, time->tm_min, time->tm_sec);
141
142 write_elapsed_second(current_sec - epoch_sec);
143
144 return 0;
145}
146
147static int vr41xx_rtc_read_alarm(struct device *dev, struct rtc_wkalrm *wkalrm)
148{
149 unsigned long low, mid, high;
150 struct rtc_time *time = &wkalrm->time;
151
152 spin_lock_irq(&rtc_lock);
153
154 low = rtc1_read(ECMPLREG);
155 mid = rtc1_read(ECMPMREG);
156 high = rtc1_read(ECMPHREG);
157 wkalrm->enabled = alarm_enabled;
158
159 spin_unlock_irq(&rtc_lock);
160
161 rtc_time_to_tm((high << 17) | (mid << 1) | (low >> 15), time);
162
163 return 0;
164}
165
166static int vr41xx_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *wkalrm)
167{
168 unsigned long alarm_sec;
169 struct rtc_time *time = &wkalrm->time;
170
171 alarm_sec = mktime(time->tm_year + 1900, time->tm_mon + 1, time->tm_mday,
172 time->tm_hour, time->tm_min, time->tm_sec);
173
174 spin_lock_irq(&rtc_lock);
175
176 if (alarm_enabled)
177 disable_irq(aie_irq);
178
179 rtc1_write(ECMPLREG, (uint16_t)(alarm_sec << 15));
180 rtc1_write(ECMPMREG, (uint16_t)(alarm_sec >> 1));
181 rtc1_write(ECMPHREG, (uint16_t)(alarm_sec >> 17));
182
183 if (wkalrm->enabled)
184 enable_irq(aie_irq);
185
186 alarm_enabled = wkalrm->enabled;
187
188 spin_unlock_irq(&rtc_lock);
189
190 return 0;
191}
192
193static int vr41xx_rtc_ioctl(struct device *dev, unsigned int cmd, unsigned long arg)
194{
195 switch (cmd) {
196 case RTC_EPOCH_READ:
197 return put_user(epoch, (unsigned long __user *)arg);
198 case RTC_EPOCH_SET:
199 /* Doesn't support before 1900 */
200 if (arg < 1900)
201 return -EINVAL;
202 epoch = arg;
203 break;
204 default:
205 return -ENOIOCTLCMD;
206 }
207
208 return 0;
209}
210
211static int vr41xx_rtc_alarm_irq_enable(struct device *dev, unsigned int enabled)
212{
213 spin_lock_irq(&rtc_lock);
214 if (enabled) {
215 if (!alarm_enabled) {
216 enable_irq(aie_irq);
217 alarm_enabled = 1;
218 }
219 } else {
220 if (alarm_enabled) {
221 disable_irq(aie_irq);
222 alarm_enabled = 0;
223 }
224 }
225 spin_unlock_irq(&rtc_lock);
226 return 0;
227}
228
229static irqreturn_t elapsedtime_interrupt(int irq, void *dev_id)
230{
231 struct platform_device *pdev = (struct platform_device *)dev_id;
232 struct rtc_device *rtc = platform_get_drvdata(pdev);
233
234 rtc2_write(RTCINTREG, ELAPSEDTIME_INT);
235
236 rtc_update_irq(rtc, 1, RTC_AF);
237
238 return IRQ_HANDLED;
239}
240
241static irqreturn_t rtclong1_interrupt(int irq, void *dev_id)
242{
243 struct platform_device *pdev = (struct platform_device *)dev_id;
244 struct rtc_device *rtc = platform_get_drvdata(pdev);
245 unsigned long count = periodic_count;
246
247 rtc2_write(RTCINTREG, RTCLONG1_INT);
248
249 rtc1_write(RTCL1LREG, count);
250 rtc1_write(RTCL1HREG, count >> 16);
251
252 rtc_update_irq(rtc, 1, RTC_PF);
253
254 return IRQ_HANDLED;
255}
256
257static const struct rtc_class_ops vr41xx_rtc_ops = {
258 .ioctl = vr41xx_rtc_ioctl,
259 .read_time = vr41xx_rtc_read_time,
260 .set_time = vr41xx_rtc_set_time,
261 .read_alarm = vr41xx_rtc_read_alarm,
262 .set_alarm = vr41xx_rtc_set_alarm,
263 .alarm_irq_enable = vr41xx_rtc_alarm_irq_enable,
264};
265
266static int rtc_probe(struct platform_device *pdev)
267{
268 struct resource *res;
269 struct rtc_device *rtc;
270 int retval;
271
272 if (pdev->num_resources != 4)
273 return -EBUSY;
274
275 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
276 if (!res)
277 return -EBUSY;
278
279 rtc1_base = devm_ioremap(&pdev->dev, res->start, resource_size(res));
280 if (!rtc1_base)
281 return -EBUSY;
282
283 res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
284 if (!res) {
285 retval = -EBUSY;
286 goto err_rtc1_iounmap;
287 }
288
289 rtc2_base = devm_ioremap(&pdev->dev, res->start, resource_size(res));
290 if (!rtc2_base) {
291 retval = -EBUSY;
292 goto err_rtc1_iounmap;
293 }
294
295 rtc = devm_rtc_device_register(&pdev->dev, rtc_name, &vr41xx_rtc_ops,
296 THIS_MODULE);
297 if (IS_ERR(rtc)) {
298 retval = PTR_ERR(rtc);
299 goto err_iounmap_all;
300 }
301
302 rtc->max_user_freq = MAX_PERIODIC_RATE;
303
304 spin_lock_irq(&rtc_lock);
305
306 rtc1_write(ECMPLREG, 0);
307 rtc1_write(ECMPMREG, 0);
308 rtc1_write(ECMPHREG, 0);
309 rtc1_write(RTCL1LREG, 0);
310 rtc1_write(RTCL1HREG, 0);
311
312 spin_unlock_irq(&rtc_lock);
313
314 aie_irq = platform_get_irq(pdev, 0);
315 if (aie_irq <= 0) {
316 retval = -EBUSY;
317 goto err_iounmap_all;
318 }
319
320 retval = devm_request_irq(&pdev->dev, aie_irq, elapsedtime_interrupt, 0,
321 "elapsed_time", pdev);
322 if (retval < 0)
323 goto err_iounmap_all;
324
325 pie_irq = platform_get_irq(pdev, 1);
326 if (pie_irq <= 0) {
327 retval = -EBUSY;
328 goto err_iounmap_all;
329 }
330
331 retval = devm_request_irq(&pdev->dev, pie_irq, rtclong1_interrupt, 0,
332 "rtclong1", pdev);
333 if (retval < 0)
334 goto err_iounmap_all;
335
336 platform_set_drvdata(pdev, rtc);
337
338 disable_irq(aie_irq);
339 disable_irq(pie_irq);
340
341 dev_info(&pdev->dev, "Real Time Clock of NEC VR4100 series\n");
342
343 return 0;
344
345err_iounmap_all:
346 rtc2_base = NULL;
347
348err_rtc1_iounmap:
349 rtc1_base = NULL;
350
351 return retval;
352}
353
354/* work with hotplug and coldplug */
355MODULE_ALIAS("platform:RTC");
356
357static struct platform_driver rtc_platform_driver = {
358 .probe = rtc_probe,
359 .driver = {
360 .name = rtc_name,
361 },
362};
363
364module_platform_driver(rtc_platform_driver);