tjh.dev / kernel
Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel os linux
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kernel / arch / powerpc / include / asm / ppc-opcode.h
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1/* 2 * Copyright 2009 Freescale Semiconductor, Inc. 3 * 4 * This program is free software; you can redistribute it and/or 5 * modify it under the terms of the GNU General Public License 6 * as published by the Free Software Foundation; either version 7 * 2 of the License, or (at your option) any later version. 8 * 9 * provides masks and opcode images for use by code generation, emulation 10 * and for instructions that older assemblers might not know about 11 */ 12#ifndef _ASM_POWERPC_PPC_OPCODE_H 13#define _ASM_POWERPC_PPC_OPCODE_H 14 15#include <linux/stringify.h> 16#include <asm/asm-compat.h> 17 18#define __REG_R0 0 19#define __REG_R1 1 20#define __REG_R2 2 21#define __REG_R3 3 22#define __REG_R4 4 23#define __REG_R5 5 24#define __REG_R6 6 25#define __REG_R7 7 26#define __REG_R8 8 27#define __REG_R9 9 28#define __REG_R10 10 29#define __REG_R11 11 30#define __REG_R12 12 31#define __REG_R13 13 32#define __REG_R14 14 33#define __REG_R15 15 34#define __REG_R16 16 35#define __REG_R17 17 36#define __REG_R18 18 37#define __REG_R19 19 38#define __REG_R20 20 39#define __REG_R21 21 40#define __REG_R22 22 41#define __REG_R23 23 42#define __REG_R24 24 43#define __REG_R25 25 44#define __REG_R26 26 45#define __REG_R27 27 46#define __REG_R28 28 47#define __REG_R29 29 48#define __REG_R30 30 49#define __REG_R31 31 50 51#define __REGA0_0 0 52#define __REGA0_R1 1 53#define __REGA0_R2 2 54#define __REGA0_R3 3 55#define __REGA0_R4 4 56#define __REGA0_R5 5 57#define __REGA0_R6 6 58#define __REGA0_R7 7 59#define __REGA0_R8 8 60#define __REGA0_R9 9 61#define __REGA0_R10 10 62#define __REGA0_R11 11 63#define __REGA0_R12 12 64#define __REGA0_R13 13 65#define __REGA0_R14 14 66#define __REGA0_R15 15 67#define __REGA0_R16 16 68#define __REGA0_R17 17 69#define __REGA0_R18 18 70#define __REGA0_R19 19 71#define __REGA0_R20 20 72#define __REGA0_R21 21 73#define __REGA0_R22 22 74#define __REGA0_R23 23 75#define __REGA0_R24 24 76#define __REGA0_R25 25 77#define __REGA0_R26 26 78#define __REGA0_R27 27 79#define __REGA0_R28 28 80#define __REGA0_R29 29 81#define __REGA0_R30 30 82#define __REGA0_R31 31 83 84/* opcode and xopcode for instructions */ 85#define OP_TRAP 3 86#define OP_TRAP_64 2 87 88#define OP_31_XOP_TRAP 4 89#define OP_31_XOP_LDX 21 90#define OP_31_XOP_LWZX 23 91#define OP_31_XOP_LDUX 53 92#define OP_31_XOP_DCBST 54 93#define OP_31_XOP_LWZUX 55 94#define OP_31_XOP_TRAP_64 68 95#define OP_31_XOP_DCBF 86 96#define OP_31_XOP_LBZX 87 97#define OP_31_XOP_STDX 149 98#define OP_31_XOP_STWX 151 99#define OP_31_XOP_STDUX 181 100#define OP_31_XOP_STWUX 183 101#define OP_31_XOP_STBX 215 102#define OP_31_XOP_LBZUX 119 103#define OP_31_XOP_STBUX 247 104#define OP_31_XOP_LHZX 279 105#define OP_31_XOP_LHZUX 311 106#define OP_31_XOP_MSGSNDP 142 107#define OP_31_XOP_MSGCLRP 174 108#define OP_31_XOP_MFSPR 339 109#define OP_31_XOP_LWAX 341 110#define OP_31_XOP_LHAX 343 111#define OP_31_XOP_LWAUX 373 112#define OP_31_XOP_LHAUX 375 113#define OP_31_XOP_STHX 407 114#define OP_31_XOP_STHUX 439 115#define OP_31_XOP_MTSPR 467 116#define OP_31_XOP_DCBI 470 117#define OP_31_XOP_LDBRX 532 118#define OP_31_XOP_LWBRX 534 119#define OP_31_XOP_TLBSYNC 566 120#define OP_31_XOP_STDBRX 660 121#define OP_31_XOP_STWBRX 662 122#define OP_31_XOP_STFSX 663 123#define OP_31_XOP_STFSUX 695 124#define OP_31_XOP_STFDX 727 125#define OP_31_XOP_STFDUX 759 126#define OP_31_XOP_LHBRX 790 127#define OP_31_XOP_LFIWAX 855 128#define OP_31_XOP_LFIWZX 887 129#define OP_31_XOP_STHBRX 918 130#define OP_31_XOP_STFIWX 983 131 132/* VSX Scalar Load Instructions */ 133#define OP_31_XOP_LXSDX 588 134#define OP_31_XOP_LXSSPX 524 135#define OP_31_XOP_LXSIWAX 76 136#define OP_31_XOP_LXSIWZX 12 137 138/* VSX Scalar Store Instructions */ 139#define OP_31_XOP_STXSDX 716 140#define OP_31_XOP_STXSSPX 652 141#define OP_31_XOP_STXSIWX 140 142 143/* VSX Vector Load Instructions */ 144#define OP_31_XOP_LXVD2X 844 145#define OP_31_XOP_LXVW4X 780 146 147/* VSX Vector Load and Splat Instruction */ 148#define OP_31_XOP_LXVDSX 332 149 150/* VSX Vector Store Instructions */ 151#define OP_31_XOP_STXVD2X 972 152#define OP_31_XOP_STXVW4X 908 153 154#define OP_31_XOP_LFSX 535 155#define OP_31_XOP_LFSUX 567 156#define OP_31_XOP_LFDX 599 157#define OP_31_XOP_LFDUX 631 158 159#define OP_LWZ 32 160#define OP_STFS 52 161#define OP_STFSU 53 162#define OP_STFD 54 163#define OP_STFDU 55 164#define OP_LD 58 165#define OP_LWZU 33 166#define OP_LBZ 34 167#define OP_LBZU 35 168#define OP_STW 36 169#define OP_STWU 37 170#define OP_STD 62 171#define OP_STB 38 172#define OP_STBU 39 173#define OP_LHZ 40 174#define OP_LHZU 41 175#define OP_LHA 42 176#define OP_LHAU 43 177#define OP_STH 44 178#define OP_STHU 45 179#define OP_LMW 46 180#define OP_STMW 47 181#define OP_LFS 48 182#define OP_LFSU 49 183#define OP_LFD 50 184#define OP_LFDU 51 185#define OP_STFS 52 186#define OP_STFSU 53 187#define OP_STFD 54 188#define OP_STFDU 55 189#define OP_LQ 56 190 191/* sorted alphabetically */ 192#define PPC_INST_BHRBE 0x7c00025c 193#define PPC_INST_CLRBHRB 0x7c00035c 194#define PPC_INST_COPY 0x7c20060c 195#define PPC_INST_CP_ABORT 0x7c00068c 196#define PPC_INST_DARN 0x7c0005e6 197#define PPC_INST_DCBA 0x7c0005ec 198#define PPC_INST_DCBA_MASK 0xfc0007fe 199#define PPC_INST_DCBAL 0x7c2005ec 200#define PPC_INST_DCBZL 0x7c2007ec 201#define PPC_INST_ICBT 0x7c00002c 202#define PPC_INST_ICSWX 0x7c00032d 203#define PPC_INST_ICSWEPX 0x7c00076d 204#define PPC_INST_ISEL 0x7c00001e 205#define PPC_INST_ISEL_MASK 0xfc00003e 206#define PPC_INST_LDARX 0x7c0000a8 207#define PPC_INST_STDCX 0x7c0001ad 208#define PPC_INST_LQARX 0x7c000228 209#define PPC_INST_STQCX 0x7c00016d 210#define PPC_INST_LSWI 0x7c0004aa 211#define PPC_INST_LSWX 0x7c00042a 212#define PPC_INST_LWARX 0x7c000028 213#define PPC_INST_STWCX 0x7c00012d 214#define PPC_INST_LWSYNC 0x7c2004ac 215#define PPC_INST_SYNC 0x7c0004ac 216#define PPC_INST_SYNC_MASK 0xfc0007fe 217#define PPC_INST_ISYNC 0x4c00012c 218#define PPC_INST_LXVD2X 0x7c000698 219#define PPC_INST_MCRXR 0x7c000400 220#define PPC_INST_MCRXR_MASK 0xfc0007fe 221#define PPC_INST_MFSPR_PVR 0x7c1f42a6 222#define PPC_INST_MFSPR_PVR_MASK 0xfc1ffffe 223#define PPC_INST_MFTMR 0x7c0002dc 224#define PPC_INST_MSGSND 0x7c00019c 225#define PPC_INST_MSGCLR 0x7c0001dc 226#define PPC_INST_MSGSYNC 0x7c0006ec 227#define PPC_INST_MSGSNDP 0x7c00011c 228#define PPC_INST_MSGCLRP 0x7c00015c 229#define PPC_INST_MTTMR 0x7c0003dc 230#define PPC_INST_NOP 0x60000000 231#define PPC_INST_PASTE 0x7c20070d 232#define PPC_INST_POPCNTB 0x7c0000f4 233#define PPC_INST_POPCNTB_MASK 0xfc0007fe 234#define PPC_INST_POPCNTD 0x7c0003f4 235#define PPC_INST_POPCNTW 0x7c0002f4 236#define PPC_INST_RFCI 0x4c000066 237#define PPC_INST_RFDI 0x4c00004e 238#define PPC_INST_RFMCI 0x4c00004c 239#define PPC_INST_MFSPR_DSCR 0x7c1102a6 240#define PPC_INST_MFSPR_DSCR_MASK 0xfc1ffffe 241#define PPC_INST_MTSPR_DSCR 0x7c1103a6 242#define PPC_INST_MTSPR_DSCR_MASK 0xfc1ffffe 243#define PPC_INST_MFSPR_DSCR_USER 0x7c0302a6 244#define PPC_INST_MFSPR_DSCR_USER_MASK 0xfc1ffffe 245#define PPC_INST_MTSPR_DSCR_USER 0x7c0303a6 246#define PPC_INST_MTSPR_DSCR_USER_MASK 0xfc1ffffe 247#define PPC_INST_MFVSRD 0x7c000066 248#define PPC_INST_MTVSRD 0x7c000166 249#define PPC_INST_SLBFEE 0x7c0007a7 250#define PPC_INST_SLBIA 0x7c0003e4 251 252#define PPC_INST_STRING 0x7c00042a 253#define PPC_INST_STRING_MASK 0xfc0007fe 254#define PPC_INST_STRING_GEN_MASK 0xfc00067e 255 256#define PPC_INST_STSWI 0x7c0005aa 257#define PPC_INST_STSWX 0x7c00052a 258#define PPC_INST_STXVD2X 0x7c000798 259#define PPC_INST_TLBIE 0x7c000264 260#define PPC_INST_TLBIEL 0x7c000224 261#define PPC_INST_TLBILX 0x7c000024 262#define PPC_INST_WAIT 0x7c00007c 263#define PPC_INST_TLBIVAX 0x7c000624 264#define PPC_INST_TLBSRX_DOT 0x7c0006a5 265#define PPC_INST_VPMSUMW 0x10000488 266#define PPC_INST_VPMSUMD 0x100004c8 267#define PPC_INST_XXLOR 0xf0000490 268#define PPC_INST_XXSWAPD 0xf0000250 269#define PPC_INST_XVCPSGNDP 0xf0000780 270#define PPC_INST_TRECHKPT 0x7c0007dd 271#define PPC_INST_TRECLAIM 0x7c00075d 272#define PPC_INST_TABORT 0x7c00071d 273 274#define PPC_INST_NAP 0x4c000364 275#define PPC_INST_SLEEP 0x4c0003a4 276#define PPC_INST_WINKLE 0x4c0003e4 277 278#define PPC_INST_STOP 0x4c0002e4 279 280/* A2 specific instructions */ 281#define PPC_INST_ERATWE 0x7c0001a6 282#define PPC_INST_ERATRE 0x7c000166 283#define PPC_INST_ERATILX 0x7c000066 284#define PPC_INST_ERATIVAX 0x7c000666 285#define PPC_INST_ERATSX 0x7c000126 286#define PPC_INST_ERATSX_DOT 0x7c000127 287 288/* Misc instructions for BPF compiler */ 289#define PPC_INST_LBZ 0x88000000 290#define PPC_INST_LD 0xe8000000 291#define PPC_INST_LHZ 0xa0000000 292#define PPC_INST_LWZ 0x80000000 293#define PPC_INST_LHBRX 0x7c00062c 294#define PPC_INST_LDBRX 0x7c000428 295#define PPC_INST_STB 0x98000000 296#define PPC_INST_STH 0xb0000000 297#define PPC_INST_STD 0xf8000000 298#define PPC_INST_STDU 0xf8000001 299#define PPC_INST_STW 0x90000000 300#define PPC_INST_STWU 0x94000000 301#define PPC_INST_MFLR 0x7c0802a6 302#define PPC_INST_MTLR 0x7c0803a6 303#define PPC_INST_MTCTR 0x7c0903a6 304#define PPC_INST_CMPWI 0x2c000000 305#define PPC_INST_CMPDI 0x2c200000 306#define PPC_INST_CMPW 0x7c000000 307#define PPC_INST_CMPD 0x7c200000 308#define PPC_INST_CMPLW 0x7c000040 309#define PPC_INST_CMPLD 0x7c200040 310#define PPC_INST_CMPLWI 0x28000000 311#define PPC_INST_CMPLDI 0x28200000 312#define PPC_INST_ADDI 0x38000000 313#define PPC_INST_ADDIS 0x3c000000 314#define PPC_INST_ADD 0x7c000214 315#define PPC_INST_SUB 0x7c000050 316#define PPC_INST_BLR 0x4e800020 317#define PPC_INST_BLRL 0x4e800021 318#define PPC_INST_BCTR 0x4e800420 319#define PPC_INST_MULLD 0x7c0001d2 320#define PPC_INST_MULLW 0x7c0001d6 321#define PPC_INST_MULHWU 0x7c000016 322#define PPC_INST_MULLI 0x1c000000 323#define PPC_INST_DIVWU 0x7c000396 324#define PPC_INST_DIVD 0x7c0003d2 325#define PPC_INST_RLWINM 0x54000000 326#define PPC_INST_RLWIMI 0x50000000 327#define PPC_INST_RLDICL 0x78000000 328#define PPC_INST_RLDICR 0x78000004 329#define PPC_INST_SLW 0x7c000030 330#define PPC_INST_SLD 0x7c000036 331#define PPC_INST_SRW 0x7c000430 332#define PPC_INST_SRD 0x7c000436 333#define PPC_INST_SRAD 0x7c000634 334#define PPC_INST_SRADI 0x7c000674 335#define PPC_INST_AND 0x7c000038 336#define PPC_INST_ANDDOT 0x7c000039 337#define PPC_INST_OR 0x7c000378 338#define PPC_INST_XOR 0x7c000278 339#define PPC_INST_ANDI 0x70000000 340#define PPC_INST_ORI 0x60000000 341#define PPC_INST_ORIS 0x64000000 342#define PPC_INST_XORI 0x68000000 343#define PPC_INST_XORIS 0x6c000000 344#define PPC_INST_NEG 0x7c0000d0 345#define PPC_INST_EXTSW 0x7c0007b4 346#define PPC_INST_BRANCH 0x48000000 347#define PPC_INST_BRANCH_COND 0x40800000 348#define PPC_INST_LBZCIX 0x7c0006aa 349#define PPC_INST_STBCIX 0x7c0007aa 350#define PPC_INST_LWZX 0x7c00002e 351#define PPC_INST_LFSX 0x7c00042e 352#define PPC_INST_STFSX 0x7c00052e 353#define PPC_INST_LFDX 0x7c0004ae 354#define PPC_INST_STFDX 0x7c0005ae 355#define PPC_INST_LVX 0x7c0000ce 356#define PPC_INST_STVX 0x7c0001ce 357 358/* macros to insert fields into opcodes */ 359#define ___PPC_RA(a) (((a) & 0x1f) << 16) 360#define ___PPC_RB(b) (((b) & 0x1f) << 11) 361#define ___PPC_RS(s) (((s) & 0x1f) << 21) 362#define ___PPC_RT(t) ___PPC_RS(t) 363#define ___PPC_R(r) (((r) & 0x1) << 16) 364#define ___PPC_PRS(prs) (((prs) & 0x1) << 17) 365#define ___PPC_RIC(ric) (((ric) & 0x3) << 18) 366#define __PPC_RA(a) ___PPC_RA(__REG_##a) 367#define __PPC_RA0(a) ___PPC_RA(__REGA0_##a) 368#define __PPC_RB(b) ___PPC_RB(__REG_##b) 369#define __PPC_RS(s) ___PPC_RS(__REG_##s) 370#define __PPC_RT(t) ___PPC_RT(__REG_##t) 371#define __PPC_XA(a) ((((a) & 0x1f) << 16) | (((a) & 0x20) >> 3)) 372#define __PPC_XB(b) ((((b) & 0x1f) << 11) | (((b) & 0x20) >> 4)) 373#define __PPC_XS(s) ((((s) & 0x1f) << 21) | (((s) & 0x20) >> 5)) 374#define __PPC_XT(s) __PPC_XS(s) 375#define __PPC_T_TLB(t) (((t) & 0x3) << 21) 376#define __PPC_WC(w) (((w) & 0x3) << 21) 377#define __PPC_WS(w) (((w) & 0x1f) << 11) 378#define __PPC_SH(s) __PPC_WS(s) 379#define __PPC_SH64(s) (__PPC_SH(s) | (((s) & 0x20) >> 4)) 380#define __PPC_MB(s) (((s) & 0x1f) << 6) 381#define __PPC_ME(s) (((s) & 0x1f) << 1) 382#define __PPC_MB64(s) (__PPC_MB(s) | ((s) & 0x20)) 383#define __PPC_ME64(s) __PPC_MB64(s) 384#define __PPC_BI(s) (((s) & 0x1f) << 16) 385#define __PPC_CT(t) (((t) & 0x0f) << 21) 386 387/* 388 * Only use the larx hint bit on 64bit CPUs. e500v1/v2 based CPUs will treat a 389 * larx with EH set as an illegal instruction. 390 */ 391#ifdef CONFIG_PPC64 392#define __PPC_EH(eh) (((eh) & 0x1) << 0) 393#else 394#define __PPC_EH(eh) 0 395#endif 396 397/* Deal with instructions that older assemblers aren't aware of */ 398#define PPC_CP_ABORT stringify_in_c(.long PPC_INST_CP_ABORT) 399#define PPC_COPY(a, b) stringify_in_c(.long PPC_INST_COPY | \ 400 ___PPC_RA(a) | ___PPC_RB(b)) 401#define PPC_DARN(t, l) stringify_in_c(.long PPC_INST_DARN | \ 402 ___PPC_RT(t) | \ 403 (((l) & 0x3) << 16)) 404#define PPC_DCBAL(a, b) stringify_in_c(.long PPC_INST_DCBAL | \ 405 __PPC_RA(a) | __PPC_RB(b)) 406#define PPC_DCBZL(a, b) stringify_in_c(.long PPC_INST_DCBZL | \ 407 __PPC_RA(a) | __PPC_RB(b)) 408#define PPC_LQARX(t, a, b, eh) stringify_in_c(.long PPC_INST_LQARX | \ 409 ___PPC_RT(t) | ___PPC_RA(a) | \ 410 ___PPC_RB(b) | __PPC_EH(eh)) 411#define PPC_LDARX(t, a, b, eh) stringify_in_c(.long PPC_INST_LDARX | \ 412 ___PPC_RT(t) | ___PPC_RA(a) | \ 413 ___PPC_RB(b) | __PPC_EH(eh)) 414#define PPC_LWARX(t, a, b, eh) stringify_in_c(.long PPC_INST_LWARX | \ 415 ___PPC_RT(t) | ___PPC_RA(a) | \ 416 ___PPC_RB(b) | __PPC_EH(eh)) 417#define PPC_STQCX(t, a, b) stringify_in_c(.long PPC_INST_STQCX | \ 418 ___PPC_RT(t) | ___PPC_RA(a) | \ 419 ___PPC_RB(b)) 420#define PPC_MSGSND(b) stringify_in_c(.long PPC_INST_MSGSND | \ 421 ___PPC_RB(b)) 422#define PPC_MSGSYNC stringify_in_c(.long PPC_INST_MSGSYNC) 423#define PPC_MSGCLR(b) stringify_in_c(.long PPC_INST_MSGCLR | \ 424 ___PPC_RB(b)) 425#define PPC_MSGSNDP(b) stringify_in_c(.long PPC_INST_MSGSNDP | \ 426 ___PPC_RB(b)) 427#define PPC_MSGCLRP(b) stringify_in_c(.long PPC_INST_MSGCLRP | \ 428 ___PPC_RB(b)) 429#define PPC_PASTE(a, b) stringify_in_c(.long PPC_INST_PASTE | \ 430 ___PPC_RA(a) | ___PPC_RB(b)) 431#define PPC_POPCNTB(a, s) stringify_in_c(.long PPC_INST_POPCNTB | \ 432 __PPC_RA(a) | __PPC_RS(s)) 433#define PPC_POPCNTD(a, s) stringify_in_c(.long PPC_INST_POPCNTD | \ 434 __PPC_RA(a) | __PPC_RS(s)) 435#define PPC_POPCNTW(a, s) stringify_in_c(.long PPC_INST_POPCNTW | \ 436 __PPC_RA(a) | __PPC_RS(s)) 437#define PPC_RFCI stringify_in_c(.long PPC_INST_RFCI) 438#define PPC_RFDI stringify_in_c(.long PPC_INST_RFDI) 439#define PPC_RFMCI stringify_in_c(.long PPC_INST_RFMCI) 440#define PPC_TLBILX(t, a, b) stringify_in_c(.long PPC_INST_TLBILX | \ 441 __PPC_T_TLB(t) | __PPC_RA0(a) | __PPC_RB(b)) 442#define PPC_TLBILX_ALL(a, b) PPC_TLBILX(0, a, b) 443#define PPC_TLBILX_PID(a, b) PPC_TLBILX(1, a, b) 444#define PPC_TLBILX_VA(a, b) PPC_TLBILX(3, a, b) 445#define PPC_WAIT(w) stringify_in_c(.long PPC_INST_WAIT | \ 446 __PPC_WC(w)) 447#define PPC_TLBIE(lp,a) stringify_in_c(.long PPC_INST_TLBIE | \ 448 ___PPC_RB(a) | ___PPC_RS(lp)) 449#define PPC_TLBIE_5(rb,rs,ric,prs,r) \ 450 stringify_in_c(.long PPC_INST_TLBIE | \ 451 ___PPC_RB(rb) | ___PPC_RS(rs) | \ 452 ___PPC_RIC(ric) | ___PPC_PRS(prs) | \ 453 ___PPC_R(r)) 454#define PPC_TLBIEL(rb,rs,ric,prs,r) \ 455 stringify_in_c(.long PPC_INST_TLBIEL | \ 456 ___PPC_RB(rb) | ___PPC_RS(rs) | \ 457 ___PPC_RIC(ric) | ___PPC_PRS(prs) | \ 458 ___PPC_R(r)) 459#define PPC_TLBSRX_DOT(a,b) stringify_in_c(.long PPC_INST_TLBSRX_DOT | \ 460 __PPC_RA0(a) | __PPC_RB(b)) 461#define PPC_TLBIVAX(a,b) stringify_in_c(.long PPC_INST_TLBIVAX | \ 462 __PPC_RA0(a) | __PPC_RB(b)) 463 464#define PPC_ERATWE(s, a, w) stringify_in_c(.long PPC_INST_ERATWE | \ 465 __PPC_RS(s) | __PPC_RA(a) | __PPC_WS(w)) 466#define PPC_ERATRE(s, a, w) stringify_in_c(.long PPC_INST_ERATRE | \ 467 __PPC_RS(s) | __PPC_RA(a) | __PPC_WS(w)) 468#define PPC_ERATILX(t, a, b) stringify_in_c(.long PPC_INST_ERATILX | \ 469 __PPC_T_TLB(t) | __PPC_RA0(a) | \ 470 __PPC_RB(b)) 471#define PPC_ERATIVAX(s, a, b) stringify_in_c(.long PPC_INST_ERATIVAX | \ 472 __PPC_RS(s) | __PPC_RA0(a) | __PPC_RB(b)) 473#define PPC_ERATSX(t, a, w) stringify_in_c(.long PPC_INST_ERATSX | \ 474 __PPC_RS(t) | __PPC_RA0(a) | __PPC_RB(b)) 475#define PPC_ERATSX_DOT(t, a, w) stringify_in_c(.long PPC_INST_ERATSX_DOT | \ 476 __PPC_RS(t) | __PPC_RA0(a) | __PPC_RB(b)) 477#define PPC_SLBFEE_DOT(t, b) stringify_in_c(.long PPC_INST_SLBFEE | \ 478 __PPC_RT(t) | __PPC_RB(b)) 479#define PPC_ICBT(c,a,b) stringify_in_c(.long PPC_INST_ICBT | \ 480 __PPC_CT(c) | __PPC_RA0(a) | __PPC_RB(b)) 481/* PASemi instructions */ 482#define LBZCIX(t,a,b) stringify_in_c(.long PPC_INST_LBZCIX | \ 483 __PPC_RT(t) | __PPC_RA(a) | __PPC_RB(b)) 484#define STBCIX(s,a,b) stringify_in_c(.long PPC_INST_STBCIX | \ 485 __PPC_RS(s) | __PPC_RA(a) | __PPC_RB(b)) 486 487/* 488 * Define what the VSX XX1 form instructions will look like, then add 489 * the 128 bit load store instructions based on that. 490 */ 491#define VSX_XX1(s, a, b) (__PPC_XS(s) | __PPC_RA(a) | __PPC_RB(b)) 492#define VSX_XX3(t, a, b) (__PPC_XT(t) | __PPC_XA(a) | __PPC_XB(b)) 493#define STXVD2X(s, a, b) stringify_in_c(.long PPC_INST_STXVD2X | \ 494 VSX_XX1((s), a, b)) 495#define LXVD2X(s, a, b) stringify_in_c(.long PPC_INST_LXVD2X | \ 496 VSX_XX1((s), a, b)) 497#define MFVRD(a, t) stringify_in_c(.long PPC_INST_MFVSRD | \ 498 VSX_XX1((t)+32, a, R0)) 499#define MTVRD(t, a) stringify_in_c(.long PPC_INST_MTVSRD | \ 500 VSX_XX1((t)+32, a, R0)) 501#define VPMSUMW(t, a, b) stringify_in_c(.long PPC_INST_VPMSUMW | \ 502 VSX_XX3((t), a, b)) 503#define VPMSUMD(t, a, b) stringify_in_c(.long PPC_INST_VPMSUMD | \ 504 VSX_XX3((t), a, b)) 505#define XXLOR(t, a, b) stringify_in_c(.long PPC_INST_XXLOR | \ 506 VSX_XX3((t), a, b)) 507#define XXSWAPD(t, a) stringify_in_c(.long PPC_INST_XXSWAPD | \ 508 VSX_XX3((t), a, a)) 509#define XVCPSGNDP(t, a, b) stringify_in_c(.long (PPC_INST_XVCPSGNDP | \ 510 VSX_XX3((t), (a), (b)))) 511 512#define PPC_NAP stringify_in_c(.long PPC_INST_NAP) 513#define PPC_SLEEP stringify_in_c(.long PPC_INST_SLEEP) 514#define PPC_WINKLE stringify_in_c(.long PPC_INST_WINKLE) 515 516#define PPC_STOP stringify_in_c(.long PPC_INST_STOP) 517 518/* BHRB instructions */ 519#define PPC_CLRBHRB stringify_in_c(.long PPC_INST_CLRBHRB) 520#define PPC_MFBHRBE(r, n) stringify_in_c(.long PPC_INST_BHRBE | \ 521 __PPC_RT(r) | \ 522 (((n) & 0x3ff) << 11)) 523 524/* Transactional memory instructions */ 525#define TRECHKPT stringify_in_c(.long PPC_INST_TRECHKPT) 526#define TRECLAIM(r) stringify_in_c(.long PPC_INST_TRECLAIM \ 527 | __PPC_RA(r)) 528#define TABORT(r) stringify_in_c(.long PPC_INST_TABORT \ 529 | __PPC_RA(r)) 530 531/* book3e thread control instructions */ 532#define TMRN(x) ((((x) & 0x1f) << 16) | (((x) & 0x3e0) << 6)) 533#define MTTMR(tmr, r) stringify_in_c(.long PPC_INST_MTTMR | \ 534 TMRN(tmr) | ___PPC_RS(r)) 535#define MFTMR(tmr, r) stringify_in_c(.long PPC_INST_MFTMR | \ 536 TMRN(tmr) | ___PPC_RT(r)) 537 538/* Coprocessor instructions */ 539#define PPC_ICSWX(s, a, b) stringify_in_c(.long PPC_INST_ICSWX | \ 540 ___PPC_RS(s) | \ 541 ___PPC_RA(a) | \ 542 ___PPC_RB(b)) 543#define PPC_ICSWEPX(s, a, b) stringify_in_c(.long PPC_INST_ICSWEPX | \ 544 ___PPC_RS(s) | \ 545 ___PPC_RA(a) | \ 546 ___PPC_RB(b)) 547 548#define PPC_SLBIA(IH) stringify_in_c(.long PPC_INST_SLBIA | \ 549 ((IH & 0x7) << 21)) 550#define PPC_INVALIDATE_ERAT PPC_SLBIA(7) 551 552#endif /* _ASM_POWERPC_PPC_OPCODE_H */