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1/* SPDX-License-Identifier: GPL-2.0 */
2/*
3 * CRIS pgtable.h - macros and functions to manipulate page tables.
4 */
5
6#ifndef _CRIS_PGTABLE_H
7#define _CRIS_PGTABLE_H
8
9#include <asm/page.h>
10#define __ARCH_USE_5LEVEL_HACK
11#include <asm-generic/pgtable-nopmd.h>
12
13#ifndef __ASSEMBLY__
14#include <linux/sched/mm.h>
15#include <asm/mmu.h>
16#endif
17#include <arch/pgtable.h>
18
19/*
20 * The Linux memory management assumes a three-level page table setup. On
21 * CRIS, we use that, but "fold" the mid level into the top-level page
22 * table. Since the MMU TLB is software loaded through an interrupt, it
23 * supports any page table structure, so we could have used a three-level
24 * setup, but for the amounts of memory we normally use, a two-level is
25 * probably more efficient.
26 *
27 * This file contains the functions and defines necessary to modify and use
28 * the CRIS page table tree.
29 */
30#ifndef __ASSEMBLY__
31extern void paging_init(void);
32#endif
33
34/* Certain architectures need to do special things when pte's
35 * within a page table are directly modified. Thus, the following
36 * hook is made available.
37 */
38#define set_pte(pteptr, pteval) ((*(pteptr)) = (pteval))
39#define set_pte_at(mm,addr,ptep,pteval) set_pte(ptep,pteval)
40
41/*
42 * (pmds are folded into pgds so this doesn't get actually called,
43 * but the define is needed for a generic inline function.)
44 */
45#define set_pmd(pmdptr, pmdval) (*(pmdptr) = pmdval)
46#define set_pgu(pudptr, pudval) (*(pudptr) = pudval)
47
48/* PGDIR_SHIFT determines the size of the area a second-level page table can
49 * map. It is equal to the page size times the number of PTE's that fit in
50 * a PMD page. A PTE is 4-bytes in CRIS. Hence the following number.
51 */
52
53#define PGDIR_SHIFT (PAGE_SHIFT + (PAGE_SHIFT-2))
54#define PGDIR_SIZE (1UL << PGDIR_SHIFT)
55#define PGDIR_MASK (~(PGDIR_SIZE-1))
56
57/*
58 * entries per page directory level: we use a two-level, so
59 * we don't really have any PMD directory physically.
60 * pointers are 4 bytes so we can use the page size and
61 * divide it by 4 (shift by 2).
62 */
63#define PTRS_PER_PTE (1UL << (PAGE_SHIFT-2))
64#define PTRS_PER_PGD (1UL << (PAGE_SHIFT-2))
65
66/* calculate how many PGD entries a user-level program can use
67 * the first mappable virtual address is 0
68 * (TASK_SIZE is the maximum virtual address space)
69 */
70
71#define USER_PTRS_PER_PGD (TASK_SIZE/PGDIR_SIZE)
72#define FIRST_USER_ADDRESS 0UL
73
74/* zero page used for uninitialized stuff */
75#ifndef __ASSEMBLY__
76extern unsigned long empty_zero_page;
77#define ZERO_PAGE(vaddr) (virt_to_page(empty_zero_page))
78#endif
79
80/* number of bits that fit into a memory pointer */
81#define BITS_PER_PTR (8*sizeof(unsigned long))
82
83/* to align the pointer to a pointer address */
84#define PTR_MASK (~(sizeof(void*)-1))
85
86/* sizeof(void*)==1<<SIZEOF_PTR_LOG2 */
87/* 64-bit machines, beware! SRB. */
88#define SIZEOF_PTR_LOG2 2
89
90/* to find an entry in a page-table */
91#define PAGE_PTR(address) \
92((unsigned long)(address)>>(PAGE_SHIFT-SIZEOF_PTR_LOG2)&PTR_MASK&~PAGE_MASK)
93
94/* to set the page-dir */
95#define SET_PAGE_DIR(tsk,pgdir)
96
97#define pte_none(x) (!pte_val(x))
98#define pte_present(x) (pte_val(x) & _PAGE_PRESENT)
99#define pte_clear(mm,addr,xp) do { pte_val(*(xp)) = 0; } while (0)
100
101#define pmd_none(x) (!pmd_val(x))
102/* by removing the _PAGE_KERNEL bit from the comparison, the same pmd_bad
103 * works for both _PAGE_TABLE and _KERNPG_TABLE pmd entries.
104 */
105#define pmd_bad(x) ((pmd_val(x) & (~PAGE_MASK & ~_PAGE_KERNEL)) != _PAGE_TABLE)
106#define pmd_present(x) (pmd_val(x) & _PAGE_PRESENT)
107#define pmd_clear(xp) do { pmd_val(*(xp)) = 0; } while (0)
108
109#ifndef __ASSEMBLY__
110
111/*
112 * The following only work if pte_present() is true.
113 * Undefined behaviour if not..
114 */
115
116static inline int pte_write(pte_t pte) { return pte_val(pte) & _PAGE_WRITE; }
117static inline int pte_dirty(pte_t pte) { return pte_val(pte) & _PAGE_MODIFIED; }
118static inline int pte_young(pte_t pte) { return pte_val(pte) & _PAGE_ACCESSED; }
119static inline int pte_special(pte_t pte) { return 0; }
120
121static inline pte_t pte_wrprotect(pte_t pte)
122{
123 pte_val(pte) &= ~(_PAGE_WRITE | _PAGE_SILENT_WRITE);
124 return pte;
125}
126
127static inline pte_t pte_mkclean(pte_t pte)
128{
129 pte_val(pte) &= ~(_PAGE_MODIFIED | _PAGE_SILENT_WRITE);
130 return pte;
131}
132
133static inline pte_t pte_mkold(pte_t pte)
134{
135 pte_val(pte) &= ~(_PAGE_ACCESSED | _PAGE_SILENT_READ);
136 return pte;
137}
138
139static inline pte_t pte_mkwrite(pte_t pte)
140{
141 pte_val(pte) |= _PAGE_WRITE;
142 if (pte_val(pte) & _PAGE_MODIFIED)
143 pte_val(pte) |= _PAGE_SILENT_WRITE;
144 return pte;
145}
146
147static inline pte_t pte_mkdirty(pte_t pte)
148{
149 pte_val(pte) |= _PAGE_MODIFIED;
150 if (pte_val(pte) & _PAGE_WRITE)
151 pte_val(pte) |= _PAGE_SILENT_WRITE;
152 return pte;
153}
154
155static inline pte_t pte_mkyoung(pte_t pte)
156{
157 pte_val(pte) |= _PAGE_ACCESSED;
158 if (pte_val(pte) & _PAGE_READ)
159 {
160 pte_val(pte) |= _PAGE_SILENT_READ;
161 if ((pte_val(pte) & (_PAGE_WRITE | _PAGE_MODIFIED)) ==
162 (_PAGE_WRITE | _PAGE_MODIFIED))
163 pte_val(pte) |= _PAGE_SILENT_WRITE;
164 }
165 return pte;
166}
167static inline pte_t pte_mkspecial(pte_t pte) { return pte; }
168
169/*
170 * Conversion functions: convert a page and protection to a page entry,
171 * and a page entry and page directory to the page they refer to.
172 */
173
174/* What actually goes as arguments to the various functions is less than
175 * obvious, but a rule of thumb is that struct page's goes as struct page *,
176 * really physical DRAM addresses are unsigned long's, and DRAM "virtual"
177 * addresses (the 0xc0xxxxxx's) goes as void *'s.
178 */
179
180static inline pte_t __mk_pte(void * page, pgprot_t pgprot)
181{
182 pte_t pte;
183 /* the PTE needs a physical address */
184 pte_val(pte) = __pa(page) | pgprot_val(pgprot);
185 return pte;
186}
187
188#define mk_pte(page, pgprot) __mk_pte(page_address(page), (pgprot))
189
190#define mk_pte_phys(physpage, pgprot) \
191({ \
192 pte_t __pte; \
193 \
194 pte_val(__pte) = (physpage) + pgprot_val(pgprot); \
195 __pte; \
196})
197
198static inline pte_t pte_modify(pte_t pte, pgprot_t newprot)
199{ pte_val(pte) = (pte_val(pte) & _PAGE_CHG_MASK) | pgprot_val(newprot); return pte; }
200
201#define pgprot_noncached(prot) __pgprot((pgprot_val(prot) | _PAGE_NO_CACHE))
202
203
204/* pte_val refers to a page in the 0x4xxxxxxx physical DRAM interval
205 * __pte_page(pte_val) refers to the "virtual" DRAM interval
206 * pte_pagenr refers to the page-number counted starting from the virtual DRAM start
207 */
208
209static inline unsigned long __pte_page(pte_t pte)
210{
211 /* the PTE contains a physical address */
212 return (unsigned long)__va(pte_val(pte) & PAGE_MASK);
213}
214
215#define pte_pagenr(pte) ((__pte_page(pte) - PAGE_OFFSET) >> PAGE_SHIFT)
216
217/* permanent address of a page */
218
219#define __page_address(page) (PAGE_OFFSET + (((page) - mem_map) << PAGE_SHIFT))
220#define pte_page(pte) (mem_map+pte_pagenr(pte))
221
222/* only the pte's themselves need to point to physical DRAM (see above)
223 * the pagetable links are purely handled within the kernel SW and thus
224 * don't need the __pa and __va transformations.
225 */
226
227static inline void pmd_set(pmd_t * pmdp, pte_t * ptep)
228{ pmd_val(*pmdp) = _PAGE_TABLE | (unsigned long) ptep; }
229
230#define pmd_page(pmd) (pfn_to_page(pmd_val(pmd) >> PAGE_SHIFT))
231#define pmd_page_vaddr(pmd) ((unsigned long) __va(pmd_val(pmd) & PAGE_MASK))
232
233/* to find an entry in a page-table-directory. */
234#define pgd_index(address) (((address) >> PGDIR_SHIFT) & (PTRS_PER_PGD-1))
235
236/* to find an entry in a page-table-directory */
237static inline pgd_t * pgd_offset(const struct mm_struct *mm, unsigned long address)
238{
239 return mm->pgd + pgd_index(address);
240}
241
242/* to find an entry in a kernel page-table-directory */
243#define pgd_offset_k(address) pgd_offset(&init_mm, address)
244
245/* Find an entry in the third-level page table.. */
246#define __pte_offset(address) \
247 (((address) >> PAGE_SHIFT) & (PTRS_PER_PTE - 1))
248#define pte_offset_kernel(dir, address) \
249 ((pte_t *) pmd_page_vaddr(*(dir)) + __pte_offset(address))
250#define pte_offset_map(dir, address) \
251 ((pte_t *)page_address(pmd_page(*(dir))) + __pte_offset(address))
252
253#define pte_unmap(pte) do { } while (0)
254#define pte_pfn(x) ((unsigned long)(__va((x).pte)) >> PAGE_SHIFT)
255#define pfn_pte(pfn, prot) __pte(((pfn) << PAGE_SHIFT) | pgprot_val(prot))
256
257#define pte_ERROR(e) \
258 printk("%s:%d: bad pte %p(%08lx).\n", __FILE__, __LINE__, &(e), pte_val(e))
259#define pgd_ERROR(e) \
260 printk("%s:%d: bad pgd %p(%08lx).\n", __FILE__, __LINE__, &(e), pgd_val(e))
261
262
263extern pgd_t swapper_pg_dir[PTRS_PER_PGD]; /* defined in head.S */
264
265/*
266 * CRIS doesn't have any external MMU info: the kernel page
267 * tables contain all the necessary information.
268 *
269 * Actually I am not sure on what this could be used for.
270 */
271static inline void update_mmu_cache(struct vm_area_struct * vma,
272 unsigned long address, pte_t *ptep)
273{
274}
275
276/* Encode and de-code a swap entry (must be !pte_none(e) && !pte_present(e)) */
277/* Since the PAGE_PRESENT bit is bit 4, we can use the bits above */
278
279#define __swp_type(x) (((x).val >> 5) & 0x7f)
280#define __swp_offset(x) ((x).val >> 12)
281#define __swp_entry(type, offset) ((swp_entry_t) { ((type) << 5) | ((offset) << 12) })
282#define __pte_to_swp_entry(pte) ((swp_entry_t) { pte_val(pte) })
283#define __swp_entry_to_pte(x) ((pte_t) { (x).val })
284
285#define kern_addr_valid(addr) (1)
286
287#include <asm-generic/pgtable.h>
288
289/*
290 * No page table caches to initialise
291 */
292#define pgtable_cache_init() do { } while (0)
293
294typedef pte_t *pte_addr_t;
295
296#endif /* __ASSEMBLY__ */
297#endif /* _CRIS_PGTABLE_H */