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1* Samsung Exynos Power Domains
2
3Exynos processors include support for multiple power domains which are used
4to gate power to one or more peripherals on the processor.
5
6Required Properties:
7- compatible: should be one of the following.
8 * samsung,exynos4210-pd - for exynos4210 type power domain.
9 * samsung,exynos5433-pd - for exynos5433 type power domain.
10- reg: physical base address of the controller and length of memory mapped
11 region.
12- #power-domain-cells: number of cells in power domain specifier;
13 must be 0.
14
15Optional Properties:
16- label: Human readable string with domain name. Will be visible in userspace
17 to let user to distinguish between multiple domains in SoC.
18- clocks: List of clock handles. The parent clocks of the input clocks to the
19 devices in this power domain are set to oscclk before power gating
20 and restored back after powering on a domain. This is required for
21 all domains which are powered on and off and not required for unused
22 domains.
23- clock-names: The following clocks can be specified:
24 - oscclk: Oscillator clock.
25 - clkN: Input clocks to the devices in this power domain. These clocks
26 will be reparented to oscclk before switching power domain off.
27 Their original parent will be brought back after turning on
28 the domain. Maximum of 4 clocks (N = 0 to 3) are supported.
29 - asbN: Clocks required by asynchronous bridges (ASB) present in
30 the power domain. These clock should be enabled during power
31 domain on/off operations.
32- power-domains: phandle pointing to the parent power domain, for more details
33 see Documentation/devicetree/bindings/power/power_domain.txt
34
35Node of a device using power domains must have a power-domains property
36defined with a phandle to respective power domain.
37
38Example:
39
40 lcd0: power-domain-lcd0 {
41 compatible = "samsung,exynos4210-pd";
42 reg = <0x10023C00 0x10>;
43 #power-domain-cells = <0>;
44 label = "LCD0";
45 };
46
47 mfc_pd: power-domain@10044060 {
48 compatible = "samsung,exynos4210-pd";
49 reg = <0x10044060 0x20>;
50 clocks = <&clock CLK_FIN_PLL>, <&clock CLK_MOUT_USER_ACLK333>;
51 clock-names = "oscclk", "clk0";
52 #power-domain-cells = <0>;
53 label = "MFC";
54 };
55
56See Documentation/devicetree/bindings/power/power_domain.txt for description
57of consumer-side bindings.