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1Device tree bindings for OMAP general purpose memory controllers (GPMC)
2
3The actual devices are instantiated from the child nodes of a GPMC node.
4
5Required properties:
6
7 - compatible: Should be set to one of the following:
8
9 ti,omap2420-gpmc (omap2420)
10 ti,omap2430-gpmc (omap2430)
11 ti,omap3430-gpmc (omap3430 & omap3630)
12 ti,omap4430-gpmc (omap4430 & omap4460 & omap543x)
13 ti,am3352-gpmc (am335x devices)
14
15 - reg: A resource specifier for the register space
16 (see the example below)
17 - ti,hwmods: Should be set to "ti,gpmc" until the DT transition is
18 completed.
19 - #address-cells: Must be set to 2 to allow memory address translation
20 - #size-cells: Must be set to 1 to allow CS address passing
21 - gpmc,num-cs: The maximum number of chip-select lines that controller
22 can support.
23 - gpmc,num-waitpins: The maximum number of wait pins that controller can
24 support.
25 - ranges: Must be set up to reflect the memory layout with four
26 integer values for each chip-select line in use:
27
28 <cs-number> 0 <physical address of mapping> <size>
29
30 Currently, calculated values derived from the contents
31 of the per-CS register GPMC_CONFIG7 (as set up by the
32 bootloader) are used for the physical address decoding.
33 As this will change in the future, filling correct
34 values here is a requirement.
35 - interrupt-controller: The GPMC driver implements and interrupt controller for
36 the NAND events "fifoevent" and "termcount" plus the
37 rising/falling edges on the GPMC_WAIT pins.
38 The interrupt number mapping is as follows
39 0 - NAND_fifoevent
40 1 - NAND_termcount
41 2 - GPMC_WAIT0 pin edge
42 3 - GPMC_WAIT1 pin edge, and so on.
43 - interrupt-cells: Must be set to 2
44 - gpio-controller: The GPMC driver implements a GPIO controller for the
45 GPMC WAIT pins that can be used as general purpose inputs.
46 0 maps to GPMC_WAIT0 pin.
47 - gpio-cells: Must be set to 2
48
49Required properties when using NAND prefetch dma:
50 - dmas GPMC NAND prefetch dma channel
51 - dma-names Must be set to "rxtx"
52
53Timing properties for child nodes. All are optional and default to 0.
54
55 - gpmc,sync-clk-ps: Minimum clock period for synchronous mode, in picoseconds
56
57 Chip-select signal timings (in nanoseconds) corresponding to GPMC_CONFIG2:
58 - gpmc,cs-on-ns: Assertion time
59 - gpmc,cs-rd-off-ns: Read deassertion time
60 - gpmc,cs-wr-off-ns: Write deassertion time
61
62 ADV signal timings (in nanoseconds) corresponding to GPMC_CONFIG3:
63 - gpmc,adv-on-ns: Assertion time
64 - gpmc,adv-rd-off-ns: Read deassertion time
65 - gpmc,adv-wr-off-ns: Write deassertion time
66 - gpmc,adv-aad-mux-on-ns: Assertion time for AAD
67 - gpmc,adv-aad-mux-rd-off-ns: Read deassertion time for AAD
68 - gpmc,adv-aad-mux-wr-off-ns: Write deassertion time for AAD
69
70 WE signals timings (in nanoseconds) corresponding to GPMC_CONFIG4:
71 - gpmc,we-on-ns Assertion time
72 - gpmc,we-off-ns: Deassertion time
73
74 OE signals timings (in nanoseconds) corresponding to GPMC_CONFIG4:
75 - gpmc,oe-on-ns: Assertion time
76 - gpmc,oe-off-ns: Deassertion time
77 - gpmc,oe-aad-mux-on-ns: Assertion time for AAD
78 - gpmc,oe-aad-mux-off-ns: Deassertion time for AAD
79
80 Access time and cycle time timings (in nanoseconds) corresponding to
81 GPMC_CONFIG5:
82 - gpmc,page-burst-access-ns: Multiple access word delay
83 - gpmc,access-ns: Start-cycle to first data valid delay
84 - gpmc,rd-cycle-ns: Total read cycle time
85 - gpmc,wr-cycle-ns: Total write cycle time
86 - gpmc,bus-turnaround-ns: Turn-around time between successive accesses
87 - gpmc,cycle2cycle-delay-ns: Delay between chip-select pulses
88 - gpmc,clk-activation-ns: GPMC clock activation time
89 - gpmc,wait-monitoring-ns: Start of wait monitoring with regard to valid
90 data
91
92Boolean timing parameters. If property is present parameter enabled and
93disabled if omitted:
94 - gpmc,adv-extra-delay: ADV signal is delayed by half GPMC clock
95 - gpmc,cs-extra-delay: CS signal is delayed by half GPMC clock
96 - gpmc,cycle2cycle-diffcsen: Add "cycle2cycle-delay" between successive
97 accesses to a different CS
98 - gpmc,cycle2cycle-samecsen: Add "cycle2cycle-delay" between successive
99 accesses to the same CS
100 - gpmc,oe-extra-delay: OE signal is delayed by half GPMC clock
101 - gpmc,we-extra-delay: WE signal is delayed by half GPMC clock
102 - gpmc,time-para-granularity: Multiply all access times by 2
103
104The following are only applicable to OMAP3+ and AM335x:
105 - gpmc,wr-access-ns: In synchronous write mode, for single or
106 burst accesses, defines the number of
107 GPMC_FCLK cycles from start access time
108 to the GPMC_CLK rising edge used by the
109 memory device for the first data capture.
110 - gpmc,wr-data-mux-bus-ns: In address-data multiplex mode, specifies
111 the time when the first data is driven on
112 the address-data bus.
113
114GPMC chip-select settings properties for child nodes. All are optional.
115
116- gpmc,burst-length Page/burst length. Must be 4, 8 or 16.
117- gpmc,burst-wrap Enables wrap bursting
118- gpmc,burst-read Enables read page/burst mode
119- gpmc,burst-write Enables write page/burst mode
120- gpmc,device-width Total width of device(s) connected to a GPMC
121 chip-select in bytes. The GPMC supports 8-bit
122 and 16-bit devices and so this property must be
123 1 or 2.
124- gpmc,mux-add-data Address and data multiplexing configuration.
125 Valid values are 1 for address-address-data
126 multiplexing mode and 2 for address-data
127 multiplexing mode.
128- gpmc,sync-read Enables synchronous read. Defaults to asynchronous
129 is this is not set.
130- gpmc,sync-write Enables synchronous writes. Defaults to asynchronous
131 is this is not set.
132- gpmc,wait-pin Wait-pin used by client. Must be less than
133 "gpmc,num-waitpins".
134- gpmc,wait-on-read Enables wait monitoring on reads.
135- gpmc,wait-on-write Enables wait monitoring on writes.
136
137Example for an AM33xx board:
138
139 gpmc: gpmc@50000000 {
140 compatible = "ti,am3352-gpmc";
141 ti,hwmods = "gpmc";
142 reg = <0x50000000 0x2000>;
143 interrupts = <100>;
144 dmas = <&edma 52 0>;
145 dma-names = "rxtx";
146 gpmc,num-cs = <8>;
147 gpmc,num-waitpins = <2>;
148 #address-cells = <2>;
149 #size-cells = <1>;
150 ranges = <0 0 0x08000000 0x10000000>; /* CS0 @addr 0x8000000, size 0x10000000 */
151 interrupt-controller;
152 #interrupt-cells = <2>;
153 gpio-controller;
154 #gpio-cells = <2>;
155
156 /* child nodes go here */
157 };