tjh.dev
Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
1* Renesas Clock Pulse Generator / Module Standby and Software Reset
2
3On Renesas ARM SoCs (SH/R-Mobile, R-Car, RZ), the CPG (Clock Pulse Generator)
4and MSSR (Module Standby and Software Reset) blocks are intimately connected,
5and share the same register block.
6
7They provide the following functionalities:
8 - The CPG block generates various core clocks,
9 - The MSSR block provides two functions:
10 1. Module Standby, providing a Clock Domain to control the clock supply
11 to individual SoC devices,
12 2. Reset Control, to perform a software reset of individual SoC devices.
13
14Required Properties:
15 - compatible: Must be one of:
16 - "renesas,r8a7743-cpg-mssr" for the r8a7743 SoC (RZ/G1M)
17 - "renesas,r8a7745-cpg-mssr" for the r8a7745 SoC (RZ/G1E)
18 - "renesas,r8a7790-cpg-mssr" for the r8a7790 SoC (R-Car H2)
19 - "renesas,r8a7791-cpg-mssr" for the r8a7791 SoC (R-Car M2-W)
20 - "renesas,r8a7792-cpg-mssr" for the r8a7792 SoC (R-Car V2H)
21 - "renesas,r8a7793-cpg-mssr" for the r8a7793 SoC (R-Car M2-N)
22 - "renesas,r8a7794-cpg-mssr" for the r8a7794 SoC (R-Car E2)
23 - "renesas,r8a7795-cpg-mssr" for the r8a7795 SoC (R-Car H3)
24 - "renesas,r8a7796-cpg-mssr" for the r8a7796 SoC (R-Car M3-W)
25 - "renesas,r8a77995-cpg-mssr" for the r8a77995 SoC (R-Car D3)
26
27 - reg: Base address and length of the memory resource used by the CPG/MSSR
28 block
29
30 - clocks: References to external parent clocks, one entry for each entry in
31 clock-names
32 - clock-names: List of external parent clock names. Valid names are:
33 - "extal" (r8a7743, r8a7745, r8a7790, r8a7791, r8a7792, r8a7793, r8a7794,
34 r8a7795, r8a7796, r8a77995)
35 - "extalr" (r8a7795, r8a7796)
36 - "usb_extal" (r8a7743, r8a7745, r8a7790, r8a7791, r8a7793, r8a7794)
37
38 - #clock-cells: Must be 2
39 - For CPG core clocks, the two clock specifier cells must be "CPG_CORE"
40 and a core clock reference, as defined in
41 <dt-bindings/clock/*-cpg-mssr.h>.
42 - For module clocks, the two clock specifier cells must be "CPG_MOD" and
43 a module number, as defined in the datasheet.
44
45 - #power-domain-cells: Must be 0
46 - SoC devices that are part of the CPG/MSSR Clock Domain and can be
47 power-managed through Module Standby should refer to the CPG device
48 node in their "power-domains" property, as documented by the generic PM
49 Domain bindings in
50 Documentation/devicetree/bindings/power/power_domain.txt.
51
52 - #reset-cells: Must be 1
53 - The single reset specifier cell must be the module number, as defined
54 in the datasheet.
55
56
57Examples
58--------
59
60 - CPG device node:
61
62 cpg: clock-controller@e6150000 {
63 compatible = "renesas,r8a7795-cpg-mssr";
64 reg = <0 0xe6150000 0 0x1000>;
65 clocks = <&extal_clk>, <&extalr_clk>;
66 clock-names = "extal", "extalr";
67 #clock-cells = <2>;
68 #power-domain-cells = <0>;
69 #reset-cells = <1>;
70 };
71
72
73 - CPG/MSSR Clock Domain member device node:
74
75 scif2: serial@e6e88000 {
76 compatible = "renesas,scif-r8a7795", "renesas,scif";
77 reg = <0 0xe6e88000 0 64>;
78 interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>;
79 clocks = <&cpg CPG_MOD 310>;
80 clock-names = "fck";
81 dmas = <&dmac1 0x13>, <&dmac1 0x12>;
82 dma-names = "tx", "rx";
83 power-domains = <&cpg>;
84 resets = <&cpg 310>;
85 };