tjh.dev
Linux kernel mirror (for testing)
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1/*
2 * Copyright 2016,2017 IBM Corporation.
3 *
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License
6 * as published by the Free Software Foundation; either version
7 * 2 of the License, or (at your option) any later version.
8 */
9#ifndef _ASM_POWERPC_XIVE_H
10#define _ASM_POWERPC_XIVE_H
11
12#define XIVE_INVALID_VP 0xffffffff
13
14#ifdef CONFIG_PPC_XIVE
15
16/*
17 * Thread Interrupt Management Area (TIMA)
18 *
19 * This is a global MMIO region divided in 4 pages of varying access
20 * permissions, providing access to per-cpu interrupt management
21 * functions. It always identifies the CPU doing the access based
22 * on the PowerBus initiator ID, thus we always access via the
23 * same offset regardless of where the code is executing
24 */
25extern void __iomem *xive_tima;
26
27/*
28 * Offset in the TM area of our current execution level (provided by
29 * the backend)
30 */
31extern u32 xive_tima_offset;
32
33/*
34 * Per-irq data (irq_get_handler_data for normal IRQs), IPIs
35 * have it stored in the xive_cpu structure. We also cache
36 * for normal interrupts the current target CPU.
37 *
38 * This structure is setup by the backend for each interrupt.
39 */
40struct xive_irq_data {
41 u64 flags;
42 u64 eoi_page;
43 void __iomem *eoi_mmio;
44 u64 trig_page;
45 void __iomem *trig_mmio;
46 u32 esb_shift;
47 int src_chip;
48 u32 hw_irq;
49
50 /* Setup/used by frontend */
51 int target;
52 bool saved_p;
53};
54#define XIVE_IRQ_FLAG_STORE_EOI 0x01
55#define XIVE_IRQ_FLAG_LSI 0x02
56#define XIVE_IRQ_FLAG_SHIFT_BUG 0x04
57#define XIVE_IRQ_FLAG_MASK_FW 0x08
58#define XIVE_IRQ_FLAG_EOI_FW 0x10
59#define XIVE_IRQ_FLAG_H_INT_ESB 0x20
60
61#define XIVE_INVALID_CHIP_ID -1
62
63/* A queue tracking structure in a CPU */
64struct xive_q {
65 __be32 *qpage;
66 u32 msk;
67 u32 idx;
68 u32 toggle;
69 u64 eoi_phys;
70 u32 esc_irq;
71 atomic_t count;
72 atomic_t pending_count;
73};
74
75/*
76 * "magic" Event State Buffer (ESB) MMIO offsets.
77 *
78 * Each interrupt source has a 2-bit state machine called ESB
79 * which can be controlled by MMIO. It's made of 2 bits, P and
80 * Q. P indicates that an interrupt is pending (has been sent
81 * to a queue and is waiting for an EOI). Q indicates that the
82 * interrupt has been triggered while pending.
83 *
84 * This acts as a coalescing mechanism in order to guarantee
85 * that a given interrupt only occurs at most once in a queue.
86 *
87 * When doing an EOI, the Q bit will indicate if the interrupt
88 * needs to be re-triggered.
89 *
90 * The following offsets into the ESB MMIO allow to read or
91 * manipulate the PQ bits. They must be used with an 8-bytes
92 * load instruction. They all return the previous state of the
93 * interrupt (atomically).
94 *
95 * Additionally, some ESB pages support doing an EOI via a
96 * store at 0 and some ESBs support doing a trigger via a
97 * separate trigger page.
98 */
99#define XIVE_ESB_STORE_EOI 0x400 /* Store */
100#define XIVE_ESB_LOAD_EOI 0x000 /* Load */
101#define XIVE_ESB_GET 0x800 /* Load */
102#define XIVE_ESB_SET_PQ_00 0xc00 /* Load */
103#define XIVE_ESB_SET_PQ_01 0xd00 /* Load */
104#define XIVE_ESB_SET_PQ_10 0xe00 /* Load */
105#define XIVE_ESB_SET_PQ_11 0xf00 /* Load */
106
107#define XIVE_ESB_VAL_P 0x2
108#define XIVE_ESB_VAL_Q 0x1
109
110/* Global enable flags for the XIVE support */
111extern bool __xive_enabled;
112
113static inline bool xive_enabled(void) { return __xive_enabled; }
114
115extern bool xive_spapr_init(void);
116extern bool xive_native_init(void);
117extern void xive_smp_probe(void);
118extern int xive_smp_prepare_cpu(unsigned int cpu);
119extern void xive_smp_setup_cpu(void);
120extern void xive_smp_disable_cpu(void);
121extern void xive_teardown_cpu(void);
122extern void xive_kexec_teardown_cpu(int secondary);
123extern void xive_shutdown(void);
124extern void xive_flush_interrupt(void);
125
126/* xmon hook */
127extern void xmon_xive_do_dump(int cpu);
128
129/* APIs used by KVM */
130extern u32 xive_native_default_eq_shift(void);
131extern u32 xive_native_alloc_vp_block(u32 max_vcpus);
132extern void xive_native_free_vp_block(u32 vp_base);
133extern int xive_native_populate_irq_data(u32 hw_irq,
134 struct xive_irq_data *data);
135extern void xive_cleanup_irq_data(struct xive_irq_data *xd);
136extern u32 xive_native_alloc_irq(void);
137extern void xive_native_free_irq(u32 irq);
138extern int xive_native_configure_irq(u32 hw_irq, u32 target, u8 prio, u32 sw_irq);
139
140extern int xive_native_configure_queue(u32 vp_id, struct xive_q *q, u8 prio,
141 __be32 *qpage, u32 order, bool can_escalate);
142extern void xive_native_disable_queue(u32 vp_id, struct xive_q *q, u8 prio);
143
144extern void xive_native_sync_source(u32 hw_irq);
145extern bool is_xive_irq(struct irq_chip *chip);
146extern int xive_native_enable_vp(u32 vp_id);
147extern int xive_native_disable_vp(u32 vp_id);
148extern int xive_native_get_vp_info(u32 vp_id, u32 *out_cam_id, u32 *out_chip_id);
149
150#else
151
152static inline bool xive_enabled(void) { return false; }
153
154static inline bool xive_spapr_init(void) { return false; }
155static inline bool xive_native_init(void) { return false; }
156static inline void xive_smp_probe(void) { }
157extern inline int xive_smp_prepare_cpu(unsigned int cpu) { return -EINVAL; }
158static inline void xive_smp_setup_cpu(void) { }
159static inline void xive_smp_disable_cpu(void) { }
160static inline void xive_kexec_teardown_cpu(int secondary) { }
161static inline void xive_shutdown(void) { }
162static inline void xive_flush_interrupt(void) { }
163
164static inline u32 xive_native_alloc_vp_block(u32 max_vcpus) { return XIVE_INVALID_VP; }
165static inline void xive_native_free_vp_block(u32 vp_base) { }
166
167#endif
168
169#endif /* _ASM_POWERPC_XIVE_H */