tjh.dev
Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
1/*
2 * Header file for Intel Broxton Whiskey Cove PMIC
3 *
4 * Copyright (C) 2015 Intel Corporation. All rights reserved.
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms and conditions of the GNU General Public License,
8 * version 2, as published by the Free Software Foundation.
9 *
10 * This program is distributed in the hope it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 * more details.
14 */
15
16#ifndef __INTEL_BXTWC_H__
17#define __INTEL_BXTWC_H__
18
19/* BXT WC devices */
20#define BXTWC_DEVICE1_ADDR 0x4E
21#define BXTWC_DEVICE2_ADDR 0x4F
22#define BXTWC_DEVICE3_ADDR 0x5E
23
24/* device1 Registers */
25#define BXTWC_CHIPID 0x4E00
26#define BXTWC_CHIPVER 0x4E01
27
28#define BXTWC_SCHGRIRQ0_ADDR 0x5E1A
29#define BXTWC_CHGRCTRL0_ADDR 0x5E16
30#define BXTWC_CHGRCTRL1_ADDR 0x5E17
31#define BXTWC_CHGRCTRL2_ADDR 0x5E18
32#define BXTWC_CHGRSTATUS_ADDR 0x5E19
33#define BXTWC_THRMBATZONE_ADDR 0x4F22
34
35#define BXTWC_USBPATH_ADDR 0x5E19
36#define BXTWC_USBPHYCTRL_ADDR 0x5E07
37#define BXTWC_USBIDCTRL_ADDR 0x5E05
38#define BXTWC_USBIDEN_MASK 0x01
39#define BXTWC_USBIDSTAT_ADDR 0x00FF
40#define BXTWC_USBSRCDETSTATUS_ADDR 0x5E29
41
42#define BXTWC_DBGUSBBC1_ADDR 0x5FE0
43#define BXTWC_DBGUSBBC2_ADDR 0x5FE1
44#define BXTWC_DBGUSBBCSTAT_ADDR 0x5FE2
45
46#define BXTWC_WAKESRC_ADDR 0x4E22
47#define BXTWC_WAKESRC2_ADDR 0x4EE5
48#define BXTWC_CHRTTADDR_ADDR 0x5E22
49#define BXTWC_CHRTTDATA_ADDR 0x5E23
50
51#define BXTWC_STHRMIRQ0_ADDR 0x4F19
52#define WC_MTHRMIRQ1_ADDR 0x4E12
53#define WC_STHRMIRQ1_ADDR 0x4F1A
54#define WC_STHRMIRQ2_ADDR 0x4F1B
55
56#define BXTWC_THRMZN0H_ADDR 0x4F44
57#define BXTWC_THRMZN0L_ADDR 0x4F45
58#define BXTWC_THRMZN1H_ADDR 0x4F46
59#define BXTWC_THRMZN1L_ADDR 0x4F47
60#define BXTWC_THRMZN2H_ADDR 0x4F48
61#define BXTWC_THRMZN2L_ADDR 0x4F49
62#define BXTWC_THRMZN3H_ADDR 0x4F4A
63#define BXTWC_THRMZN3L_ADDR 0x4F4B
64#define BXTWC_THRMZN4H_ADDR 0x4F4C
65#define BXTWC_THRMZN4L_ADDR 0x4F4D
66
67#endif